EXAMPLE6.

1: DFF WITH ASYNCHRONOUS RESET #1

q
d

DFF

clk

rst

A DFF as shown above is the most basic building block in sequential ckts. In it
the output must copy the input either at the positive edge or at the negative edge
of the clock pulse.
In the code presented below we make use of the if statement to design a DFF
with asynchronous reset. If rst = ’1’,then the output must be q = ‘0’, regardless of
the status of the clk. Otherwise the output must copy the input that is q = d at the
positive edge of the clk. The EVENT attribute is used to detect a clock transition.
The process is run every time any of the signals that appear in the sensitivity list
(clk, rst) changes.

--------------------- DFF WITH ASYNCHRONOUS RESET #1--------------------

library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------
entity dff is
port (d,clk,rst:in std_logic;
q:out std_logic);
end dff;
--------------------------------------------------------------------
architecture behavior of dff is
begin
process (clk,rst)
begin
if (rst='1') then
q <= '0';
elsif (clk'event and clk='1')then
q <= d;
end if;
end process;
end behavior ;
--------------------------------------------------------------------
EXAMPLE6.2: ONE DIGIT COUNTER #1

COUNTER q
clk

The code below implements a progressive 1-digit decimal counter (0-9-0). A top
level diagram of the circuit is shown in fig. Above. It contains a single-bit
input(clk) and a 4-bit output (digit).The IF statement is used in this example. A
variable, temp was employed to create the four flip-flops necessary to store the
4-bit output signal.

-------------example6.2 one-digit counter #1--------------------

library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------
entity counter is
port (clk : in std_logic;
digit : out integer range 0 to 9);
end counter;
----------------------------------------------------------------
architecture counter of counter is
begin
count: process(clk)
variable temp : integer range 0 to 9;
begin
if (clk'event and clk='1') then
temp := temp+1;
if (temp=10) then temp := 0;
end if;
end if;
digit <= temp;
end process count;
end counter;
----------------------------------------------------------------
EXAMPLE6.3: SHIFT REGISTER
q
d

DFF DFF DFF DFF

clk
rst
Above fig shows 4-bit shift register. The output bit (q) must be four positive clock
edges behind the input bit (d). It also contains an asynchronous reset, which
must force all the FF to output to ‘0’ when asserted. In this example, the IF
statement is again employed.

-----------------example6.3 Shift register ---------------------

library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------
entity shiftreg is
generic (n: integer := 4); -- no of stages
port(d,clk,rst:in std_logic;
q:out std_logic);
end shiftreg;
--------------------------------------------------------------------
architecture behavior of shiftreg is
signal internal:std_logic_vector (n-1 downto 0);
begin
process(clk,rst)
begin
if (rst='1') then
internal <= (others => '0');
elsif (clk'event and clk='1') then
internal <= d&internal(internal'left downto 1);
end if;
end process;
q <= internal(0);
end behavior;
--------------------------------------------------------------------
EXAMPLE6.4: DFF WITH ASYNCHRONOUS RESET #2
The code implements the same DFF of example6.1 and 6.2(refer fig. Of above
example). However here WAIT ON is used instead of IF only.

-------example6.4 dff with asyn reset #2----------------

library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------
entity dff is
port (d,clk,rst:IN STD_LOGIC;
q: out std_logic);
end dff;
-----------------------------------------------
architecture dff of dff is
begin
process
begin
wait on rst,clk;
if (rst='1')then
q<='0';
elsif (clk'event and clk='1')then
q<= d;
end if;
end process;
end dff;
-----------------------------------------
EXAMPLE6.5: ONE DIGIT COUNTER #2
The code below implements the progressive 1-digit decimal counter of example
6.2 (see fig.)
However WAIT UNTIL was used instead of IF only

----------EXAMPLE65 ONE DIGIT COUNTER #2----------------

library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------------
entity counter is
port(clk: in std_logic;
digit: out integer range 0 to 9);
end counter;
---------------------------------------------------------
architecture counter of counter is
begin
process --no sensitivity list
variable temp: integer range 0 to 10;
begin
wait until (clk'event and clk='1');
temp := temp+1;
if (temp=10)then temp:=0;
end if;
digit <= temp;
end process;
end counter;
------------------------------------------------------------------
EXAMPLE6.6: DFF WITH ASYNCHRONOUS RESET #2
The code below implements the same DFF of example6.1 (see fig.). However,
here CASE was used instead of IF only. Notice that a few unnecessary
declarations were intentionally included in the code to illustrate their usage.

-------------------- example6.6 dff with asynchronous reset #3 ---------------------

entity dff is
port (d,clk,rst:in bit;
q: out bit);
end dff;
--------------------------------------------------------
architecture dff3 of dff is
begin
process (clk,rst)
begin
case rst is
when '1' => q <= '0';
when '0' =>
if (clk'event and clk='1') then
q<=d;
end if;
when others => null;-- unnecessary rst is of
type bit
end case;
end process;
end dff3;
------------------------------------------------------------------
 EXAMPLE6.7: TWO-DIGIT COUNTER WITH SSD OUTPUT

EXAMPLE6.6: DFF WITH ASYNCHRONOUS RESET #3

The code below implements the same FF of example6.1(see fig.). H

clk
COUNTER DIGIT2
DIGIT1