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What Are Macros in VLSI?

Macros are pre-built intellectual properties that can be used in chip designs and come in two types: soft macros which are synthesizable RTL that are flexible but unpredictable, and hard macros which are optimized blocks targeted at a specific manufacturing process and imported as GDS2 files.

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Raveen Kumar
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0% found this document useful (0 votes)
979 views1 page

What Are Macros in VLSI?

Macros are pre-built intellectual properties that can be used in chip designs and come in two types: soft macros which are synthesizable RTL that are flexible but unpredictable, and hard macros which are optimized blocks targeted at a specific manufacturing process and imported as GDS2 files.

Uploaded by

Raveen Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
Download as docx, pdf, or txt
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What is a macro?

Macros are intellectual properties that you can use in your design. You do not need
to design it.

For example, memories, processor core, PLL etc. A macro can be hard or soft
macro.

Soft macro and hard macro are categorized as IP.

Soft macros:

Soft macros are used in SOC implementations. Soft macros are synthesizable RTL
form, are more flexible than hard macros in terms of re-configurability. Soft macros
are not specific to any manufacturing process and have the disadvantage of being
unpredictable in terms of timing, area, performance, or power. Soft macros carry
greater IP protection risks because RTL source code is more portable and therefore,
less easily protected than either a netlist or physical layout data. Soft macros are
editable and can contain standard cells, hard macros, or other soft macros.

Hard macros:

Hard macros are targeted for specific IC manufacturing technology. They are block
level designs which are optimized for power or area or timing and silicon tested.
While accomplishing physical design it is possible to only access pins of hard
macros unlike soft macros which allow us to manipulate the RTL. Hard macro is a
block that is generated in a methodology other than place and route and is imported
into physical design database as a GDS2 file.

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