Computer Architecture and Organization

Input/ Output Organization

1.0 Introduction :
The input and output modules play very important part in a computer system. These are
the modules through which the computer interacts with the external environment. The users feed
in programs, data, and commands and the computer provides the results/ reports for use by the
user.

As computers have a wide variety of applications and they are used in different kinds of
environments there are wide variants of input/ output devices with vastly differing characteristics
found in use in computer systems. These devices may vary in their speed of operation, in the
format of the data they input/ output, in the size of the data unit they exchange, in the way they
interact with the computer system etc. Not to speak of devices differing in functionality, devices
with the same functionality may also differ in their mode of interaction. The architecture of the
computer system must be flexible enough to accommodate devices widely varying in
characteristics. The input/ output modules have to be organized incorporating mechanisms such
that these devices can be connected to it and can exchange data. To the same computer system it
should be possible to connect a keyboard transferring one character at-a-time at a rate of a few
characters per second, a storage device transferring data in large blocks at a rate of several
megabytes per second, or a network interface transferring data in even larger blocks at rates that
may go beyond gigabits per second. On top of it there are also variations within the I/O devices
with the same functionality but produced by different manufacturers.

Some of the ways in which the I/O devices differ are-

1. Speed of Data Transfer: Ranging from a few bytes per minute in telemetry devices or a
few bytes per second in a keyboard to some gigabits per second
for data communication devices or high speed storage devices.

2. Interface:
a. Serial/ parallel: Single bit at-a-time or multiple bits at-a-time.
b. Connector: Type of connector.
c. Protocol: Steps involved in the transaction of data.

3. Unit of data transferred:

a. Character/ byte: Data bits transferred grouped in units of bytes.
b. Block: Data bits transferred grouped in hundreds of thousands of bits.

It is difficult for a processor to deal directly with devices having widely varying
characteristics and interfaces. Therefore the computer systems add a buffer set of interfaces,
called I/O Interface, between the processor and the I/O devices. These interfaces provide a
uniform interface to the processor on one side while on the other side each of these provides an
interface as appropriate for the device(s) it serves.

The I/O interfaces are often connected to the processor and the memory unit by a
common set of data and control signal lines referred to as the Bus or the System Bus as shown in
Figure-1. The uniform side of the I/O interface is connected to the bus. The processor and the
memory also have compatible interfaces to the bus to enable transfer of data and control
information.

PROCESSOR MEMORY

SYSTEM BUS

o o o
INTERFACE INTERFACE INTERFACE INTERFACE

I/O
I/O DEV
I/O
DEV DEV I/O I/O
DEV DEV
I/O I/O
DEV DEV
I/O BUS I/O I/O
DEV DEV
I/O I/O I/O
DEV DEV DEV

Figure-1: I/O Interface

The other side of an I/O interface is connected to one or more I/O devices using an I/O Bus that
is compatible to the interface on the device(s) concerned.

2.0 The System Bus:

The system bus consists of a common set of signal lines shared by the interfaces for exchange of
data and control information. These signal lines can be categorized in the following groups:

1. Address Lines,

2. Data lines,

3. Control lines.

In addition there may be a set of utility lines such as power supply.

3.0 The I/O Interface:

The I/O Interface consists of the following:

1. System Bus Interface: The system bus interface consists of a set of registers and a decoder
logic circuitry. The typical set of registers are-
i. Data Register(DR) : To hold the data transferred to/ from the processor/ memory.
In interfaces for faster devices there could be a number of
data registers
ii. Status Register(SR): To hold the status information about the I/O device and its
interface. The status information includes readiness of the
interface for taking the next command, if the device is
connected/ powered on, working/ developed fault, expecting
attention of the processor etc. Bits in the status register are
assigned to represent these information.
iii. Command/ Control Register(CR): To hold the command issued by the processor to
the interface.
Each of the registers is identified by a unique address. The decoder logic decodes address
specified on the bus to select the appropriate register for transfer of data, status, or a
command.
2. Control logic circuitry : Logic circuitry to interpret the commands issued by the processor and
to carry these out, to perform the house keeping operations in the
interface and to update the status register with the status information
on the device(s) it serves.

3. Device Interface : Interface with the I/O device possibly as per an I/O bus standard.

3.1 I/O Address Space:

The collection of the addresses of the registers in the I/O interfaces constitutes the I/O Address
Space. The I/O address space is organized in one of the two ways-
1. Memory mapped I/O: In this organization the addresses of the registers in the I/O
interfaces are mapped to an area in the memory address space
itself. As a result read/write operations on the I/O interface
registers can be performed as in case of memory locations. There is
no need for separate control signal lines in the bus for I/O read/
write operations. All the processor instructions available for
memory operands can also be used for I/O operands.

Memory
Locations I/O
Memory
Registers
Locations
I/O
Registers
 Memory mapped I/O Isolated I/O

2. Isolated I/O: In this the I/O address space is totally independent of the memory
address space. For the read/ write operations on the I/O interface
registers there is a separate set of control signal lines provided in
the bus. There is also a separate set of instructions provided in the
instruction set for these operations. The disadvantage is lesser
flexibility in programming. The advantage is that the memory
address space is not fractured and the entire space is available for
memory purpose.

4.0 Modes of I/O Transfer:

There are basically three modes of transfer of data to and from I/O interfaces. These are-
1. Program Controlled I/O
2. Interrupt Driven I/O
3. Direct Memory Access
4.1 Program Controlled I/O
In program controlled I/O the transfer of data is entirely carried out by the processor under the
control of an I/O program routine. For example, in case of an output operation, i.e. transfer of
data to an output device such as a printer, the output routine reads a data element from the
memory location holding the data and writes in onto the data register of the interface. Before
performing the write operation the processor checks the status register in the interface to see if
it is ready for the operation. After the write operation on the data register done by the processor
the interface control logic clears the ready bit in the status register and initiate the process of
transferring the data element to the output device. After transferring the data the interface sets
the ready bit in the status register to indicate that it is ready to receive the next data element.
The processor then writes the next data element on finding the ready bit in the status register
on. This process is repeated until the entire data block is transferred to the device. A typical
output routine performing transfer operation to a printer can be as follows:
data_seg segment
data db 1000 dup(?) ; Data block in memory
data_size dw 500 ; Size of the data block
ready_mask db 01 ; Ready bit mask
printer_sr db 10 ; Printer interface status register address
printer_dr db 11 ; Printer interface data register address
data_seg ends

code_seg segment
-
-
-
mov si, offset data
mov cx, data_size
mov dx, printer_sr
mov bx, printer_dr
print_loop: and [dx], ready_mask
jz print_loop
mov al, [si]
mov [bx], al
inc si
 dec cx
jnz print_loop
-
-
-
code_seg ends

The problem with this mode of data transfer is due to the speed mismatch between the
processor and the I/O devices. For example, a printer with a speed of 150 cps (say) each
character takes about 7 ms. It will be possible for the interface to transfer a character to the
printer once in every 7 ms. Even if we assume that each m/c instruction requires 1 μs the print
loop will require only 7 μs. After completing the transfer of one character in 7 μs the processor
has keep checking for the printer interface to become ready for about 7 ms in what is known as
the Busy Wait loop doing nothing useful. This is rather wasteful.

4.2 Interrupt Driven I/O:

Interrupt driven I/O tries to do away with the inefficient Busy Wait loop of the processor. Here
the processor transfers one data unit and than goes on to carryout some useful work in the form
of executing another program. Once the data unit is transferred to/ from the I/O device and the
I/O interface is ready to receive/ deliver the next data unit it sends a signal to the processor
indicating its readiness. This signal is called an Interrupt Request. The interrupt request signal
is sent through a signal line meant for the purpose also known as the Interrupt Request Line.
On receiving the Interrupt Request signal the processor interrupts the process under execution
and gives its attention to the I/O interface that raised the interrupt request. This it does by
transferring control to a routine maintained for the purpose called the Interrupt Service
Routine(ISR). There is one ISR maintained for every device or the devices of the same
category. The ISR checks if the data transfer is complete. If not, it transfers the next data unit
and then returns control to the interrupted program to resume its execution.

As can be seen, in this mode of data transfer the processor does not waste time in a busy wait
loop. This mechanism works fine for the slow I/O devices. For faster I/O devices that require
transfers at rates of megabytes per second, however, transfer of one data unit per execution of
the ISR is not efficient as a good number of instructions are required to be executed in every
unit of data transfer. For that matter, involving the processor for every byte of data transfer
itself becomes very inefficient. This is because in the process of the processor transferring the
data there are two bus cycles involved. In one the processor transfers the data from the memory
to a processor register and in the other it transfer the data from the register to the I/O interface.

4.3 Direct Memory Access (DMA):

In DMA the I/O interface is made to perform the actual transfer of the individual bytes of the
data to/from the memory unit. The processor through the ISR initiates the I/O operation by
supplying the start address of the data block in memory and the size of the data block to be
transferred to the I/O interface and specifying the operation to be performed. The interface than
performs the transfer of the data units in the data block one by one on its own by directly
accessing the memory unit without involving the processor. While this I/O data transfer
operation is carried out by the I/O interface the processor makes itself busy in the execution of
some other process. After the entire data block transfer is completed the interface raises the
interrupt request signal to intimate this information to the processor. The processor, on receipt
of the interrupt request, interrupts the process under execution and checks for the next
command to be given to the interface raising the interrupt and after giving the command to the
interface it resumes execution of the interrupted process.
 The DMA mechanism brings in efficiency in the following ways-
1. It reduces the number of bus cycles required for a block of data transfer to/from an I/O
device to half.
2. Reduces the overhead of instruction execution in the ISR per unit of data transfer as the
ISR needs to be executed only once for a large block of data instead of every byte/word of
data transfer.
3. Frees the processor from I/O data transfer activity and allows it to devote its time in useful
process activities and makes multiprogramming possible.

4.4 Interrupt Mechanisms:

The basic interrupt mechanism in a computer typically consists of the following:

1. There is an Interrupt Request (IRQ) signal line on the bus that allows an I/O interface to
raise an interrupt request.
2. There is an Interrupt Acknowledgement (INTA) signal line using which the processor
indicates acceptance of to the interrupt request.
3. The processor interrupts the program currently under execution, saves the current PC &
PS in the stack and transfers control to the ISR meant for the I/O device concerned.
4. After completion of execution of the ISR the processor restores the saves PC & PS so as
to resume execution of the interrupted program.

4.4.1 Multiple Interfaces with Interrupt Capability:

To allow more than one interface in the computer system to have interrupt capability there are
different possibilities:
1. Provide one IRQ signal line for each interface,
2. Let multiple interfaces share one IRQ signal line.

In the first case the IRQ signal line itself identifies the interrupting device interface. Therefore
the processor can chose the appropriate ISR for servicing of the interrupt request raised. In the
second case, however, there is need for mechanism to resolve the identity of the interrupting
device. The following are the mechanisms for interrupt identification:

Polling: In this one of the bits in the status register is used to indicate that the interface has raised
an interrupt. The processor on receipt of an interrupt request reads the status registers of the
interfaces one by one and thus identifies the interrupting interface.
Vectored Interrupt: An interrupt vector consists of the Start Address (PC) & Processor Status
(PS) pair for the ISR of an interface. The interrupt vectors of the interfaces are typically
maintained in an Interrupt Vector Table. Each interface is assigned an identification code which
basically acts as a pointer to the interrupt vector of the interface in the table. When the processor
raises the INTA signal the interrupting interface places its identification code on the data bus.
The processor reads this code and uses this to extract the interrupt vector (PC & PS) of the
interrupt and then transfers control to the ISR of the interface. The interrupt vectors are usually
maintained in a table called the Interrupt Vector Table (IV-table). The interrupt identification
code acts as a pointer to relevant entry in the IV-table.

4.4.2 Simultaneous Interrupts/ Interrupt Priority Mechanisms:

When there are multiple I/O interfaces capable of raising interrupt request there is possibility
that more than one interface raise interrupt request at the same time. In such a situation the
processor has to decide to which interface it will service first. While one interface is serviced
the other ones have to wait for their turn. Hence there is a question of priority that comes up.
The system must therefore have an Interrupt Priority mechanism. Some of the possible
mechanisms are-

4.4.2.1 Priority Levels: In case there are different interrupt request lines each interrupt
request line is assigned a priority level. When more than one interface raises interrupt
requests simultaneously the processor compares the priority levels of the
corresponding interrupt request lines and responds to the interface using the IRQ with
higher priority by sending INTA to that interface.

4.4.2.2 Daisy Chaining of Interrupt Acknowledgement: When more than one interfaces share
an IRQ signal line they also share the same INTA signal line. The INTA signal line is
however daisy chained through the interfaces, that is, the INTA signal line enters one
interface, goes through its logic circuits, comes out to enter the next interface . . . .
The INTA signal can therefore propagate through the interfaces. An interface,
however, does not allow the signal to propagate through it if it is one of the interfaces
raising interrupt request. Thus, the first interface in the chain among the interfaces
raising IRQ receives the INTA signal and gets the chance to place its identification
code on the data bus to obtain service from the processor while the rest have to wait
for their turn. Hence the sequence of the interfaces in the daisy chain defines the
interrupt priority among the interfaces sharing the IRQ, INTA pair. The priorities of
the interfaces are as per their position in the daisy chain and the one nearest to the
processor has the highest priority.

IRQ
Processor
INTA
Interface1 Interface2 Interface N

Daisy Chain

4.4.3 Nested Interrupts:

The I/O interfaces are used for different devices serving wide variety of applications. Some
devices have a higher urgency in receiving the attention of the processor than the others. For
example, an interface involved in a real-time control system has a deadline before which it has
to respond to certain input from the system. Similarly, an interface for a high-speed storage
device needs to transfer data blocks to/ from the device as per time constraints of the device. In
contrast, some of the other devices, particularly the slower ones such as printer, keyboard, etc.
do not have any hard time constraints. Thus it is possible to order the devices in terms of their
urgency in receiving attention/ service from the processor. In case the ISR of a device with
lower urgency is under execution and a device with higher urgency raises an interrupt request,
it may be necessary that the execution of the current ISR is interrupted to allow execution of
the ISR of the device with higher urgency. Once execution of this ISR is complete the control
has to be returned to the previous ISR so that the servicing of that device can be completed.
Such execution of an ISR during execution of another ISR is referred to as nesting of
interrupts. From execution point of view this nesting is similar to that of subroutines.
Therefore, here too stack is used for saving the PC & PS of the current ISR before transferring
control to next ISR. As in case of nesting of subroutines here too several levels of nesting is
possible for interrupts.
 There is however another important aspect to this nesting of interrupts. The processor should
attend to an interrupt request only if the device raising interrupt request is of higher urgency
than the one that is currently being served. To ensure this the processors use an interrupt
priority mechanism. As per the urgency of the devices their interfaces are assigned interrupt
priority codes. The device interfaces with the same priority codes are grouped together and
they share the same IRQ, INTA pair while those with different priority codes are assigned

IRQ1
INTA1

IRQ2
INTA2
Processor

IRQ3
INTA3

different IRQ, INTA pairs. Some designated bits in the processor status register are used to
hold the priority of the process under execution. The interrupt priority of the device being
served is assigned to this process priority. This is done through the Interrupt Vector while a
new interrupt vector (PC & PS value pair) is loaded before execution of an ISR begins. When
the code under execution is not an ISR the priority bits in the PS are normally set to 0(zero) so
that the processor can respond to any interrupt that may occur.

4.4.4 Steps involved in the process of interrupts:

The steps involved in the process of interrupts in case of Vectored Interrupt mechanism are as
follows:

1. The I/O interface raises the IRQ

2. The processor starts interrupt processing by comparing the priority level of the IRQ
with the priority level in PSR. If the priority level of the IRQ is found to be higher
than it interrupts the current process, saves its PC and PS in the stack and issues the
appropriate INTA. Else the interrupt processing is deferred until the priority level in
PSR is modified.
3. In response to the INTA the interrupting interface places its identification code on the
data bus and removed the IRQ.
4. The processor reads identification code from the bus, extracts the interrupt vector
from the IV-table, modifies PC and PSR accordingly to transfer control to the IRS of
the I/O device.
5. The ISR is executed to provide the required service to the device.
6. On completion of execution of the ISR the saved PC, PS values are restored so that
execution of the interrupted process is resumed.

4.4.5 Provision for Interrupts in the Instruction Execution Loop:

 In the instruction execution loop it is necessary to provide for recognition of the event of
raising of an interrupt request. Normally it is done by the control unit of the processor checking
the IRQ lines after the completion of execution of an instruction or before starting of fetching
of a new instruction. The instruction execution loop is modified as follows:

Repeat
If Interrupt Request raised Process Interrupt
MAR ← PC
PC++
Read
IR ← MDR
Execute
Until IR = Halt
At the beginning of the loop the control unit checks the interrupt request lines made available
at its inputs. If it finds any of the IRQs raised it jumps to a routine that processes the interrupt
and then returns to the repeat loop for normal instruction execution. Note that interrupts are not
recognized during the execution of an instruction.

4.4.6 Triggering of Interrupts:

After an interface raises an IRQ the processor has to recognize it and then respond to it. The
state or the transition in the IRQ signal that causes the processor to recognize the occurrence of
an interrupt request is called triggering of the interrupt. Some interrupts are triggered by the
IRQ signal being in the active state (High- in case of active high, Low- in case of active low).
This is called Level Triggering. In others the triggering is caused by a transition in the IRQ
signal, either from low to high or from high to low. This is called Edge Triggering.

Triggering becomes important when nested interrupts are supported. In case of level triggering
after an interrupt request is recognized and the processor goes on to start execution of its ISR,
just before it executes the first instruction of the ISR the execution loop will check for interrupt
requests. If the interrupt is level triggered the control unit will find the IRQ currently under
process active and shall respond to it again. This will lead to an infinite loop of interrupt
response.

One way to overcome this problem is Edge Triggering of interrupts. The control unit will
respond to an interrupt request only once. Basically the relevant edge of the IRQ signal will set
a flip-flop in the control unit. After the control unit checks the IRQ line it also resets this flip-
flop so that is does not cause a response to the IRQ second time.

The other possibility is that the control unit disables the interrupts by masking all the IRQ lines
at its input on recognition of an IRQ. The interrupts are enabled again by executing an
Interrupt Enable(IE) instruction provided in the instruction set. The IE instruction can be
placed at the beginning of the ISR if interrupt nesting is to be allowed.

4.5 Exceptions:
 Exceptions refer to an event occurring internal to the processor that causes an interruption to
the execution of the current program. Some examples of exceptions are-

1. Occurrence of an illegal instruction.

2. Occurrence of a Bus Error/ Page Fault.
3. Occurrence of divide by zero condition
4. Causing a Trap such as- Breakpoint, Trace etc. for debugging purpose.

When an exception occurs a routine provided for handling the specific condition gets executed.

• An illegal instruction exception occurs when the processor encounters an illegal

instruction. A routine that perhaps prints a message like “Illegal Instruction
Encountered” and then terminates the program is executed.
• A bus error occurs when a bus cycle is initiated at an address that is physically not
available. The ISR may print a message like “Bus Error” and then terminate the
program.
• A page fault is a condition that occurs in virtual memory when an operation is initiated
on a memory location in a page that has not been loaded to the physically memory. The
ISR will locate the page in the virtual memory and load it to the physical memory so
that the memory access can be completed.
• A divide by zero condition occurs when in a divide operation the divisor turns out to be
a zero. As there is no binary representation for infinity a routine has to take an
appropriate action. The ISR does that.
• Traps are often used for debugging or certain analysis purposes. Normally when a
program gets control of the processor it continues execution until completion or a fault
condition occurs. For debugging a program it is necessary to know the status of the
variables of the program at different points in its execution. To do that the program has
to be halted at desired points and control is transferred to the analysis/ access routine.
Once the job is done the control is transferred back to the program. Special trap
instructions are provided in the instruction set of a processor. The appropriate trap
instruction is inserted into the program at appropriate point. The ISR transfers control
to the debugger program.

4.6 Software Interrupts:

A software interrupt is caused by execution of an instruction provided for the purpose.
Execution of software interrupt instruction causes execution of an ISR as for a Hardware
Interrupt. After completion of execution of the ISR control returns to the interrupted program.
Therefore it is, in a way, like execution of a subroutine. However its difference w.r.t. a
subroutine call lies in the following:

1. The program causing the software interrupt does not provide the address of the routine.
This is obtained from the Interrupt Vector.
2. Before transferring control to the IRS the Processor Status Register (PSR) content is
changed with that provided in the interrupt vector.

The usefulness of software interrupt also lies in these. Normally software interrupts are used by
application programs for obtaining operating system services. The OS services are encoded in
routines within the OS. The memory addresses of these routines are not known to the
applications. Therefore these routine cannot be executed by the application programs through
subroutine calls. However these addresses can be made available to the ISR for a software
interrupt and thus provide access to these routines to the application programs.
There is another important aspect associated with execution of OS service routines. The OS
service routines can be executed only with a higher privilege level than that of an application
level program. That is because an application level program should not be allowed direct
access to the system resources. This restriction is required to protect these resources from
unauthorized malicious access as well as faulty access by untested and defective code.
Therefore only tested OS service routines are allowed access to the sensitive resources in the
system. The privilege level of a process is encoded in some of the bits in the processor status
register. When a new PS value given in the interrupt vector is loaded to the PSR before
transferring control to the ISR of the software interrupt, the process assume the privilege level
required for execution of the OS service routine. This change in privilege level of the process
from application or user level to that of OS or Supervisory level is called a Context Switch- a
switch of context from application or user context to an OS or supervisory context. This
context switch occurs is case of all interrupts as well as exceptions. At the completion of
execution of the ISR a reverse switch from supervisory context to user context occurs.

A software interrupt differs from a (hardware) interrupt in that-

1. Identification of the interrupt is automatic from the interrupt instruction. Hence the
interrupt vector can be readily extracted from the IV-table.
2. In software interrupt the task performed by the ISR is initiated by the process under
execution and is very much a part of it. In case of hardware interrupt the task
performed by the IRS executed due to the interrupt may be caused by an event not due
to the interrupted process under execution and may in no way be related to it.
 4.7 Direct Memory Access (DMA)

In DMA the I/O interface needs to access the memory unit by itself. Therefore it requires the
capability of driving the bus. This includes the ability of becoming a bus master, to generate a
memory address and place it on the bus and issue a read or write command to the memory unit.
To become a bus master there are protocols and mechanisms that shall be discussed later.

Normally, a DMA interface is used in devices that require transfer of data in blocks. Therefore
it needs to generate the addresses of consecutive locations in a block of memory starting at a
given location. For this it needs to know the start address of the block and the size of the block.
A counter can be used to generate the consecutive addresses. For this a DMA interface
typically has the following:

1. a start address register,

2. a word count/ block size register,
3. an address counter, and
4. the normal set of I/O interface registers, namely, data register, command register, and
status register

The typical DMA process is as follows:

• The ISR for the interface running on the processor transfers the start address of the
memory block for data transfer and the size of the data to be transferred to the start
address register and the word count/ block size register respectively in the interface and
then writes the command in the command register of the interface. After that the ISR
transfers control of the processor to the interrupted program.
• On receiving the command the interface performs the data transfer as follows:

1. Clears the ready bit in the status register in the interface.

2. Transfers the start address to the address counter.
3. Gets mastership of the bus, enables the address count content on to the
address bus and initiates read or write operation on the memory location as per
the command.
4. Performs a data transfer operation from the interface data register to I/O
device if the command specifies a data transfer operation from memory to
device/ Performs a data transfer operation from I/O device to the interface data
register if the command specifies a data transfer operation from device to
memory.
5. On completion of the memory operation release the bus mastership,
increment the address counter, decrement the word counter.
6. Repeat steps 3 to 6 until the word count becomes zero.
7. Set the ready bit and write the successful completion code in the interface
status register.
8. Raise an interrupt request.

4.7.1 Modes of DMA:

A DMA interface performs data transfer operations in one of the two following modes-

1. Cycle Stealing Mode: In this mode normally the processor is assumed to be the bus
master. When the bus is not in use by the processor, the DMA interface gets hold of
 the bus, performs one bus cycle for memory operation and then releases the bus.
This mode is normally used in interfaces for slower devices.

2. Burst/ Block Mode: In this mode the interface obtains bus mastership, performs a
burst of data transfers to/from memory and then releases the bus. This is normally
used in high speed devices. To operate in this mode the interface maintains a data
buffer capable of holding several bytes/ words of data instead of a single data
register.