Generating, Optimizing and Verifying

HDL Code with MATLAB and Simulink

Puneet Kumar
Application Engineering Team

© 2012 The MathWorks, Inc.1

Agenda
 Integrated Workflow for FPGA/ASIC Development

 Automatic HDL Code Generation & Optimization

– Refining DUT from floating to fixed point
– Automatic HDL Code Generation from MATLAB, Simulink, and Stateflow

 Integrated HDL Verification

– Automatically Measuring Test Coverage
– Generating Co-Simulation Test benches
– FPGA-in-Loop Verification with Xilinx ML 605 FPGA Board

 Q&A

2
Algorithm Development Process
Requirements

Research & Design

 Explore and discover Design

Test
 Gain insight into problem

Test & Verification

Elaborate
 Evaluate options, trade-offs

Implementation

Desktop Embedded
Design
.dll C, C
C++
Test
.exe VHDL / Verilog
Elaborate
.c,
C, .cpp
C++ Structured Text

3
The Algorithm Design Challenge

 How can we: MATLAB

Algorithm Design
– Implement designs
faster?

– Reuse designs on a
variety of hardware?

FPGA
MCU ASIC
DSP FPGA ASIC

4
Solution: C and HDL Code Generation

 Design, execute, and verify MATLAB

algorithms in MATLAB Algorithm Design

 Automatically generate C or MATLAB Coder HDL Coder

HDL code

Generate

Generate
 Deploy generated code on
hardware

C VHDL/Verilog

FPGA
MCU ASIC
DSP FPGA ASIC

5
Code Generation Products for VHDL/Verilog

HDL Coder™
HDL Coder Automatically generate VHDL or Verilog
from MATLAB code and Simulink Model

MATLAB® Coder™
MATLAB Coder Automatically generate C and C++ from
MATLAB code

Fixed-Point Designer™
Fixed-Point Designer provides fixed-point data types and
arithmetic

6
 Best Practice 1:
Algorithm and System Design
with Fixed-Point Quantization Analysis

Use modeling and simulation to

optimize at the system level
using Simulink and Simulink Fixed Point

7
 Best Practice 1:
Algorithm and System Design
with Fixed-Point Quantization Analysis

Best Practice 2:
Automatic
HDL Code Generation

Automatically generate readable, traceable HDL code

for FPGA and ASIC designs
using HDL Coder

8
 Best Practice 1:
Algorithm and System Design
with Fixed-Point Quantization Analysis

Best Practice 2:
Best Practice 3:
Automatic
HDL Cosimulation
HDL Code Generation

Reuse system-level test benches with

cosimulation for HDL verification
using HDL Verifier

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 Best Practice 1:
Algorithm and System Design
with Fixed-Point Quantization Analysis

Best Practice 2:
Best Practice 3:
Automatic
HDL Cosimulation
HDL Code Generation

Enable regression testing

Implement Design with FPGA-in-the-loop simulation
using HDL Verifier

Best Practice 4:
FPGA Hardware-in-the-Loop

10
Audio Equalizer
(A Brief Example)

11
Semtech Speeds Development of
Digital Receiver FPGAs and ASICs

Challenge
Accelerate the development of optimized digital
receiver chains for wireless RF devices The Semtech SX1231 wireless transceiver.

Solution
Use MathWorks tools for Model-Based Design to
generate production VHDL code for rapid FPGA “Writing VHDL is tedious, and the
and ASIC implementation handwritten code still needs to be
verified. With Simulink and Simulink
Results
HDL Coder, once we have simulated
 Prototypes created 50% faster
 Verification time reduced from weeks to days the model we can generate VHDL
 Optimized, better-performing design delivered directly and prototype an FPGA. It
saves a lot of time, and the generated
code contains some optimizations we
hadn’t thought of.”
Frantz Prianon
Semtech

12
HDL Coder
Generate VHDL and Verilog Code for FPGA and ASIC designs

New: MATLAB to HDL

MATLAB Simulink
 Automatic floating-point to
fixed-point conversion

HDL  HDL resource optimizations

Coder and reports

 Algorithm-to-HDL traceability

 Integration with simulation &

Verilog and VHDL synthesis tools

13
Model-Based Design flow using MATLAB/Simulink
from Algorithm to FPGA Implementation

MATLAB® and Simulink®

Algorithm and System Design

DESIGN

HDL Coder HDL Verifier Algorithm MATLAB

RTL Creation HDL Co-Simulation Development Simulink
Stateflow

RTL Back Annotation

Implement Design Verification

Functional Simulation
Synthesis
Static Timing Analysis
Map
Timing Simulation
Place & Route

HDL Verifier
FPGA in the Loop
14
Algorithm to HDL Workflows

1. Simulink to HDL
(with MATLAB and Stateflow)
2. MATLAB to HDL 1
2
3. Hybrid workflow

VHDL &
VHDL & Verilog
Verilog
15
Using HDL Coder: 5-Step Workflow
Prepare your MATLAB algorithm for code generation
Prepare • Use supported language features
• Make implementation choices

Fixed-Point MATLAB code generation from your

floating-point design using your MATLAB
*_FixPt.m TestBench
• Accelerate TestBench for fast simulation
Fixed-Point *_wrapper_FixPt.m • Automatically propose Fixed-Point type
*_tb_FixPt.m • Iterate data-type customization to optimize
• Verify Fixed-Point code against original Floating-Point
code.

Generate synthesizable RTL & TestBench code from

Generate *.vhd, *.v Fixed-Point MATLAB code for final use
*.do, *.tcl • Iterate your MATLAB code to optimize
• Implement as source, executable or library

Simulation the generated HDL code with test vectors

Simulate *.wlf, *.txt from the test bench using the specified
simulation tool

Synthesis, Place and Route the generated RTL code

by creating project with ISE/Quartus II
Synthesis, • Check timing analysis report to optimize
*.edf, *.edn
P&R
*.bit
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Simulink Library Support for HDL
HDL Supported Blocks
 180 blocks supported

 Core Simulink Blocks

– Basic and Array Arithmetic, Look-Up Tables,
Signal Routing (Mux/Demux, Delays,
Selectors), Logic & Bit Operations, Dual and
single port RAMs, FIFOs, CORDICs, Busses

 Signal Processing Blocks

– NCOs, FFTs, Digital Filters (FIR, IIR, Multi-
rate, Adaptive), Rate Changes (Up &Down
Sample), Statistics (Min/Max)

 Communications Blocks
– Psuedo-random Sequence Generators,
Modulators / Demodulators, Interleavers /
Deinterleavers, Viterbi Decoders

17
Agenda
 Integrated Workflow for FPGA/ASIC Development

 Automatic HDL Code Generation & Optimization

– Refining DUT from floating to fixed point
– Automatic HDL Code Generation from MATLAB, Simulink, and Stateflow

 Integrated HDL Verification

– Automatically Measuring Test Coverage
– Generating Co-Simulation Test benches
– FPGA-in-Loop Verification with Xilinx ML 605 FPGA Board

 Q&A

18
From Algorithm to Synthesizable RTL
MATLAB® and Simulink®
Algorithm and System Design
Model Refinement for Hardware

Automatic HDL
HDL Co-Simulation
Code Generation
Behavioral Simulation

Back Annotation

Implement Design Verification

Functional Simulation
Synthesis
Static Timing Analysis
Map
Timing Simulation
Place & Route

FPGA Hardware
FPGA-in-the-Loop

19
Best Practice 1
Use modeling and simulation to optimize at the system level
Optimize on fixed-point
word-length to reduce
area and power

 Convert floating point to optimized fixed-point models

– Automatic tracking of signal range (also intermediate quantities)
– Word / Fraction lengths recommendation
 Bit-true models in the same environment
20
Best Practice 2
Automatically generate readable, traceable HDL code for
FPGA and ASIC designs

Automatically generate bit true,

cycle accurate HDL code from
Simulink, MATLAB and Stateflow

Full bi-directional
traceability!!

Requirements

21
Speed optimization
Use pipelining to improve speed

Critical Path highlighting makes it

easier to identify the true
bottlenecks of the system

Advanced Pipelining options for

pipeline distribution and automatic
delay compensation

22
 Area optimization
Use sharing and streaming to reduce area

Automatically generated
validation models

Use sharing
and streaming
to reduce area

Multipliers 10
Adders/Subtractors 36
Registers 292 Resource utilization reports
provide early feedback on
RAMs 2 resource utilization
Multiplexers 116
23
Agenda
 Integrated Workflow for FPGA/ASIC Development

 Automatic HDL Code Generation & Optimization

– Refining DUT from floating to fixed point
– Automatic HDL Code Generation from MATLAB, Simulink, and Stateflow

 Integrated HDL Verification

– Automatically Measuring Test Coverage
– Generating Co-Simulation Test benches
– FPGA-in-Loop Verification with Xilinx ML 605 FPGA Board

 Q&A

24
Which tests do you
perform today?

25
 Verification Landscape:

Model VHDL / Verilog FPGA

 Requirements  Requirements  Equivalence
 Functional  Equivalence  Regression
 Equivalence  Coverage  Timing Analysis
 Coverage  Assertions
 Property Proving
 Virtual Platforms

26
Verification Challenges:
Stimuli-Driven Test Bench in HDL Simulators

 Digital waveforms are difficult to analyze

– Application specific analysis methods are needed
 How to get test vectors to achieve 100% test coverage?
– Formal methods to derive required test cases
27
 Verification Landscape Solution:
Re-use System Level Test Bench

Model VHDL / Verilog FPGA

 Requirements  Requirements  Equivalence
 Functional  Equivalence  Regression
 Equivalence  Coverage  Timing Analysis
 Coverage  Assertions
 Property Proving
 Virtual Platforms

28
 Audio Equalizer
• Bank of 10 filters
• Controllable by up to +/-6dB
• 5 pre-programmed user settings for
• Rock, Pop, Jazz, Classical, Vocal
• Fits into available FPGA space
• No dead-locks or unreachable states
• Sounds good

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Automatically Measuring Test Coverage
Audio Equalizer

Automatically
collect and report
test coverage

Missed 100%
coverage coverage

30
Test Generation for 100% Coverage
Audio Equalizer

Not the same as HDL

code coverage

Automatically generate
tests to reach coverage
objectives

31
Integrate with HDL Code Coverage
Audio Equalizer

Re-use test benches for

equivalence checking
--and--
code coverage analysis
Integrate with
leading HDL
Simulators

32
 Best Practice 3
Re-use System Level Test Bench for HDL Verification

Model VHDL / Verilog FPGA

 Requirements  Requirements  Equivalence
 Functional  Equivalence  Regression
 Equivalence  Coverage  Timing Analysis
 Coverage  Assertions  On target
 Property Proving prototyping
 Virtual Platforms

33
HDL cosimulation to verify HDL
Re-use System Level Test Bench for HDL Verification

Re-use test benches for Integrate with HDL code

equivalence checking coverage analysis

HDL Cosimulation

Integrate with
Flexible test bench creation: Also works with
Modelsim/Questa
closed loop, multi domain handwritten code
and Incisive

34
 Best Practice 4
Enable regression testing with FPGA-in-the-loop simulation

Model VHDL / Verilog FPGA

 Requirements  Requirements  Equivalence
 Functional  Equivalence  Regression
 Equivalence  Coverage  Timing Analysis
 Coverage  Assertions  On target
 Property Proving prototyping
 Virtual Platforms

35
FPGA-in-the-loop
Enable regression testing with FPGA-in-the-loop simulation
Re-use test benches for Integrate with Altera / Xilinx
regression testing FPGA Development Boards

Flexible test bench creation: Also works with

closed loop, multi domain handwritten code

36
Automation FPGA-in-the-loop Verification
Supported FPGA boards

Integration with FPGA

development boards

Automatic creation of
FPGA-in-the-loop
verification models

37
Additional Methods for Verification
HDL Verification Techniques

 Generate stimuli-based test benches for

standalone verification

 MATLAB based verification

38
Stimuli-based test benches for
standalone verification
MATLAB or Simulink Test bench

MATLAB or Simulink
Stimulus Design Reference Can be used in
Targeted to Hardware Results any HDL
Simulator

Automatically Generated HDL Test Bench

Automatically
generate self-
checking test
Stimulus Actual
benches
HDL Design
Results

39
MATLAB Based Verification

 Re-use the MATLAB test bench

 Accelerate Verification with FPGA Hardware

Stimulus MATLAB Functions Response

Input Output
stimuli response

Input Output
stimuli response

40
FPGA turnkey workflow
FPGA on target prototyping

Music in Music out Integrate with Altera / Xilinx

FPGA Development Boards

Stand alone testing of Automated workflow from

algorithms on FPGA hardware model to FPGA prototype

41
Summary
Best Practice 1:
Algorithm and System Design
with Fixed-Point Quantization Analysis

Best Practice 2:
Best Practice 3:
Automatic
HDL Cosimulation
HDL Code Generation

Implement Design

Best Practice 4:
FPGA Hardware-in-the-Loop

42
FLIR Accelerates Development of
Thermal Imaging FPGA

Challenge
Accelerate the implementation of advanced thermal imaging
filters and algorithms on FPGA hardware
Solution
Use MATLAB to develop, simulate, and evaluate algorithms,
and use HDL Coder to implement the best algorithms on
FPGAs
Results “With MATLAB and HDL Coder we are much
 Time from concept to field-testable prototype more responsive to marketplace needs. We
reduced by 60% now embrace change, because we can take
 Enhancements completed in hours, not weeks a new idea to a real-time-capable hardware
 Code reuse increased from zero to 30% prototype in just a few weeks.
There is more joy in engineering, so we’ve
increased job satisfaction as well as
customer satisfaction.”

—Nicholas Hogasten, FLIR Systems

43
 Public Trainings in the next Few Months
Course Dates Location

Statistical Methods in MATLAB 2 Sep – 3 Sep Bangalore

MATLAB based Optimization Techniques 4 Sep Bangalore

MATLAB Fundamentals 23 Sep – 25 Sep Delhi

Simulink for System and Algorithm Modeling 26 Sep – 27 Sep Delhi

MATLAB Fundamentals 07 Oct – 09 Oct Pune

Simulink for System and Algorithm Modeling 10 Oct – 11 Oct Pune

Generating HDL Code from Simulink 28 Nov – 29 Nov Bangalore

Email: training@mathworks.in URL: http://www.mathworks.in/services/training Phone: 080-6632-600044

Agenda
 Integrated Workflow for FPGA/ASIC Development

 Automatic HDL Code Generation & Optimization

– Refining DUT from floating to fixed point
– Automatic HDL Code Generation from MATLAB, Simulink, and Stateflow

 Integrated HDL Verification

– Automatically Measuring Test Coverage
– Generating Co-Simulation Test benches
– FPGA-in-Loop Verification with Xilinx ML 605 FPGA Board

 Q&A

45
Thank You!

46