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Laboratory #1

Tutorial on Xilinx ISE 10.1

Objectives
• To become familiar with using Xilinx ISE to draw schematic representations of PLD circuits
• To become familiar with using Xilinx ISE to conduct graphical waveform simulations of PLD
circuits
• To become familiar with using Xilinx ISE to write HDL representations of PLD circuits
• To become familiar with using Xilinx ISE to write HDL testbench simulations of PLD circuits
• To become familiar with downloading PLD circuits to the Nexys development board

Introduction
“There is more than one way to do it” (TIMTOWTDI, usually pronounced "Tim Toady") is a
Perl motto. The language was designed with this idea in mind, so that it "doesn't try to tell the
programmer how to program". This makes it easy to write extremely messy programs, but, as
proponents of this motto argue, it also makes it easy to write beautiful and concise ones.

The Zen of Python has a principle which is the exact opposite of TIMTOWTDI: "There should
be one—and preferably only one—obvious way to do it."1

In designing programmable logic, and in the tools used to do so, there is definitely more than one way to
do it.

Part I – Drawing Schematics

The Xilinx Integrated Software Environment (ISE) allows users to design circuits for Xilinx FPGA’s and
CPLD’s. It involves the use of Project Navigator, a user interface that helps users manage the entire
design process including design entry, simulation, synthesis, implementation and finally downloading the
design onto an FPGA or CPLD.

1. Start ISE from the Start menu by selecting Start -> Programs -> Xilinx ISE Design Suite 10.1 ->
ISE -> Project Navigator. The ISE Project Navigator opens as shown in Figure 1. The Project
Navigator lets you manage the sources and processes in your ISE project.

1
Description reprinted from Wikipedia
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Figure 1: Launching ISE Project Navigator

2. The next step is to create a new ISE project. To create a new project for this tutorial:
 Select File -> New Project. The New Project Wizard appears as shown in Figure 2.
 First, enter a Project Location (directory path) for the new project. Choose a location on your USB
drive since files stored on laboratory computers do not persist once the computer shuts down.
 Type counter in the Project Name field. When you type counter in the Project Name field, a
counter subdirectory is created automatically in the directory path you selected.
 Select Schematic in the Top-Level Source Type list, indicating that the top-level file in your
project will be a schematic rather than another type, such as HDL, EDIF or NGC/NGO. Click
Next to go to the Device Properties window

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Figure 2: Creating a new project

3. In the Device Properties window, you will be selecting your Target device, Simulator tool, Synthesis
tool and Hardware language in which you will be writing your design code. Figure 3 shows the
selections you need to make. NOTE: If you purchased the Nexys board with the -1200 option, you
should select the XC3S1200E device instead of the XC3S500E device. All other fields can stay the
same.

Figure 3: Target Device and Tool Selection

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4. Click Next three times and you will reach the Project Summary window. This window gives you an
overview of your project created so far. Click on Finish and your project is created as shown in Figure
4. Verify that the project name is counter.ise (shown as the last component in the title bar of the
application). You can also verify by going to the location where you created the project and double-
clicking on the folder named counter.

Figure 4: Successful creation of project

5. Now you will create a top level schematic for your design. In the Sources window, right click on
xc3s500e-4fg320 and select New Source. A New Source Wizard window appears as shown in
Figure 5. Select Schematic and enter counter under file name. Make sure the “Add to project”
checkbox is checked.

Figure 5: Creation of a schematic source file

6. Click Next two times followed by Finish to create the counter.sch file under the project folder.
Figure 6 shows the final layout of the project after the source file is created. If you don’t see the

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schematic, you may see a Design Summary. Click on the “counter.sch” tab at the bottom of the main
design window to see the schematic.

Figure 6: Project Navigator showing top-level schematic

7. The Sources window at the top-left should have the Symbols tab selected (there are 5 tabs at the
bottom of the window). From this tab, you can select schematic symbols to add to the schematic.
From the Categories listbox, select Counter. Then, from the Symbols listbox, select “cb2ce”. Move
your cursor to the main schematic window on the right and you will see a schematic symbol attached
to the cursor. Left-click to place the symbol on the schematic. Press ESCAPE to detach the symbol
from the cursor, and then press the F8 key several times to zoom in on the symbol you placed. The
result should be as shown in Figure 7.

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Figure 7: CB2CE symbol added to schematic

8. To enable the counter to count, we have to tie the CLR input low, since this is an active-high
asynchronous clear input. From the Categories listbox on the left, select General, and from the
Symbols listbox select ‘gnd’. Place a ground symbol on the schematic below the connection point of
the CLR pin (look forward to Figure 8 for reference).

9. The CE clock-enable pin is active-high. To allow the counter to count, we have to tie this pin high.
From the Categories listbox, select the <-All Symbols-> choice right at the top, and type ‘vcc’ in the
Symbol Name Filter textbox (a quicker way to add symbols when you already know the name). Click
on the ‘vcc’ symbol name in the Symbols listbox and use the cursor to place a VCC symbol above the
CE pin on the schematic.

10. Press Ctrl-W to start drawing wires, then click on the connection point of the CE pin (the small
square). Draw a wire ending at the connection point of the VCC symbol. Similarly, connect the CLR
pin and GND symbol together. The result should be as shown in Figure 8.

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Figure 8: VCC and GND symbols connected to the CB2CE symbol

11. Press Ctrl-G or click on the “Add I/O Marker” tool in the toolbar to start placing I/O markers (which
are connections to the outside world). Place an I/O marker directly over the connection point for the C
(clock) input. An I/O port symbol with an arbitrary name such as “XLXN_3” will appear. Press
ESCAPE and use the mouse to click and drag this I/O port symbol away from the symbol. A wire will
automatically be drawn to keep the I/O port and clock pin connected.

12. Right-click on the I/O port symbol, select Rename Port and type in the name CLK. The result should
be as shown in Figure 9.

Figure 9: CB2CE symbol connected to an I/O port

13. Finally, add two I/O ports for the Q0 and Q1 outputs and connect them. Name the I/O ports Q0 and
Q1. This is a good time to save your work (press Ctrl-S).

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14. The counter design must now be synthesized, i.e., converted to a representation that maps to actual
hardware resources on the Xilinx FPGA that you selected. To do so:

1. In the Sources window, click on the left-most Sources tab at the bottom.
2. Open the tree control beside the xc3s500e-4fg320 heading.
3. This will show the counter(counter.sch) item. Click on it.
4. Go to the Processes window below the Sources window and click on the Processes tab at the
bottom. Your screen should now appear as in Figure 10.
5. Double-click on the Synthesize-XST item. It’s OK if a yellow warning icon appears next to
this item once the process is complete.

Figure 10: Preparation for synthesizing the design

Part II – Constructing Waveform Simulations

1. In the Sources window at the top-left, click the Sources tab at the bottom of the window. Right-click
on the counter.sch filename and and select New Source. In the New Source Wizard dialog, select
Test Bench Waveform from the window on the left and enter countersim in the File name text box.
Make sure the “Add to project” checkbox is checked (see Figure 11). Click Next and make sure that

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counter is the top-level module name selected for this test bench waveform file. Click Next followed
by Finish.

Figure 11: A test bench waveform file is added to the project

2. The Initial Timing and Clock Wizard dialog opens, which allows you to create a clock stimulus for
the 2-bit counter design. Set the values in the dialog as shown in Figure 12 and then click Finish.

Figure 12: Clock stimulus settings for behavioral simulation

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3. You should see a timing diagram display that looks like a logic analyzer with the filename
countersim.tbw, as shown in Figure 13. Press Ctrl-S to save the file.

Figure 13: Test bench waveform for 2-bit counter

4. To run the simulation, go to the Sources window at the top-left, click on the Sources tab at the bottom,
and use the drop-down listbox to switch from Implementation to Behavioral Simulation. Click on
the countersim(countersim.tbw) module name. In the Processes window below it, click on the
Processes tab, then open the Xilinx ISE Simulator tree control. Finally, double-click on the Simulate
Behavioral Model item.

5. After a surprisingly long time for such a simple circuit, the simulation results should appear in a
Simulation window, as shown in Figure 14. Verify that your circuit functions as a 2-bit counter with
Q1 as the most significant bit.

Figure 14: Results of 2-bit counter simulation

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Part III – Circuit Design with VHDL

1. Close the 2-bit counter project by using the File->Close Project menu item. Now create a new project
by selecting File->New Project. In the New Project Wizard dialog, set the name for this project to
be counter_vhdl, and set the Top-Level Source Type to be HDL. The wizard should appear as in
Figure 15.

Figure 15:
Creating a new
project using
VHDL as the top-
level source

2. Click Next,
and verify
that the
Device Properties are the same as for the previous project (Spartan3E XC3S500E FG320-4 device
(or XC3S1200E device), VHDL as the preferred language, XST synthesis tool, ISE simulator).

3. Once again, right-click on the xc3s500e-4fg320 module name in the Sources window and select New
Source. The New Source Wizard dialog appears. Set the file name to be ‘counter_vhdl’ and select
the type of the module to be VHDL Module. Make sure the “Add to project” checkbox is checked.
Click Next.

4. The Define Module dialog box appears. In this dialog you will set the names of the input and output
“pins” of the circuit. Set the fields of this dialog to appear as in Figure 16 and click Next and then
Finish.

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Figure 16: Defining the inputs and outputs of a VHDL module

5. Back in the New Project Wizard dialog, click Next twice then Finish. After the process completes,
you should see the ‘counter_vhdl.vhd’ file, as shown in Figure 17.

Figure 17: A new project showing the VHDL top-level source

6. Some of the VHDL code has already been written for you. Finish implementing the circuit by
modifying the source code as shown in Figure 18. Press Ctrl-S to save your work.

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Figure 18: VHDL code implementation of an 8-bit counter

7. To verify that you typed in the code correctly, perform a syntax check by clicking on the
counter_vhdl module in the Sources window, opening the Synthesize-XST tree control in the
Processes window and double-clicking on the Check Syntax item. If your code is correct, a green
checkbox will eventually appear next to this item.

8. Once the code is correct, synthesize the design by double-clicking on the Synthesize-XST tree control
in the Processes window.

9. After synthesizing the design, let’s perform a behavioral simulation of the design. Right-click on
counter_vhdl in the Sources window and select New Source. In New Source Wizard, select Test
Bench Waveform and set the File name to be ‘countersim’. Click Next and then make sure
‘counter_vhdl’ is the top level module name with which you are associating this test bench file. Click
Next followed by Finish to open Initial Timing and Clock Wizard. Make changes as shown in
Figure 19 and then click Finish.

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Figure 19: Setting a clock stimulus for the counter_vhdl circuit.

10. Once you click on Finish, the Test bench waveform window opens as shown in Figure 20.

Figure 20: Test bench waveform stimulus for counter_vhdl circuit

11. To run the simulation, switch the Sources window drop-down listbox from Implementation to
Behavioral Simulation, then click on the countersim(countersim.tbw) module (you will have to
expand the xc3s500e-4fg320 module tree control). Under the Processes window, click on the
Processes tab and expand Xilinx ISE Simulator and double-click Simulate Behavioral Model.

12. The simulator runs and opens another window which has the results of the simulation. You may need
to zoom in on the simulation by clicking on icon on the toolbar at the top of the window. Figure
21 shows the simulation output.

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Figure 21: Results of behavioral simulation for the counter_vhdl design

13. Scroll horizontally through the simulation results to verify that the circuit functions as an 8-bit
counter.

Part IV – VHDL Test Benches

Although we can construct waveform stimulus for our designs using the graphical editor, doing so is
cumbersome, time consuming, and error-prone. Furthermore, the graphical simulation results must be
verified “by eye”, which is also cumbersome, time-consuming, and error-prone. We can instead use
VHDL to both specify the input stimulus (just a clock so far) and check the output results.

1. In the Sources window, make sure the drop-down box setting is still Behavioral Simulation. In the
Processes window, select the Processes tab and expand the Xilinx ISE Simulator tree control.
Expand the Simulate Behavioral Model tree control and double-click on the Generate Self-
Checking Test Bench item, as shown in Figure 22.

Figure 22: Generating a self-checking test bench

2. Note that a new entry has been added to the ‘xc3s500e-4fg320’ module in the Sources window.
Right-click on the new ‘countersim_selfcheck_beh’ item in the Sources window and select Open.
The ‘countersim_selfcheck_beh.vhd’ file is a VHDL test bench that both provides clock stimulus to
your counter and also checks the outputs. Scroll through this file for a big-picture view of what it is
doing.

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3. To simulate this test bench, make sure the countersim_selfcheck_beh.vhd module is highlighted in
the Sources window. Open the Xilinx ISE Simulator tree control in the Processes window and
double-click the Simulate Behavioral Model item.

4. To verify that this test bench is capable of detecting errors, let’s change an expected result. In the
‘countersim_selfcheck_beh.vhd’ file at about line 103 (simulation time of 75ns), change the line that
reads “CHECK_ledout(“00000100”, 75)” to “CHECK_ledout(“10000100”, 75)”. Double-click on
Simulate Behavioral Model again and verify that the Transcript window at the bottom of the screen
indicates an error at 75ns.

Part V – Downloading to the Hardware

1. After successfully verifying the behavior of the design, now we need to download the design onto the
actual hardware. But before that we need to slow down the clock, so that each count is visible to the
user through LED’s on the board. Close the simulation window and the
‘countersim_selfcheck_beh.vhd’ window. Go back to edit the original ‘counter_vhdl.vhd’ source
file. Figure 23 below shows the changes you need to make to your code to include a clock divider
process. You will need to:
a. Add a clk_div signal at line 37
b. Add a ClockDivider process at line 40-45
c. Modify the Counter process at line 47 from (clk) to (clk_div)
d. Modify the rising_edge statement at line 49 from rising_edge(clk) to
rising_edge(clk_div(25)).

Figure 23: Modification to counter_vhdl design to implement a clock divider

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2. Synthesize your design again by double-clicking on the Synthesize-XST item in the Processes
window (switch the drop-down list back to Implementation). On successful synthesis, you should see
a green check next to Synthesize-XST, although a yellow “caution” symbol might also appear.

3. After converting your design into a hardware representation, the next step is to assign actual device
pins to your design input/output ports through a constraint file. Select the counter_vhdl module in the
Sources window, then open up the User Constraints tree control in the Processes window.

4. Double-click on Floorplan Area / IO / Logic. Click on Yes for the dialog box that asks whether you
want to have a UCF file automatically added to your project. This process starts a separate program,
Xilinx PACE. This program allows you to assign pins to your ports.

5. In the Design Object List – I/O Pins window at the bottom-left of PACE (see Figure 24), click on
the I/O Name column to sort the pin names alphabetically. Enter the pin numbers in the LOC column
as shown in the figure.

How do you know which pins go where? Download the Nexys reference manual from Digilent.

Figure 24: Assigning I/O pins

6. Select File->Save to save the counter_vhdl.ucf file and close the Xilinx PACE application window.
After assigning the pins, you now need to convert and map your design to the logic blocks inside the
FPGA. In the Sources window, select the ‘counter_vhdl.vhd’ file and under the Processes window,
double-click on Implement Design as shown in Figure 25. On successful implementation, you should
see a yellow exclamation mark next to Implement Design.

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Figure 25: Implementing the design

7. Now under the Processes window, double-click on Generate Programming File to create a bit file
(the file that will be downloaded onto your hardware). You should see a green check beside it when
the process completes.

8. Now you need to open a downloading tool that will download your design onto the FPGA. Go to
Start -> Programs -> Digilent -> Adept -> ExPort to open the tool as shown in Figure 26.

Figure 26: The Digilent ExPort downloading tool

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9. Connect your Nexys board to the computer using the USB cable provided with the board. Make sure
that the Power Select jumper JP7 (near the top-left of the board) is configured for USB (this is the
factory-default position). Also, the Nexys board as-shipped has jumper JP9 (near the top-right of the
board) installed in the ROM position. This will cause the FPGA to execute a “program” stored in a
factory-programmed ROM. It is a good idea to run this program to make sure your board is functional.
Leave JP9 in the ROM position and turn on power to the board by sliding the main power switch
(top-left of the board) upwards. The LED display should eventually show PASS to indicate your
board is functional. Press the buttons and play with the slide switches to see what happens.

10. Slide the main power switch back down to turn off power to the board. Then, move the JP9 jumper
from the ROM to the JTAG position. Turn the power switch on again.

11. Now click on the Initialize Chain button in the Digilent ExPort window. Two devices are detected,
FPGA and ROM as shown in Figure 27.

Figure 27: Detecting the devices on the Basys board

12. Click on the FPGA graphic (not the checkbox next to it). It should turn green indicating it’s selected.
Then click on Browse and go to your design folder and select the ‘counter_vhdl.bit’ file and click
Open. A warning window appears. Click Yes and you will see the ‘counter_vhdl.bit’ file associated
with the FPGA as ahown in Figure 28.

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Figure 28: Associating a .BIT file with the FPGA

13. Click on Program Chain and your program is downloaded to the FPGA. You should see the 8 LED’s
counting in binary at a rate of 1 Hz.

14. Once you verify that the program works, try modifying the ‘counter_vhdl.vhd’ file to achieve a faster
count rate. You may have to think and experiment a bit!

15. Once you are done, slide the power switch down to turn off the board power then disconnect the USB
cable from the computer. Close the Digilent ExPort and Xilinx ISE applications.

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