PC Architecture

W.J. BUCHANAN, Napier University, Edinburgh, UK.

 IDE bus South bridge North bridge

Video
DRAM
adaptor

Video
memory
PCI bus
Socket-7
for processor
ISA bus

Level-2 cache
 Aims

• To outline the basic architecture of the IBM PC.

• To show the evolution of the architecture, and the
enhancements that have improved the performance of
the modern PC.
• To show how bridges have enhanced the performance of
the PC.
• To illustrate the usage of modern chipsets.
• To outline hub-based systems.
• To present a future legacy-free system.
 MN/-MX
CLK GND
8284 READY CLK
-S0 -S0 -MEMR
Clock RESET
Generator -S1 -S1 -MEMW
-S2 -S2 -IOR
-IOW
DEN
-INTA
DT/-R
ALE
8088 8288 Bus
8088
Processor Controller
Processor

GND 1 40 VCC
STB
A14 2 39 A15
Address
A13 3 38 A16/S3 AD0-AD19
bus
A12 4 37 A17/S4
A16-A19
A11 5 36 A18/S5 Latch
A10 6 35 A19/S6
A9 7 34 SSO
DIR
A8 8 33 MN/-MX
AD7 9 32 -RD -G Data
AD6 10 31 -RQ/-GT0 bus
INTR
AD5 11 30 -RQ/-GT1 Buffer
AD4 12 29 -LOCK
AD3 13 28 -S2
AD2 14 27 -S1
AD1 15 26 -S0 IRQ0
AD0 16 25 QS0 IRQ1
8259
NMI 17 24 QS1 IRQ2
Interrupt Interrupt
INTR 18 23 -TEST controller requests
CLK 19 22 READY
GND 20 21 RESET
IRQ7

Roots?
Roots?
 8250
8250
UART
UART COM1:
Serial
Serial
I/O
I/O COM2:
8255
8255
Digital
DigitalI/O
I/O
PC
PC
Processor
Processor

8237 DMA0-DMA3
8237
DMA
DMA
Controller DMA4-DMA7
Controller

1.2MHz System
82C59 Timer (IRQ0). 18.3Hz
82C59(PIC)
(PIC) 82C54
82C54
Programmable IRQ0-IRQ7 PTC Memory refresh
Programmable PTC
Interrupt timer. One clock
Interrupt Timer
Timer
Controller Pulse every 15 µs.
Controller IRQ8-IRQ15
Speaker tone

Roots?
Roots?
 8250
8250
UART
UART
Serial
Serial
I/O
I/O
8255
8255
Digital
DigitalI/O
I/O
PC
PC
Processor
Processor
Integration
8237
8237 of external
DMA
DMA
Controller
devices (such
Controller
as Chips & Tech.)

82C59
82C59(PIC)
(PIC) 82C54
82C54
Programmable
Programmable PTC
PTC
Interrupt
Interrupt Timer
Timer
Controller
Controller

Roots?
Roots?
 A[31:2]
D[31:0]
BE0#
BE1# 32-bit address bus
BE2# and byte enables
ADS#
Burst BE3#
control RDY#
M/IO#
INTR
D/C#
Interrupt RESET W/R# Bus cycle
signals NMI LOCK# definition
PLOCK#
Cache EADS#
invalidation M/IO# D/C# W/R# Bus cycle type
HOLD
KEN
0 0 0 Interrupt acknowle
80486
HLDA 0 0 1 Special (see next)
Cache
control FLUSH BOFF# Bus 0 1 0 I/O read
AHOLD arbitration 0 1 1 I/O write
PWT 1 0 0 Instruction fetch
Page caching BREQ
control PCD 1 1 0 Memory data read
BRDY# 1 1 1 Memory write
Burst
FERR# BLAST#
Numeric control
errors IGNNE# BS8#
B16# Bus size
Address control
A20/M# DP0
bit 20 mask
DP1
CLK DP2
Parity
DP3
PCHK#
 Memory
Memory
Multiplied clock

High transfer
PC
PC rates (local
Video
Video
Processor
Processor bus). 32/64-bit
at 66 MHz.

Bridge
Bridge

Medium transfer
Network
Network Hard
Harddisk
disk rates (local
adaptor
adaptor bus). 16/32-bit
at 33 MHz.

Bridge
Bridge
Low transfer
rates (local
Floppy
Floppy Serial
Serial bus). 8/16-bit
disk
disk comms
comms at 8 MHz.

Local
Local
bus
bus
 Level-2
Level-2
cache
cache

Cache bus

System
System DRAM
DRAM
Controller
Controller
Processor System DRAM
Processor bus bus

Level-1 AGP
cache bus
PCI bus
Keyboard
Interrupt
Serial ports
ISA bus Ultra
PCI
PCIbridge
bridge Ultra Parallel ports
I/O
I/O
Floppy disk
Power
management Infrared port
Flash
Flash
DMA IDE USB BIOS PS/2 mouse
X-bus BIOS
signals bus bus
 Level-2
Level-2
cache
cache

Cache bus

System
System
Controller
Controller DRAM
DRAM
System 82438
82438(TXC)
(TXC) DRAM
Processor
Processor bus bus

Level-1 AGP
cache bus
PCI bus
Keyboard
Interrupt
Serial ports
PCI
PCIbridge
bridge ISA bus Ultra
Ultra Parallel ports
82371SB
82371SB(PIIX3)
(PIIX3) I/O
I/O
Floppy disk
Power
management Infrared port
Flash
Flash
DMA IDE USB BIOS PS/2 mouse
X-bus BIOS
signals bus bus
HX
HX
chipset
chipset
 Level-2
cache

PCI Bridge:
Cache bus PCI Bridge:
DMA.
DMA.Enhanced
Enhancedseven-channel
seven-channel
DMA
DMAwith withtwo
two82378237controllers.
controllers.
System This
This is supported withthe
is supported with the
Controller handshaking
handshaking lines
DRAM DRQ0–DRQ7
lines DRQ0–DRQ7
System 82438 (TXC) DRAM and DRQ0#–DRQ7#.
and DRQ0#–DRQ7#.
Processor bus Fast
bus FastIDE.
IDE.Fast
FastIDEIDEsupport
supportforfor
up
upto
tofour
fourdisk
diskdrives
drives(two(two
Level-1 AGP masters
masters and two slaves).ItIt
and two slaves).
cache bus supports
PCI bus supportsmode modefourfourtimings,
timings,
which
which gives transfer ratesofofup
gives transfer rates up
to
to22MB/s.
22MB/s. Keyboard
Interrupt Timer.
Timer.Incorporates
Incorporates82C54 82C54
Serial ports
timer for system timer,
timer for system timer, refreshrefresh
PCI
PCIbridge
bridge ISA request
bus and speaker output tone.
request andUltra
speaker Parallel
output ports
tone.
82371SB (PIIX3)
82371SB (PIIX3) I/O
Floppy disk
Power
management Infrared port
Flash
DMA IDE USB PS/2 mouse
X-bus BIOS
signals bus bus
HX
HX
chipset
chipset
 Level-2
cache

PCI Bridge:
Cache bus PCI Bridge:
PCI.
PCI.Steerable
SteerablePCI PCIinterrupts
interruptsfor for
PCI
PCIdevice
deviceplug-and-play.
plug-and-play.The The
System PCI interrupt lines (PIRQA–
PCI interrupt lines (PIRQA–
Controller PIRQD)
PIRQD)can be
DRAM
can besteered
steeredto toone
oneofof
System 82438 (TXC) DRAM 1111interrupt
interrupt(IRQ3–IRQ7,
(IRQ3–IRQ7,IRQ9– IRQ9–
Processor bus IRQ12,
bus IRQ12,IRQ14
IRQ14and andIRQ15).
IRQ15).
Mouse.
Mouse.Support
Supportfor forPS/2-type
PS/2-type
Level-1 AGP mouse
mouse and serial portmouse.
and serial port mouse.
cache bus IRQ12/M
PCI bus IRQ12/M can be enabledfor
can be enabled forthe
the
PS/2-type
PS/2-type mouse or disable foraa
mouse or disable for
serial
serialport
portmouse.
mouse. Keyboard
Interrupt IRQs.
IRQs.Two Two82C59
82C59controllers
controllers
Serial ports
with 14 interrupts.
with 14 interrupts. The The
ISA interrupts
bus
PCI
PCIbridge
bridge interruptslinesUltra
lines IRQ1,
IRQ1,IRQ3– Parallel ports
IRQ3–
IRQ15
IRQ15are areavailable
I/O (IRQ0
available (IRQ0isis
used Floppy disk
Power usedby bythe
thesystem
systemtime timeandand
management IRQ2
IRQ2by bythe
thecascaded
cascadedinterrupt
interrupt
Infrared port
line).
line).
Flash
DMA IDE USB PS/2 mouse
X-bus BIOS
signals bus bus
HX
HX
chipset
chipset
 Level-2
cache

System controller:
Cache bus System controller:
Clocks.
Clocks.Supports
Supports50MHz,
50MHz,
60MHz
60MHzandand66MHz
66MHzhost hostbuses.
buses.
System
System Memory controller. Integrated
Memory controller. Integrated
Controller DRAM
Controller DRAMcontroller.
DRAMSupports
controller. Supportsfourfour
System 82438 (TXC)
82438 (TXC) DRAM CAS lines and eight RAS lines.
CAS lines and eight RAS lines.
Processor bus The
Bus Thememory
memorysupports
supports
HD[63:0] symmetrical
symmetricalandandasymmetrical
asymmetrical
Level-1 HA[31:0] addressing
addressing for 1MB,2MB
for 1MB, 2MBand and
cache 4MB-deep SIMMs
4MB-deep SIMMs and and
PCI bus
AGP bus symmetrical
symmetricaladdressing
addressingforfor
16MB-deep
16MB-deepSIMMs.
SIMMs. Keyboard
Interrupt L-2
L-2controller.
controller.Supports
Supports up
upto
Serial to
ports
512MB of second-level cache
512MB of second-level cache
PCI bridge ISA with
bus
withsynchronous
Ultra pipelined
synchronous pipelined burst
Parallel
burstports
82371SB (PIIX3) SRAM.
SRAM. I/O
Floppy disk
Power
management Infrared port
Flash
DMA IDE USB PS/2 mouse
X-bus BIOS
signals bus bus
HX
HX
chipset
chipset
 Cache
(SRAM)

Control: HCACHE#, Control: CCS#, CTAG

HKEN#, HSMIACT#, COE#, CADS#, [10:0]
HADS#, HBRDY, CBWE#,CGWE#
HNA#, HAHOLD, CTWE#
HEADS#, HBOFF# ,
HCLKTXC, HLOCK#, Parity: MP[7:0]
HW/R#, HD/C#,
HM/IO#, HHITM#
Data: MD[63:0]
Data: HD[63:0] 82439HX
Address: MA[11:2], Main
System
Pentium MMAA[1:0], MMAB[1:0, memory
Controller
processor Address: HA[31:3] (TXC) MRAS#[3:0], MCAS#[7:0] (DRAM)

Address: HBE#[7:0] Control: MWE#

Interrupt: HINT
AD[31:0]
Fast IDE
USB C/BE#[3:0]
DMA PCI bus
Speaker 82371SB
Reset PIRQA, PIRQB, PIRQC, PIRQD
PCI I/O IDE
Xcelerator PCICLK, FRAME#, TRDY#, IRDY#,
82091AA STOP#, DEVSEL#, SERR#, PAR, IDSEL,
AIP ISA (PIIX3)
PHOLD#, PHOLDA#, LOCK#, PREQ#[3:0],
bus
PGNT#[3:0], PHLD#
2 serial ports, 1 parallel port
Floppy disk controller
HX
HX
chipset
chipset
 Level-2
Level-2
cache
cache

Cache bus

System
System
Processor
Processor Controller
Controller DRAM
DRAM
System (PAC/MTXC)
(PAC/MTXC) DRAM
bus bus

PCI bus

DMA ISA bus

PCI
PCIIDE/ISA
IDE/ISAAccelerator
Accelerator
Interrupts USB bus
(PIIX4)
(PIIX4)
Reset
Primary IDE Secondary IDE X-Bus
Power
management
PDIORDY#

SDIORDY#
PDDACK#

SDDACK#
PDD[15:0]

SDD[15:0]
PDIOW#
PDDREQ

SDIOW#
SDDREQ
PDIOR#
PDCS1#

PDA[2:0

SDIOR#
SDCS1#
SDCS3#
SDA[2:0
PDS3#
 Level-2
Level-2
cache
cache
Host control bus
(BE[7:0], ADS#, D/C#, M/IO#, Cache tag
W/R#, BRDY#, EADS#, HITM#, Cache control bus (CCS#, TWE#, COE#,
control GWE#, CADS#, CADV#, BWE#)
BOFF#, AHOLD, NA#, KEN#,
(TIO[7:0])
CACHE#, HLOCK#, SMIACT#,
HCLK, PCLK) DRAM Control bus (RAS[5:0,
CAS[7:0], MWE#, MWEB#,
SRAS[A:B]#, SCAS[A:B], CKE)
Pentium
Pentium Host data bus (HD[63:0]) 82439TX
82439TX
processor
processor (MTXC)
(MTXC) DRAM data bus (MD[63:0]) DRAM
DRAM
Host address bus (HA[31:0])
DRAM address bus (MA[11:0])

PCI control bus (REQ[3:0]#, GNT[3:0]#, PCI address/data bus

FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#,
(AD[31:0])
SERR#, PAR, IDSEL, PHOLD#, PHLKA#,
CLKRUN#, PCICLK#, PIRQ[D:A]) X-data control (PCS[1:0]#,
XDIR#, XOE#, RTCALE,
Fast IDE (Primary IDE:
FERR, IGNNE#, BIOSCS#,
PDCS1#, PDCS3#,
USB 82371AB
82371AB RTCCS#, KBCCS#, A20M#,
PDA[2:0], PDD[15:0],
(CLK48, USBP0+, USBP0–, (PIIX4)
(PIIX4) A20GATE, MCCS#)
PDDACK#, PDDREQ#,
PDIOIR#, PDIOIW#, PDIORDY) USBP1+, USBP1–, OC0, OC1) 74F245
74F245
DMA
(REFRESH#, TC, DREQ[7:0],
DACK[7:0], REQ[A:C], SD[7:0] X-data bus
GNT[A:C]) ISA bus (SD[15:0], SA[23:0],
IOCS16#, LA[23:17], SBHE#,
MEMCS#, MEMR#, MEMW#,
AEN, IOCHRDY, IOCHK#, Peripheral
Peripheralcomponents,
components,
SYSCLK, BALE, IOR#, IOW#, XD[7:0], CMOS,
CMOS,Keyboard
Keyboardcontroller
controller
SMEMR#, SMEMW#, ZEROWS#, XOE#, and
andFlash
FlashBIOS
BIOS
IRQ1, IRQ[12:3], IRQ14, IRQ15) XDIR#
IR port
(IRRX, IRTX,
MEDID1)
Ultra
UltraI/O
I/O Keyboard/mouse
(KBCLK#, KBDAT#,
MSCLK#, MSDAT#)
Floppy bus (INDEX#, DIR#, Parallel bus (PD[7:0, SLIN#, RS-232 bus (RX, TX, RTS#,
STEP#, WDATA#, WGATE#, INIT#, AFD#, STB#, BUSY, CTS#, DTR#, DSR#, DCD#,
TRK0#, WPT#, RDATA#, ACK#, PE, SLCT, ERR#) RI#) 430
430TX
TX
SLIDE1#, DSKCHG#, MTR0#,
MTR1#, DRVSEL0#, DRVSEL1#, chipset
chipset
DRVDEN0# DRVDEN1#)
 AGP
AGP
Graphics
Graphics
Controller
Controller

AGP 2.0

HA[31:0]

HD[63:0] MD[63:0] MD[63:0]

MAA[10:0] MAA[10:0]
ADS#
BNR# DQMB[7:0] CAS[7:0]#
BPRI# S[3:0]# RAS[3:0]#
DBSY# Host/PCI
Host/PCI
bridge CLK[3:0]
DEFER# bridge
SC242
SC242processor (North DRAM
processor DRDY# (North CAS# DRAM11
bridge)
bridge) (SDRAM/EDO)
HIT# RAS# (SDRAM/EDO)
HITM#
CB[7:0] CB[7:0]
HLOCK#
HREQ[4:0] WE[2:0]# WE[2:0]#
HTRDY# OE[2:0]# OE[2:0]#
RS[2:0]#
SA[2:0] SA[2:0]
CPURST#

PCI PCI SDRAM EDO

devices bus signals signals
AGPset
AGPset(LX/
(LX/
SLP#
FERR#
BX/GX/etc)
BX/GX/etc)
IGNNE# USB bus
INT
INITR IDE bus
A20GATE PCI
PCIbridge
bridge
(South Floppy disk
NMI (Southbridge)
bridge)
SMI# Serial port
STPCLK#
RCIN# Parallel port
ISA bus Super
SuperI/O
I/O Mouse port
K/B port
I/R port
 PC Evolution

ISA architecture.
Addition of the PCI bus, for improved automated configuration.
Addition of an on-chip level-1 cache.
Addition of a level-2 cache onto the motherboards.
Usage of the North/South bridge approach, for faster interfaces to
memory.
Enhancements of DRAM from EDO to SDRAM.
Addition of the AGP interface, for faster interfaces to graphics.
Movement of level-2 cache from motherboard to an on-package
memory.
Faster DRAM memory transfers with 100MHz and 133MHz SDRAM.
Hub-based architecture, for faster transfers between the
processor, graphics and memory.
Fast RDRAM, for ultra-high data transfers between the processor
and memory, and the AGP interface and memory.
 Hub-based architecture

810 series: 82801 I/O controller hub (ICH), 82802 firmware hub
(FWH) and 82810 graphics memory controller hub (GMCH). This
GMCH has an integrated graphics controller that uses direct AGP
(integrated AGP) for ultrafast 2D and 3D effects and images. The
82810 also has an integrated hardware motion compensation to
improve soft DVD video quality and a digital TV out port.
820 series: 82820 memory controller hub (MCH), 82801 ICH,
82802 FWH.
840 series: 82840 MCH 82801 I/O ICH 82802 FWH 82806 64-bit
PCI controller hub and 82803 RDRAM-based memory repeater hub
(MRH-R) or 82804 SDRAM-based memory repeater hub.
 Servers/workstation Performance desktop

450NX 840 440GX 820 810E 440BX 440ZX

AGP AGP

Processors Pentium Pentium Pentium Pentium Pentium Pentium Pentium

II/III Xe on II/III Xe on II/III Xeon II/III II/III II/III II/III

Bus signals AGTL+ AGTL+ GTL+ AGTL+ AGTL+ GTL+ GTL+

Maximum 4 2 2 2 1 2 2
number of
processors

DRAM refresh CAS- RDRAM CAS- N/A CAS- CAS- CAS-

before- Active before- before- before- before-
RAS Refresh RAS RAS RAS RAS

Memory 8 rows 32 8 rows 32 4 rows 8 rows 4 rows

support RDRAM RDRAM
devices
per
channel

DRAM chips Yes 64/128/ 64/128 64/128/ Yes Yes Yes

supported 256 Mbit Mbit 256 Mbit

Maximum 8 GB 8 GB 2 GB 1 GB 512 MB 1 GB 256 MB

memory

Memory types SDRAM / PC800/ SDRAM RDRAM PC100 SDRAM SDRAM

PC600 SDRAM
EDO RDRAM
PC100
SDRAM

PCI type PCI 2.1 PCI 2.2 PCI 2.1 PCI 2.2 PCI 2.2 PCI 2.1 PCI 2.1

Integrated No No No No Yes No No
graphics

AGP type No AGP 1×/ AGP 1×/ AGP AGP AGP AGP
2×/4× 2×

AGP pipe No PIPE PIPE PIPE Integrated PIPE PIPE

AGP SBA No SBA SBA SBA Integrated SBA SBA

South bridge PIIX4E ICH PIIX4E ICH ICH PIIX4E PIIX4E

IDE type ATA/33 ATA/66 ATA/33 ATA/66 ATA/66 ATA/33 ATA/33

 810 440LX 440EX AGP 440ZX AGP

Processors Pentium II/III Pentium Celeron Pentium Celeron Pentium Celeron

Bus signals AGTL+ GTL+ GTL+ AGTL+

Maximum number 1 2 1 1
of processors

DRAM refresh CAS-before-RAS CAS-before-RAS CAS-before-RAS CAS-before-RAS

Memory support 4 rows 8 rows 4 rows 4 rows

DRAM chips 16/ 64/128 Mbit Yes Yes Yes

supported

Maximum 512MB 1 GB 256 MB 256 MB

memory

Memory types PC100 SDRAM EDO SDRAM SDRAM EDO SDRAM

PCI type PCI 2.2 PCI 2.1 PCI 2.1 PCI 2.1

Integrated graphics Yes No No No

AGP type Integrated AGP 1×/ 2× AGP 1×/ 2× AGP 1×/ 2×

AGP pipe Integrated PIPE PIPE PIPE

AGP SBA Integrated SBA SBA SBA

South bridge ICH PIIX4E PIIX4E PIIX4E

IDE type ATA/66 ATA/33 ATA/33 ATA/33

AC’97:
AC’97:Digital
Digital
link x4
x4AGP
link foraudio
for audio AGP
Graphics
Graphics
and
andmodem
modem controller
controller
codec
codec. .
RDRAM
AGP 2.0

GC/BE[3:0]#
interface

GAD[31:0]
interface

Control
LDQA[8:0]

HAD[31:0]# LDQB[8:0]

HD[63:0]# MCH LCOL[4:0] DRAM

Processor
Processor MCH(Memory
(Memory DRAM
controller (RDRAM)
Control
controllerhub)
hub) (RDRAM)
LROW[2:0]

Control

HL_STB#
Hub

HL[10:0]
HL_STB
interface

AC’97
AC’97
Codec ICH
Codec AC’97 2.1 ICH(I/O
(I/O PCI bus
Keyboard controller
controller PCI-ISA
PCI-ISA
Mouse hub)
hub) USB bus bridge
bridge
Serial Port Super
SuperI/O
I/O (opt.)
(opt.)
LPC (Low-pin IDE bus
count) interface
ISA bus

Firmware
Firmware Hub-based
Hub-based
hub
hub architecture
architecture
 AGP
AGP
graphics
graphics
controller
controller The
Thefuture?
future?
>8Gbps

AGP 2.0

Memory
Memory
controller
controller RDRAM
RDRAM
Processor
Processor Host hub DRAM
bus hub(MCH)
(MCH)
bus

Hub
interface
Floppy disk
USB
USB2.0
2.0
hub
hub Hard disk
USB Port 1
USB Audio device/
Video USB2.0
2.0
Video controller modem
device controllerhub
hub
device Firewire
Scanner
USB
USB2.0
2.0
USB Port 2 hub
hub Storage

Network
1.5Mbps
adaptor
12Mbps
>500Mbps 480Mbps
 AGP
AGP
graphics
graphics
controller
controller Transfer rates
>8Gbps
Clock Clocking Data Rate Transfer
Speed (million rate
(MHz) samples/s) (MB/s)
AGP 2.0
AGP 2.0 66 Quad 266 1066
(32 bits) (4 samples/
clock)

CPU bus 133 Single 133 1066

Memory
Memory (64 bits)
controller
controller Hub RDRAM
RDRAM
Processor
Processor Host hub DRAM66 Quad 266 266
bus hub(MCH)
(MCH) interface
bus
(8 bits)

PCI 2.2 33 Single 33 133

Hub (32 bits)
interface
RDRAM 266/300/ Double 533/600/ 1066/1200
(16 bits) 356/400 711/800 /1422/1600
Floppy disk
USB
USB2.0
2.0
hub
hub Hard disk
USB Port 1
USB Audio device/
Video USB2.0
2.0
Video controller modem
device controllerhub
hub
device Firewire
Scanner
USB
USB2.0
2.0
USB Port 2 hub
hub Storage

Network
1.5Mbps
adaptor
12Mbps
>500Mbps 480Mbps
 SBA[7::0]

GAD[31:0]#

GC/BE[3:0]#

CPUST#

MCH
GFRAME#
GDEVSEL#
MCH
GIRDY#
GTDRY# connections
connections
GSTOP#
GPAR
HA[31:0]# GREQ#

AGP
GGNT#
HD[64:0]# PIPE#
PIPE#
CPUST# MCH_CK66
HADS# RBF#
WBF#
BNR#
ST[2:0]
BRPI#
ADSTB[0]
DBSY#
Processor
Processor MCH
MCH ADSTB[0]#
DEFER#
ADSTB[1]
(SCS242)
(SCS242) DRDY#
ADSTB[1]#
HIT#
SBSTB
HITM# SBSTB#
HCLOCK#
Fast memory
HTDRY# to graphics
control/ LDQA[8:0]
RS[2:0]# processor
transfers LDQB[8:0]
HREQ[4:0]#
LCOL[4:0]

LROW[2:0]

RDRAM
LCLKTM
LCLKTM#
LCLKFM
Hub

LCLKFM#
RCLKOUT
HCLKOUT
HL_STB#
HL[10:0]

HL_STB
 CFM
CFM--Clock
Clock
from Master
from Master

LDQA[8:0] RDQA[8:0] TERMDQA[8:0]

LDQB[8:0] RDQB[8:0] TERMDQB[8:0]

LROW[2:0] RROW[2:0] TERMROW[2:0]

LCOL[4:0] RCOL[4:0] TERMCOL[4:0]

Terminator
MCH RIMM
RIMM00 RIMM
RIMM11
MCH LCFM RCFM RCFM
LCFM# RCFM# RCFM#
LCTM RCTM
LCTM# RCTM#

LCMD RCMD TERMCMD

LSCK RSCK TERMSCK
LSIO RSIO
 CC BB AA
CTM CTM CTM
TCLK TCLK CLK
DD Clock
CLK generator
CTM CTM CTM
Controller RDRAM RDRAM
Vterm
CFM CFM
RCLK RCLK

CFM CFM
EE
EE

CFM–RCLK (used for Controller to RDRAM)

CTM– RCLK (used for RDRAM to controller)

CTM/CTM# signals Terminator

CFM/CFM#/RSL/
Controller CMOS signals
RIMM 0 RIMM 1
 Processor

MCH

I/O
I/O
Controller
Controller

HL[10:0]

HL_STB#
HL_STB
Hub

CLK14
CLK48
CLK66
Hub
AD[31:0]
A20M#
C/BE[3:0]#
SLP#
Hub DEVSEL#
FERR# FRAME#
IDNNE# IRDY#
HINT# TRDY#
STOP#
LINT0#
Processor PAR
LINT1# PCIRST#
SMI# PLOCK#
STPCLK# PCI SERR#
PERR#
KBRST#
PCI_PME#
A20GATE REQ[A}#
GNT[A]#
PDD[15:0]
PCI_CLK
SDD[15:0] I/O controller PIRQ[D:A]#
IRQ14 hub (ICH)
PREQ[4:0]#
IRQ15#
PGNT[4:0]#
PDA[2:0]#
SDA[2:0]# USB1+
PDCS[1,3]# USB1-
IDE
SDCS[1,3]# USB0+
PDREQ# USB USB0-
SDREQ# OC1#
OC0#
PDDACK#
SDDACK# AC_RST#
AC_SYNC
etc
AC_BIT_CLK
Serial ports
AC_SDOUT
Parallel port LAD[3:0] AC97 ACSDIN0
Floppy disk Super
LDRQ[0]# ACSDIN1#
I/O LPC
LFRAME#]
SPEAKER
KBRST#
KBDAT
LAD[3:0]
KBCLK
Mouse/
MDAT keyboard LFRAME#
MCLK
ICH
LDRQ0#

RXD1
Super I/O PCIRST#
TXD1
DRVDEN1
DSR1#
DRVDEN0
RTS1#
Serial MITR#
CTS1#
port 1 DS0#
DTR1#
DIR#
RI1#
STEP#
DCD1
WDATA#
Floppy WGATE#
RXD2 disk HDSEL#
TXD2
INDEX#
DSR2#
TRK0#
RTS2#
CTS2# Serial WRTPRT# Super
SuperI/O
I/O
DTR2# port 2 RDATA# device
device
RI2# DSKCNG#
DCD2
IRRX#
Infrared IRTX#
PD[7:0]
INIT#
SLCTIN# J1BUTTON1
SLCT# J1BUTTON2
PE Parallel Joypad JOY1X
BUSY port 2 (1)
JOY1Y
ACK#
ERROR# KEYLOCK#
ALF#
14.1MHz
STROBE#
 LINE_OUT_R
LINE_OUT_L

LINE_IN_R
LINE_IN_L
MIC_IN
AC_SDATOUT
ICH
ICH
CD_R Audio
Audio
AC_SDATIN
CD_L AC_SYNC
Codec
Codec
CD_REF AC_BITCLK

MONO_PHONE1
MONO_OUT

AC’97 SPEAKER
Audio
Audiocodec
codec
connections
connections
 (x4
AGP
AGP
Graphics

(x4AGP)
Graphics
Controller
AGP)
Controller

GFRAME#
GPAR
GSTOP#
GSERR#
SBA[7:0]
ST[2:0]
STB, STB#

GIRDY#
GDEVSEL#
GGNT#
RBF#
WBF#
PIPE#
STB[1:0]#
STB[1:0]

GAD[31:0]
GC_BE#[3:0]
GTDRY#
GREQ#
HA[35:3]

HD[63:0]

ADS#
BNR#
BPRI#
DQA[8:0]
DBSY#
DEFER# DQB[8:0]

DRDY# RQ[7:5]/ROW[2:0]
HIT#
RQ[4:0]/COL[2:0]
HITM#
HLOCK#
DRAM

hub

HREQ[4:0] CTM, CTM#

hub
control
Memory
DRAM11

(82840)
control
Memory

(82840)

HTRDY#
(SDRAM/EDO)

CFM, CFM#

SC242
(SDRAM/EDO)

SC242
RS[2:0]#
CMD
CPURST#
SCK
AP[1:0]#
SIO
BERR#
BREQ0#
DEP[7:0]#
IERR#
RP# 300MHz or 400MHz
RSP#
BSTRB[1:0]
AZCOMP
ASTRB

HLB[19:0]
HLA[11:0]

BZCOMP
BSTRB[1:0]#
ASTRB

A20M#
FERR#
64/32-bit PCI bus (66MHz)
IGNNE# IDE bus
INIT 64/32-bit PCI bus (66MHz)
(82801AA
(82801AB
I/O

INITR PCI bus (33MHz) Either two 66MHz

PCI

A20GATE
or

PCI slots, or four

hub

or
hub

NMI AC’97 bus 64/32-bit PCI bus(33MHz)

PCI64H

33MHz PCI slots

64H

I/Ocontrol
(82806AA)

control
(82806AA)

SMI#
(82801AB––ATA/33

64/32-bit PCI bus(33MHz)

(82801AA–– ATA/66

PCI bus (33MHz)

STPCLK#
ATA/33IDE)

ATA/66IDE)
IDE)

IDE)

RCIN# 2xUSB bus

LPC

Serial port

Parallel port
Super

Joystick
Firmware
(82802)

SuperI/O
(82802)

I/O
Firmwarehub

Keyboard
hub

Mouse
 Video
Videodisplay
display Digital
DigitalTV
TVout
out

LVDATA[11:0]
TV output

CLKOUT[1:0]
Encoder

TVHSYNC
Encoder

DDCSDA
DDCSCL

TVSYNC
TVCLKIN
HSYNC
GREEN

BLANK#
VSYNC

LTVDA
LTVCL
BLUE

RED
IREF
LMD[31:0]
HA[31:0] LDQM[3:0]

HD[63:0] LSRAS# Display

Displaycache
cache
(4MB
(4MBSDRAM
SDRAM
LSCAS#
100/133MHz)
100/133MHz)
ADS# LWE#
BNR#
LCS#
BPRI#
DBSY#
Pentium
Pentium DEFER#
processor
processor DRDY#
DQA[8:0]
HIT# Graphics
GraphicsMemory
Memory
Controller DQB[8:0]
HITM# Controller
Hub
Hub(GMCH
(GMCH- -82810E)
82810E)
HLOCK# RQ[7:5]/ROW[2:0]
HREQ[4:0] RQ[4:0]/COL[2:0]
HTRDY#
RS[2:0]# RDRAM
RDRAM
CPURST# CTM, CTM#
CFM, CFM#

CMD
SCK
SIO

HLSTRB#

HL [10:0]
HCOMP

HLSTRB
HUBREF
Floppy disk
PCI bus
810
810chipset
chipset
Serial port

Parallel port USB bus

Low Pin
Super
SuperI/O I/O
Mouse port I/O Count (LPC) I/OController
Controller IDE bus
interface Hub
Hub
K/B port
I/R port Audio bus (AC’97)
 Conclusions

• Move towards hub-based systems.

• Move to systems based around hot plug-and-play systems
such as Firewire and USB.
• Modern hub-based systems optimise the flow of data.
• PCI and ISA will be phased-out as they are legacy based.
• Enhanced memory devices, such as RDRAMs increase the
maximum transfer rate.