Top Level View of Computer Function and Interconnection

William Stallings
Computer Organization
and Architecture
8th Edition
Chapter 3
Top Level View of Computer
Function and Interconnection
Program Concept
• Hardwired systems are inflexible
• General purpose hardware can do
different tasks, given correct control
signals
• Instead of re-wiring, supply a new set of
control signals
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals
• We have a computer!
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• Combination of above
Example of Program Execution
Instruction Cycle State Diagram
Interrupts
• Virtually all computers provide a mechanism by
which other modules (I/O, memory) may
interrupt the normal processing of the
processor
• Interrupts are provided primarily as a way to
improve processing efficiency. e.g, most external
devices are much slower than the processor
— processor is transferring data to a printer using the instruction
cycle scheme.
— After each write operation, the processor must pause and
remain idle until the printer catches up. The length of this
pause may be on the order of many hundreds or even
thousands of instruction cycles that do not involve memory.
— Clearly, this is a very wasteful use of the processor.
Interrupts
Program Flow Control
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
INTERCONNECTION STRUCTURES
• All the units must be connected
• A computer consists of a set of components
or modules of three basic types (processor,
memory, I/O) that communicate with each
other
• The collection of paths connecting the various
modules is called the interconnection
structure.
• The design of this structure will depend on the
exchanges that must be made among modules.
• The figure suggests the types of exchanges that
are needed by indicating the major forms of
input and output for each module type
Computer Modules
Computer Modules
• The interconnection structure must
support the following types of transfers:
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Input/Output Module Connection(1)
• From an internal (to the computer
system) point of view, I/O is functionally
similar to memory.
—two operations, read and write.
• Further, an I/O module may control more
than one external device.
• We can refer to each of the interfaces to
an external device as a port and give each
a unique address (e.g., 0, 1, …, M - 1).
—In addition, there are external data paths for
the input and output of data with an external
device.
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
—e.g. spin disk
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
What is a Bus?
• A communication pathway connecting two
or more devices
• A key characteristic of a bus is that it is a
shared transmission medium
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels
• Power lines may not be shown
Buses
• There are a number of possible
interconnection bus systems
• Single and multiple BUS structures are
most common.
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)
• A bus that connects major computer
components (processor, memory, I/O) is
called a system bus.
Data Bus
• Carries data
—Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of
performance
—8, 16, 32, 64 bit
Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction (data) from a given
location in memory
• Bus width determines maximum memory capacity of
system
— e.g. 8080 has 16 bit address bus giving 64k address space
• Furthermore, the address lines are generally also used to
address I/O ports.
• Typically, the higher-order bits are used to select a
particular module on the bus, and the lower-order bits
select a memory location or I/O port within the module.
— For example, on an 8-bit address bus, address 01111111 and
below might reference locations in a memory module (module
0) with 128 words of memory, and address 10000000 and
above refer to devices attached to an I/O module (module 1).
Control Bus
• The control lines are used to control the
access to and the use of the data and
address lines.
• Because the data and address lines are
shared by all components, there must be a
means of controlling their use
• Control signals transmit both command and
timing information among system modules.
— Timing signals indicate the validity of data and address
information
— Command signals specify operations to be performed.
Control Bus
• Control and timing information

Operation of the bus
• The operation of the bus is as follows.
• If one module wishes to send data to
another, it must do two things:
1. obtain the use of the bus, and
2. transfer data via the bus.
• If one module wishes to request data from
another module, it must:
1. obtain the use of the bus, and
2. transfer a request to the other module over
the appropriate control and address lines.
3. It must then wait for that second module to
send the data.
Bus Interconnection Scheme
Big and Yellow?
• What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
– e.g. PCI
—Sets of wires
Physical Realization of Bus Architecture
Single Bus Problems
• Lots of devices on one bus leads to:
—Propagation delays
– Long data paths mean that co-ordination of bus use
can adversely affect performance
– If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to
overcome these problems
Traditional (ISA)
(with cache)
Traditional (ISA)
(with cache)
• It is possible to connect I/O controllers directly
onto the system bus.
• A more efficient solution is to make use of one or
more expansion buses for this purpose.
• An expansion bus interface buffers data transfers
between the system bus and the I/O controllers
on the expansion bus.
• This arrangement allows the system to support a
wide variety of I/O devices and at the same time
insulate memory-to-processor traffic from I/O
traffic.
High Performance Bus
High Performance Bus
• The cache controller is integrated into a bridge, or buffering
device, that connects to the high-speed bus
• This bus supports connections to
— high-speed LANs, such as Fast Ethernet at 100 Mbps
— video and graphics workstation controllers,
— as well as interface controllers to local peripheral buses, including
SCSI and FireWire.
• The advantage of this arrangement is that the high-speed bus
brings high demand devices into closer integration with the
processor and at the same time is independent of the
processor.
• Changes in processor architecture do not affect the high-
speed bus, and vice versa.
Elements of Bus Design
Bus Types
• Dedicated
—Separate data & address lines
• Multiplexed
—Shared lines
—Address valid or data valid control line
—Advantage - fewer lines save space and cost
—Disadvantages
– More complex control (circuitary)
– potential reduction in performance because certain
events that share the same lines cannot take place in
parallel.
Bus Arbitration
• More than one module controlling the bus
• e.g. CPU and DMA controller
• Only one module may control bus at one
time
• Arbitration may be centralised or
distributed
Centralised or Distributed Arbitration
• Centralised
—Single hardware device controlling bus access
– Bus Controller
– Arbiter
—May be part of CPU or separate
• Distributed
—Each module may claim the bus
—Access Control logic on all modules and the
modules act together to share the bus.
Timing
• Timing refers to the way in which events
are coordinated on the bus
• Synchronous
—Events determined by clock signals
—Control Bus includes clock line
—A single 1-0 is a bus cycle
—All devices can read clock line
—Usually sync on leading edge
—Usually a single cycle for an event
Synchronous read and write operations
Timing (simplified) Diagram
• The processor:
— places a memory address on the address lines during
the first clock cycle
— may assert various status lines.
— Once the address lines have stabilized, the processor
issues an address enable signal.
• For a read operation,
— the processor issues a read command at the start of the
second cycle.
— A memory module recognizes the address and, after a
delay of one cycle, places the data on the data lines.
— The processor reads the data from the data lines and
drops the read signal.
• For a write operation,
—the processor puts the data on the data lines
at the start of the second cycle
—and issues a write command after the data
lines have stabilized.
—The memory module copies the information
from the data lines during the third clock
cycle.
• With asynchronous timing, the
occurrence of one event on a bus
follows and depends on the occurrence
of a previous event.
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
Comparison
• Synchronous timing is simpler to
implement and test.
• However, it is less flexible than
synchronous timing.
—Because all devices on a synchronous bus are
tied to a fixed clock rate, the system cannot
take advantage of advances in device
performance.
• With asynchronous timing, a mixture of
slow and fast devices, using older and
newer technology, can share a bus.
POINT-TO-POINT INTERCONNECT
• The shared bus architecture was the standard
approach to interconnection between the
processor and other components (memory, I/O,
and so on) for decades.
• But contemporary systems increasingly rely on
point-to-point interconnection rather than shared
buses.
— At higher and higher data rates, it becomes increasingly
difficult to perform the synchronization and arbitration
functions in a timely fashion.
— point-to-point interconnect has lower latency, higher
data rate, and better scalability
• Intel’s QuickPath Interconnect (QPI), which was
introduced in 2008
• QPI
• PCIe
• Read from book

Top Level View of Computer Function and Interconnection

Uploaded by

Top Level View of Computer Function and Interconnection

Uploaded by

William Stallings

• Control and timing information

You might also like