IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS 521

Unified Architecture for Double/Two-Parallel

Single Precision Floating Point Adder
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, and Kolin Paul

Abstract—Floating point (F.P.) addition is a core operation for a for double precision with dual single precision support, targeted
wide range of applications. This brief presents an area-efficient, for normalized operands.
dynamically configurable, multiprecision architecture for F.P. ad- In this brief, we have developed an architecture for addi-
dition. We propose an architecture of a double precision (DP) tion arithmetic with double precision F.P. numbers which can
adder, which also supports a dual (two parallel) single precision
(SP) computational feature. Key components involved in the F.P. also support on-the-fly dual (two parallel) single precision F.P.
adder architecture, such as comparator, swap, dynamic shifters, numbers computations, named as DPdSP adder architecture.
leading one-detector (LOD), mantissa adders/subtractors, and We have designed and/or configured the key elements of F.P.
rounding circuit, have been redesigned to efficiently enable re- adder, to share them among different precision operands, to sup-
source sharing for both precision operands with minimal multi- port the multiprecision computation. The proposed architecture
plexing circuitry. The proposed design supports both normal and fully supports normal as well as sub-normal computations, with
sub-normal numbers. The proposed architecture has been synthe-
round-to-nearest rounding method. Other rounding methods
sized for OSUcells Cell 0.18 μm technology ASIC implementation.
Compared to a standalone DP adder with two SP adders, the can be easily included. We have compared our results with the
proposed unified architecture can reduce the hardware resources best optimized implementations available in the literature. The
by ≈ 35%, with a minor delay overhead. Compared to previous main contributions of this work can be summarized as follows:
works, the proposed dual mode architecture has 40% smaller • Proposed an architecture for DPdSP adder, which can
area × delay, and has better area and delay overhead over only
perform on-the-fly either a Double Precision or dual (two
DP adder.
parallel) Single Precision addition/subtraction.
Index Terms—ASIC, digital arithmetic, floating point (F.P.) • Components have been optimized/configured with tuned
addition, multiprecision arithmetic. data path, to minimize the multiplexing circuitry, for re-
I. I NTRODUCTION ducing the area and delay metrics. It can be easily extend
for any dual precision F.P. adder implementation.

F LOATING POINT (F.P.) addition is a core arithmetic

operation in a multitude of scientific and engineering
computations. Over the past few decades, considerable work
• Compared to previous works, the proposed work provides
more computational support, and has smaller area over-
head over only DP design with similar or smaller delay
have been done to improve the architecture of floating point overhead.
arithmetic [1], [2]. In view of the large area requirement of
F.P. arithmetic per unit computation, we aim for a unified
multiprecision architecture. II. P ROPOSED DPdSP A DDER A RCHITECTURE
In literature, some authors have focused on multiprecision
A basic state-of-the-art flow [9] of the floating point addition
floating point arithmetic architecture design. Many of these are
is given below in Algorithm 1. In the present work of DPdSP
focused on multiprecision F.P. multiplier architecture design
adder architecture, we have followed the complete steps de-
[3], [4], which supports only normalized numbers. Isseven et al.
scribed in Algorithm 1 and constructed them for the support
[5] has presented a multiprecision divider for quadruple and
of the dual mode operation.
dual double precision operands. A. Akkas [6] has shown multi-
precision architectures for F.P. addition, which has been further
extended in [7] with single path and two path design. How- Algorithm 1 F.P. Adder Computational Flow [9]
ever, both of them have designed to support only normalized
numbers. The computation related to sub-normal numbers and 1: (IN 1, IN 2) Input Operands;
exceptional case handling were left for software processing. 2: Data Extraction & Exceptional Check-up:
Further, Ozbilen et al. [8] has presented an adder architecture 3: {S1(Sign1), E1(Exponent1), M1(Mantissa1)} ← IN 1
4: {S2, E2, M2} ← IN 2
Manuscript received February 3, 2014; accepted May 25, 2014. Date of 5: Check for INFINITY, SUB-NORMALs, NAN
publication May 29, 2014; date of current version July 16, 2014. This work was 6: Update hidden bit of Mantissa’s for SUB-NORMALs
supported in part by Croucher Startup Allowance. This brief was recommended 7: COMPARE, SWAP & Dynamic Right SHIFT:
by Associate Editor Y. Ha.
M. K. Jaiswal and R. C. C. Cheung are with Department of Electronic
8: IN 1_gt_IN 2 ← {E1, M 1} ≥ {E2, M 2}
Engineering, City University of Hong Kong, Kowloon, Hong Kong (e-mail: 9: Large_E, M ← IN 1_gt_IN 2? E1,M1: E2,M2
manish.kj@my.cityu.edu.hk; r.cheung@cityu.edu.hk). 10: Small_E, M ← IN 1_gt_IN 2? E2,M2: E1,M1
M. Balakrishnan and K. Paul are with Department of Computer Science and 11: Right_Shift ← Large_E − Small_E
Engineering, Indian Institute of Technology, New Delhi 110 016, India (e-mail:
mbala@cse.iitd.ernet.in; kolin@cse.iitd.ernet.in). 12: Small_M ← Small_M  Right_Shift
Digital Object Identifier 10.1109/TCSII.2014.2327314 13: Mantissa Computation:

1549-7747 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
522 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS

14: OP ← S1 ⊕ S2
15: if OP == 1 then
16: Add_M ← Large_M + Small_M
17: else
18: Add_M ← Large_M − Small_M
19: Leading-One-Detection & Dynamic Left SHIFT:
20: Left_Shift ← LOD(Add_M)
21: Left_Shift ← Adjustment for SUB-NORMAL or Under-
flow or No-Shift(True Add_M MSBs)
22: Add_M ← Add_M  Left_Shift
23: Normalization & Rounding:
24: Mantissa Normalization & Compute Rounding ULP
based on Guard, Round & Sticky Bit
25: Add_M ← Add_M + ULP
26: Large_E ← Large_E + Add_M[MSB] − Left_Shift
27: Finalizing Output:
28: Update Exponent & Mantissa for Exceptional Cases
29: Determine Final Output

The proposed architecture of double precision with dual

single precision support (DPdSP) floating point adder is shown
in Fig. 1. Two 64-bit input operands, may contain either
1-set of double precision or 2-sets of single precision operands.
First operand contains either first input of DP or first inputs
of both SPs, and second operand contains second inputs of
either of DP or both SPs. Based on the signal dp_sp, it can
be dynamically switched to either double precision or dual
single precision mode (dp_sp : 1 → DP Mode, dp_sp : 0 →
Dual SP Mode). All the computational steps in dual mode is
discussed below in detail. The explanation has been in relation
to the state-of-the-art flow discussed in Algorithm 1.

A. Data Extraction and Subnormal Handler

Fig. 1. DPdSP adder architecture (with a 4-stage pipeline).
Computation of this sub-component is shown in Fig. 2.
In this part, the sign, exponent and mantissa of single or
double precision operands have been extracted from the input been established. Even for only double precision, we require
operands, according to the floating point formats of single and the same/similar components for comparator, which have been
double precision [9]. configured to support DP with dual SP processing.
The exponents have been checked for sub-normal condition
by NOR of their bits. Since, 8-bit exponents of double precision C. SWAP: Large Sign, Exponent, Mantissa, and Operation
and second single precision overlapped, their sub-normal check
have been shared to save some resources. Further, all the The underlying computation of this sub-component is
exponents and mantissas have been updated according to the shown in Fig. 2. This section of the architecture determines
result of sub-normal checks’. In this part, compared to only the effective operation between large and small mantissa
double precision, we need extra resources for sub-normal check (addition/subtraction). This also produces the large sign (in ef-
and update for first single precision operands. Similar to sub- fect output sign bits), small and large exponents, and small and
normal checks, the checks for infinity and nan has been large mantissa. For SWAP, in general, we need four 8-bit (for
shared among DP and SP. both SP exponents), two 10-bit (for DP exponent), four 24-bit
(for both SP mantissas) and two 53-bit (for DP mantissa) SWAP
components for all the computations of this section. However,
B. Comparator
by multiplexing either of the double precision or both single
This component has been shared among operands, with the precision operands, we need only four 8-bit (for exponents) and
resource used only for double precision operands. Related four 32-bit (for mantissas) SWAP circuitry for entire processing.
computation of this sub-unit is shown in Fig. 2. A 31-bit Effectively, it needs SWAP components slightly more than we
comparator (for “greater than”) is used for first single precision require for only DP, along with extra multiplexing circuitry.
operands comparison. Another, 31-bit “greater than” compara- Among extra appended LSB ZEROs in mantissa multiplexing
tor is used for second single precision operands. By combining (for m1 and m2), 3-bit are for Guard, Round, and Sticky bit
these two outputs with a 31-bit “equal to” and 1-bit “greater computations in Rounding phase, and remaining can provide
than equal to” comparator, the double precision comparison has extended precision support to the operands. The output m_L
JAISWAL et al.: UNIFIED ARCHITECTURE FOR SINGLE PRECISION FLOATING POINT ADDER 523

contains two multiplexers for each 32-bit blocks, which shift

their inputs based on the corresponding shifting bit (either
of double or single precision). Along with this, it contains a
multiplexer which can select between lower shifting output or
their combination with primary input to the stage, based on
the true dp_sp and corresponding shifting bit of dp_r_shif t.
Except this multiplexer, the architecture behaves like two 32-bit
barrel shifter, which have been constructed to support dual
mode shifting operation. The proposed dual mode dynamic
right shifter takes approximately similar area with minor delay
overhead than a single mode 64-bit dynamic right shifter.

F. Mantissa Addition and SUM Normalization

This unit uses two 32-bit adder-subtraction (add-sub) units.
The input operands to this section are m_L from SWAP unit and
right shifted small mantissa from dynamic right shifter. For true
dp_sp, both adders perform together for DP processing, and for
false dp_sp, they perform individually for both SP’s. In effect,
this unit requires the resources similar to only double precision
processing. The “Mantissa SUM Normalization” unit combine
the previous two 32-bit sum operation, to generate actual sum
(either for DP or SP’s), mantissa overflow bits, and the inputs
Fig. 2. DPdSP adder: Sub-components. for LOD. generally, for only DP it requires a 1-bit shifter of
64-bits, whereas in dual mode it has been accomplished by two
1-bit shifters of 31-bits each, along with some gates for small
contains mantissa of either large DP operand or both of large SP control logics, as shown in Fig. 2.
operands. Similarly, m_S contains small mantissas. Likewise,
e_L contains large exponent, and e_S contains small expo-
nents, either of DP or both SP operands. G. Leading-One-Detector and Left Shift Update
This section of the architecture is meant to detect leading
D. Right Shift Amount one in the add_m, in case it has lost its MSB, to bring it
The right shift amount has been determined by the difference in to normalized format after left shifting. It happens when
between large and small exponents, generated in SWAP unit. In two mantissa, values are very close to each other, undergoes
general, it requires two 8-bit subtractors for single precision and subtraction operation. Input to the leading-one-detector (LOD)
one 11-bit subtractor for double precision. However, because would be either a DP operand or two SP operands, generated
of effective multiplexing of operands in SWAP section, we need from mantissa sum normalizer unit. LOD unit architecture is
only one 16-bit subtractor for this. It will produce either shift shown in Fig. 3(b). It consists of two 32-bit LOD, each of
amount for double precision or for both single precision. For which processes 32-bit input on LOD_in. Their individual
shift amount, compared to only double precision, it requires outputs acts as SP left shift amount, which after combining act
extra resources for 5-bit subtraction. Other processing in this as DP left shift amount. The architecture of 32-bit LOD is based
section are bit-wise operations, and are done separately for on a easy hierarchical flow shown in Fig. 3(b). Based on the
all operands. Computation of this sub-component is shown in above approach, this can be easily extend to larger size LOD.
Fig. 2. The LOD, in effect, uses same resources as used for only DP
processing.
Further to quantify the left shift amount, it has been up-
E. Dynamic Right Shifter
dated for sub-normal cases (both sub-normal input operands),
This component in the adder architecture is for the right underflow cases (if the left shift amount exceeds or equals to
shifting of small mantissa which is used to align the decimal the corresponding large exponent), and no-shift case (add_m
points of mantissas. The architecture of the dual mode dynamic MSBs are true, either for DP or SPs). For both sub-normal input
right shifter is shown in Fig. 3(a). The input to this unit operands case or the no-shift case, the corresponding left shift
is small mantissas m_S from SWAP unit, and right shifted is forced to zero, and for the underflow case, the corresponding
amount dp_r_shif t, sp2_r_shif t, and sp1_r_shif t. When left shift is equal to corresponding large exponent decremented
dp_sp is true, the sp2_r_shif t = sp1_r_shif t = 0, and when by one. Further, for true dp_sp, the SP left shifts are forced to
it is false, dp_r_shif t = 0. When MSB of dp_r_shif t is zero, and for false dp_sp the DP left shift is forced to zero.
true (in case dp_sp = 1) the 64-bit input is right shifted by In the left shift update section, the exponent decremented part
32-bit. All the other stages (Stage-1 to Stage-5) work on the of DP and first SP has been shared. This becomes possible
dual shift mode, and are parameterized for their inputs. The because the required LSBs of e_L has been shared among them.
proposed dynamic right shifter can be easily extended for All other computation, related to left shift update need to be
any size dual mode dynamic shifting. Each of these stages computed separately for DP and both SP.
524 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS

Fig. 3. DPdSP adder: Dynamic left/right shifter, LOD. (a) Dual mode dynamic right shifter; (b) dual mode leading-one-detector; and (c) dual mode dynamic left
shifter.

H. Dynamic Left Shifter adder in effect is similar to that required for only DP processing.
Further to rounding of the mantissa, the exponents has been
The architecture of dual mode dynamic left shifter is shown
updated, for mantissa overflow. For this, each exponent update
in Fig. 3(c). The input to this unit are mantissa addition add_m,
may require to be incremented by one. One adder has been
and updated left shift amount from previous stage. The basic
shared for DP and one SP-1, because of shared operands in
idea of this is similar to dual mode dynamic right shifter. It
e_L. Further to this, each exponent has been updated for either
contains two left shifters to process each of the 32-bit inputs
of infinity, sub-normal or underflow cases, and each requires
in this stage. In comparison to right shifter, the additional
separate units. The computed signs, exponents and mantissas
multiplexer is used to process the higher left shift output or its
of double precision and both single precision have been finally
combination with primary input of the stage. Furthermore, this
multiplexed to produce the final 64-bit output, which either
is also parameterized and can be easily extended for any amount
contains a DP output or two SP outputs.
of dual mode dynamic left shifting.
Thus, the complete architecture needs only one multiplexer
for multiplexing the operands, and this belongs to the SWAP
I. Exponent Update section. All other processing data path components have been
tuned to follow those operands to support dual mode operations
In this unit the exponents have been updated for mantissa
without any further extra multiplexing circuitry, except the last
overflow and mantissa underflow. The exponents need to be
one to produce the final 64-bit output. A brief summary of
incremented by one or decremented by left shift amount. This
shared resources and extra resources over only DP adder is
update has been shared for DP and one SP, by sharing a
shown in Table I.
subtractor. This need an extra 5-bit adder for a SP processing
as an overhead over DP processing.
III. I MPLEMENTATION R ESULTS AND C OMPARISONS
J. Rounding and Final Processing
The proposed architecture is synthesized using the open-
The primary operands for this section is the left shifted source “OSUcells Cell [10]” 0.18 μm technology, using Syn-
mantissa from previous dual mode dynamic left shifter. The opsys Design Compiler. We have also synthesized only DP
add_m_shif ted consists either of DP or both SP in each of and only SP adder using similar data path computational
its 32-bit parts. Based on the MSBs of the add_m_shif ted, flow, for comparison purpose. The implementation details have
the rounding position need to be determined. Right next bit been shown in Table II. Each module has been synthesized
to the rounding position is the Guard-bit, the next right is for best possible delay. The proposed DPdSP architecture
Round-Bit, and remaining right bits generate Sticky-bit. Based needs roughly 15% more hardware and 7% extra delay than
on the rounding position bit, Guard-bit, Round-bit, Sticky-bit only DP adder, however has 37% saving when compared to
and MSB-bit, the round ULP (unit at last place) has been combined one DP with 2 SP modules (Area(DP + 2∗ SP) −
computed. This need to perform separately for DP and both SP Area(DPdSP)/Area(DP + 2∗ SP)).
and requires few gates for each. Approximately we need thrice A comparison with previous works is shown in Table III.
of DP only computation. After generating the ULP, it has been Other previously reported DPdSP adder designs [6]–[8] sup-
added to add_m_shif ted using two 32-bit adders, individually port only normal implementation, and lacks exceptional case
works for SP computation, and collectively produce the output handling. Though the inclusion of sub-normal support and
for DP (similar to the case of mantissa addition). Further, exceptional case handling is not difficult, it affects the overall
this rounded mantissa sum has been normalized. The rounding area and critical path delay significantly [11], [12]. Because
JAISWAL et al.: UNIFIED ARCHITECTURE FOR SINGLE PRECISION FLOATING POINT ADDER 525

TABLE I
R ESOURCE S HARING IN DPdSP A DDER S UB -C OMPONENTS

TABLE II design has smaller area and delay overhead when compared to
ASIC I MPLEMENTATION D ETAILS
only DP, and has 40%–50% smaller area × delay product. The
proposed DPdSP architecture provides full support to normal
and sub-normal, along with relevant exceptional case handling.

IV. C ONCLUSION
TABLE III In this brief, we have presented an architecture for floating
C OMPARISON W ITH R ELATED W ORK point adder with on-the-fly dual precision support, with both
normal and sub-normal support, and exceptional case han-
dling. It supports double precision with dual single precision
(DPdSP) adder computation. The data path has been tuned
with minimal required multiplexing circuitry. The supporting
sub-components have been tuned for on-the-fly dual mode
computation. It needs approx 15% more resources than DP
module and has a benefit of more than 37% reduction in area
when compared to combined single DP and two SP module.
In comparison to previous works in literature, our proposed
DPdSP design has 40–50% smaller area × delay product, and
has smaller area and delay overhead when compared to only
DP, and provide more computational support.

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