Microprocessors and Microcontrollers Module 5

MODULE 5
Data Processing Instructions
 The data processing instructions manipulate data within registers. They are move
instructions, arithmetic instructions, logical instructions, compare instructions and
multiply instructions.
 Most data processing instructions can process one of their operands using the barrel
shifter.
 If S is suffixed on a data processing instruction, then it updates the flags in the cpsr.
MOVE INSTRUCTIONS:
 It copies N into a destination register Rd, where N is a register or immediate value. This
instruction is useful for setting initial values and transferring data between registers.

Syntax: <instruction> {<cond>} {S} Rd, N

 In the example shown below, the MOV instruction takes the contents of register r5 and
copies them into register r7.

USING BARREL SHIFTER WITH DATA TRANSFER INSTRUCTION:

 Data processing instructions are processed within the arithmetic and logic unit (ALU).
 A unique and powerful feature of the ARM processor is the ability to shift the 32-bit
binary pattern in one of the source registers left or right by a specific number of positions
before it enters the ALU.
 This shift increases the power and flexibility of many data processing operations.
 For example, We apply a logical shift left (LSL) to register Rm before moving it to the
destination register.
PRE r5=5
r7=8
MOV r7, r5, LSL #2
POST r5=5
r7=20
 The above example shift logical left r5=5 (00000101 in binary) by two bits and then
r7=20 (00010100 in binary).

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Figure: Barrel shifter and ALU

 Following table shows barrel shifter operation

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ARITHMETIC INSTRUCTIONS:
 The arithmetic instructions implement addition and subtraction of 32-bit signed and
unsigned values.
Syntax: <instruction>{<cond>} {S} Rd, Rn, N

 In the following example, subtract instruction subtracts a value stored in register r2 from
a value stored in the register r1. The result is stored in register r0.

 In the following example, the reverse subtract instruction (RSB) subtract r1 from the
constant value #0, writing the result in r0.

USING THE BARREL SHIFTER WITH ARITHMETIC INSTRUCTIONS:

 Example below illustrates the use of the inline barrel shifter with an arithmetic
instruction. The instruction multiplies the value stored in register r1 by three.
 Register r1 is first shifted one location to the left to give the value of twice r1. The ADD
instruction then adds the result of the barrel shift operation to register r1. The final result
transferred into register r0 is equal to three times the value stored in register r1.

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LOGICAL INSTRUCTIONS:
 Logical instructions perform bitwise operations on the two source registers.
Syntax: <instruction> {<cond>} {S} Rd, Rn, N

 In the example shown below, a logical OR operation between registers r1 and r2 and the
result is in r0.

COMPARISON INSTRUCTIONS:
 The comparison instructions are used to compare or test a register with a 32-bit value.
They update the cpsr flag bits according to the result, but do not affect other registers.
 After the bits have been set, the information can be used to change program flow by
using conditional execution.
Syntax: <instruction> {<cond>} Rn, N

 Example shown below for CMP instruction, both r0 and r1 are equal before the execution
of the instruction. The value of the z flag prior to the execution is 0 and after the
execution z flag changes to 1 (upper case of Z).

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The CMP is effectively a subtract instruction with the result discarded;

Similarly the TST instruction is a logical AND operation and TEQ is a logical XOR
operation. For each, the results are discarded but the condition bits are updated in the
cpsr.
MULTIPLY INSTRUCTIONS:
 The multiply instructions multiply the contents of a pair of registers and depending upon
the instruction, accumulate the results in another register.
 The long multiplies accumulate onto a pair of registers representing a 64-bit value.
Syntax: MLA {<cond>} {S} Rd, Rm, Rs, Rn
MUL {<cond>} {S} Rd, Rm, Rs

Syntax: <instruction> {<cond>} {S} RdLo, RdHi, Rm, Rs

 In the following example below shows a multiply instruction that multiplies registers r1
and r2 and places the result into the register r0.

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 The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL) produce a 64-
bit result.

BRANCH INSTRUCTIONS
Q2. Explain briefly branch instructions of ARM processor.
Answer:
 A branch instruction changes the flow of execution or is used to call a routine.
 This type of instruction allows programs to have subroutines, if-then-else structures, and
loops.
 The change of execution flow forces the program counter (pc) to point to a new address.

 T refers to the Thumb bit in the cpsr.

 When instruction set T, the ARM switches to Thumb state.
 The example shown below is a forward branch. The forward branch skips three
instructions.

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 The branch with link (BL) instruction changes the execution flow in addition
overwrites the link register lr with a return address. The example shows below a
fragment of code that branches to a subroutine using the BL instruction.

The branch exchange (BX) instruction uses an absolute address stored in register Rm.
It is primarily used to branch to and from Thumb code. The T bit in the cpsr is updated
by the least significant bit of the branch register.
 Similarly, branch exchange with link (BLX) instruction updates the T bit of the cpsr
with the least significant bit and additionally sets the link register with the return
address.
LOAD-STORE INSTRUCTIONS
 Load-store instructions transfer data between memory and processor registers. There are
three types of load-store instructions: single-register transfer, multiple-register transfer,
and swap.
a) Single-Register Transfer
 These instructions are used for moving a single data item in and out of a register.
 Here are the various load-store single-register transfer instructions.
Syntax: <LDR|STR>{<cond>}{B} Rd, addressing1
LDR{<cond>}SB|H|SH Rd, addressing2
STR{<cond>}H Rd, addressing2

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 Example:
1. LDR r0, [r1]
o This instruction loads a word from the address stored in register r1 and places it
into register r0.

2. STR r0, [r1]

 This instruction goes the other way by storing the contents of register r0 to the
address contained in register r1.

b) Multiple-Register Transfer
 Load-store multiple instructions can transfer multiple registers between memory and the
processor in a single instruction. The transfer occurs from a base address register Rn
pointing into memory.
 Multiple-register transfer instructions are more efficient from single-register transfers for
moving blocks of data around memory and saving and restoring context and stacks.

Syntax: <LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{ˆ}

 Here N is the number of registers in the list of registers.

c) SWAP Instruction
 The swap instruction is a special case of a load-store instruction. It swaps the
contents of memory with the contents of a register.

Syntax: SWP {B} {<cond>} Rd, Rm, [Rn]

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Addressing modes:
Single-Register Load-Store Addressing Modes
 The ARM instruction set provides different modes for addressing memory.
 These modes incorporate one of the indexing methods: preindex with writeback,
preindex, and postindex

Example:

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Addressing mode for load-store multiple instructions

 Table below shows the different addressing modes for the load-store multiple
instructions.

Example:
mem32[0x8001c] =0x04

 If LDMIA is replaced with LDMIB post execution the content of registers is shown
below

STACK OPERATIONS
 The ARM architecture uses the load-store multiple instructions to carry out stack
operations.
 The pop operation (removing data from a stack) uses a load multiple instruction;
similarly, the push operation (placing data onto the stack) uses a store multiple
instruction.

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 When you use a full stack (F), the stack pointer sp points to an address that is the last
used or full location.
 In contrast, if you use an empty stack (E) the sp points to an address that is the first
unused or empty location.
 A stack is either ascending (A) or descending (D). Ascending stacks grow towards
higher memory addresses; in contrast, descending stacks grow towards lower memory
addresses.
 Addressing modes for stack operation

 The LDMFD and STMFD instructions provide the pop and push functions, respectively.
 Example1: With full descending

Figure: STMFD instruction full stack push operation.

Example 2: With empty descending

Figure: STMED instruction empty stack push operation.

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SOFTWARE INTERRUPT INSTRUCTION

Q3. Explain briefly the software interrupt instruction.
Answer:
 A software interrupt instruction (SWI) causes a software interrupt exception, which
provides a mechanism for applications to call operating system routines.

Syntax: SWI {<cond>} SWI_number

 When the processor executes an SWI instruction, it sets the program counter pc to the
offset 0xB in the vector table.
 The instruction also forces the processor mode to SVC, which allows an operating system
routine to be called in a privileged mode.
 Each SWI instruction has an associated SWI number, which is used to represent a
particular function call or feature.
 The example below shows an SWI call with SWI number 0x123456, used by ARM
toolkits as a debugging SWI.

 Since SWI instructions are used to call operating system routines, it is required some
form of parameter passing.
 This achieved by using registers. In the above example, register r0 is used to pass
parameter 0x12. The return values are also passed back via register.

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Program Status Register Instructions

Q4. Explain briefly program status register instructions.
Answer:
 The ARM instruction set provides two instructions to directly control a program status
register (psr).
 The MRS instruction transfers the contents of either the cpsr or spsr to general purpose
register.
 The MSR instruction transfers the contents of a general purpose register to cpsr or spsr.
 Together these instructions are used to read and write the cpsr and spsr.
Syntax: MRS {<cond>} Rd <cpsr |spsr>
MSR {<cond>} <cpsr|spsr} _<fields>,Rm
MSR {<cond>} <cpsr|spsr} _<fields>, #immediate
 The table shows the program status register instructions

Coprocessor Instructions
Q5. Explain briefly coprocessor instructions.
Answer:
 Coprocessor instructions are used to extend the instruction set.
 A coprocessor can either provide additional computation capability or be used to control
the memory subsystem including caches and memory management.
 These instructions are used only by core with a coprocessor.
Syntax: CDP {<cond>} cp,opcode1, Cd, Cn {,opcode2}
<MRC|MCR>{<cond>}cp,opcode1,Rd,Cn,Cm{,opcode2}
<LDC|STC>{<cond>}cp,Cd,addressing

 In the syntax of the coprocessor instructions, the cp field represents the number between
p0 and p15. The opcode fields describe the operation to take place on the coprocessor.
The Cn, Cm and Cd fields describe registers within the coprocessor.
 For example: The instruction below copies coprocessor CP15 register c0 into a general
purpose register r10.

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MRC p15, 0, r10, c0, c0, 0 ; CP15 register-0 is copied into general purpose
register r10.
 For example: The instruction below moves the contents of CP15 control register c1 into
register r1 of the processor core.
MRC p15, 0, r1, c1, c0, 0
Loading Constants
Q6. Explain briefly the loading constants.
Answer:
 There are two pseudo instructions to move a 32-bit constant value to a register.
Syntax: LDR Rd, =constant
ADR Rd, label

 The example below shows an LDR instruction loading a 32-bit constant 0xff00ffff into
register r0.
LDR r0, =0xff00ffff
Programs:
1. Write ALP program for ARM7 demonstrating the data transfer.
Answer:
AREA DATATRANSFER, CODE, READONLY
ENTRY
LDR R0, =SRC
LDR R1, =DST
LDR R2, = 20
WORDCOPY LDR R3, [R0], #4
STR R3, [R1], #4
SUBS R2, R2, #1
BNE WORDCOPY
SRC DCD 1,2,3,4,5,6,7,8,1,2,3,4,5,6,7,8,1,2,3,4
AREA BLOCKDATA, DATA, READWRITE
DST DCD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
END

2. Write ALP program for ARM7 demonstrating logical operation.

Answer:
AREA LOGIC, CODE, READONLY
ENTRY
LDR R0, =5
LDR R1, =3

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AND R4, R0, R1

ORR R5, R0, R1
EOR R6, R0, R1
BIC R7, R0, R1
END
3. Write ALP program for ARM7 demonstrating arithmetic operation.
Answer:
AREA ARITH, CODE, READONLY
ENTRY
LDR, R1, =20
LDR R2, =25
ADD R3, R1, R2
MUL R4, R1, R2
SUB R5, R1, R2
END
4. Write ALP using ARM instructions that calls subroutine fact to find factorial of a given
number.
Answer:
AREA Factorial, CODE, READONLY
ENTRY
LDR R0, =VALUE
BL FACT // Branch with link
LDR R1, =0X40000000
STR R5, [R1]
STOP B STOP
AREA DATA, CODE
VALUE DCD 0A
FACT
MOV R6, R14 // store the return address in R6
LDR R2, [R0]
CMP R2, #00
BEQ END1
MOV R3, R2
LOOP
SUB R2, R2, #01
CMP R2, #00
MULNE R3, R2, R3
BNE LOOP
MOV R5, R3
B END2

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END1
LDR R5, =0X01
END2
MOV PC, R6
END

5. Write ALP program to add array of 16 bit numbers and store the result in memory.
Answer:
AREA AryAdd, CODE, READONLY
ENTRY
LDR R0, =SCR ; pointer to source array
LDR R1, = DST ; pointer to destination
LDR R2, =5 ; count of numbers
LDR R5, =0 ; initial sum
UP LDRH R3, [R0] ; 1st number in R2
ADD R5, R5, R3 ; add numbers
ADD R0, R0, #2 ; increment pointer to next number
SUBS R2, R2, #1 ; decrement count by 1
CMP R2, #0
BNE UP
STRH R5, [R1]
SRC DCW 10, 20, 30, 40, 50
AREA BLOCKDATA, DATA, READWRITE
DST DCW 0
END

6. Write ALP program to Fibonacci of given number.

AREA FIB, CODE, readonly

ENTRY
LDR R1, =0A //Number of Fibonacci numbers generated//
LDR R2, =0X40000000 ; /*Memory address where Fibonacci numbers are
saved*/
LDR R3, =0X00
MOV R6, R2
STR R3, [R2], #04
ADD R3, R3, #01
MOV R7, R2

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STR R3, [R2], #04

SUB R1, R1, #02 ; decrement count by 2 as 2 numbers are generated
BACK LDR R4, [R6], #04 ; R4 = 1st number
LDR R5, [R7], #04 ; R5 = 2nd number
ADD R5, R4, R5 ; add 1st and 2nd number to generate 3rd number
STR R5, [R2], #04
SUB R1, R1, #1
CMP R1, #0
BNE BACK
END

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