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Volume-7, Issue-1, January-February 2017

International Journal of Engineering and Management Research
Page Number: 411-415

Xilinx Implementation of Pulse Width Modulation Generation using

FPGA
Rahul Patel1, Prof. Vijay Prakash Singh2
1
(M.Tech Student) Department of Electronics and Communication, SSSUTMS University, Sehore, INDIA
2
Department of Electronics & Communication Engineering, SSSUTMS University, Sehore, INDIA

ABSTRACT carriers. Some methods use carrier disposition and others

Multi level inverter is used in applications that need use phase shifting of multiple carrier signals. [1]
high voltage and high current. The topologies of multilevel Xilinx field programmable gate arrays (FPGA's)
inverter have several advantages such as lower EMI are standard integrated circuits that can be programmed by
generation, better output waveform and higher efficiency for a user to perform a variety of complex logic functions. The
a given quality of output waveform. In this paper a XILINX
high level of integration available with these devices
FPGA based multilevel PWM controller design is simulated
and compilation portion is tested through VHDL in real time (currently up to 500,000 gates) means that they can be used
process using hardware-co simulation. The effective to implement complex electronic systems. Furthermore,
controller maintains the voltage to frequency ratio constant. there are many advantages due to the rapid design process
The simulation with experimental results demonstrates and reprogrammable functions. XILINX FPGA enables to
quality of voltage and current waveforms with less harmonic produce prototype logic designs right in a short period. It is
content at the output of the cascaded inverter. In this paper possible to create, implement, and verify a new design. This
we have implemented multilevel inverter using FPGA for the is a sharp contrast to conventional gate array design
hardware implementation of proposed methodology. processes, which can take months to produce working
silicon. The FPGA architecture consists of three types of
Keyword-- Cascaded Multilevel Inverter, FPGA, Pulse configurable elements - a perimeter of input/output blocks
Width Modulation, XILINX. (IOBs), a core array of configurable logic block (CLBs),
and resources for interconnection. The IOBs provide a
programmable interface between the internal array of logic
I. INTRODUCTION blocks (CLBs) and the device's external package pins.
CLBs perform user-specified logic functions, and the
Multilevel inverters have been attracting interconnect resources carry signals among the blocks. A
increasing attention in the past few years as power Inverters configuration program stored in internal static memory cells
of choice in many applications. They have significant determines the logic functions and the interconnections.
advantages over the conventional one because of the The configuration data is loaded into the device during
capability to reduce the undesirable harmonics in order to power-up reprogramming functions. [1]
improve the performance and efficiency. Various
topologies to realize these inverters have been introduced II. PROPOSED METHODOLOGY
and studied recently. Waveform synthesis methods for these
inverters include staircase modulation, sine-triangle carrier This details a pulse width modulation (PWM)
modulation, space vector modulation, and other predictive generator component for use in CPLDs and FPGAs, written
methods. Normally the topological structure of multilevel in VHDL. The component outputs PWM signals based on
inverter suggested must cope with the following points: 1) the duty cycle set by user logic. The center of each pulse
It should have less switching devices as far as possible, 2) It occurs at the PWM frequency, and the pulse width varies
should be capable of enduring very high input voltage such around the center. If set to multiple phases, the component
as HVDC transmission for high power applications, and 3) generates one PWM signal for each phase, evenly spaced.
Each switching device should have lower switching For example, when set to three phases, it generates three
frequency owing to multilevel approach. PWM outputs 120° out-of-phase with one another. The
PWM generation is considered the more important in the component was designed with Quartos II, version 12.1 and
inverter design and several multicarrier techniques have tested with ModelSim Altera 10.1b. Resource requirements
been developed to reduce the distortion in multilevel depend on the implementation. Fig. 1 illustrates a typical
inverters, based on the classical (SPWM) with triangular example of the PWM generator integrated into a system.

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Table 1: Generic Parameters

Generic Data Description
Type
sys_clk Integer System clock frequency in
Hz.
pwm_freq Integer Frequency of PWM in Hz.
bits_resolution Integer The number of bits of
resolution setting the duty
cycle.
Figure 1: Example Implementation Phases Integer The number of output
PWMs and phases.
A. Theory of Operation
The system clock divided by the PWM frequency Design properties of any project play’s an
equals the number of system clock pulses in one PWM important role for project implementation. In the design
period. Counters define this PWM period for each phase. properties the main things are use the change the target
There is one counter for each PWM phase, with their values device project information. For details, see Changing
offset by the phase. Each counter increments on each Design Properties. Figure 3 shows all the parameter with
system clock and clears once it reaches the end of its specification of parts.
period.
The duty cycle determines the points during the
period when the PWM signal’s rising and falling edges
occur. Figure 2 illustrates the basic concept used to
determine these positions. The signal’s falling edge happens
at ½ duty cycle, and its rising edge happens at the end of the
period minus ½ duty cycle. Once the counter reaches each
of these positions, the PWM signal is toggled as
appropriate. Since a half duty cycle can never exceed a half
period, the falling edge always occurs before the rising
edge.

Figure 3: Design Properties

B. RTL View of Proposed Work

Figure 2: Waveform of a Pulse in Phase with the PWM

Period

The PWM generator is configured using four

GENERIC parameters, set in the ENTITY. Table 1 lists the
parameters. The PWM generator does not require a specific
input clock, so long as the user sets the sys_clk parameter to
the clock frequency provided. The parameter pwm_freq
corresponds to the PWM frequency. The bits_resolution
determines the resolution of the pulse width. For example, a
value of 8 provides 8 bits of resolution. Therefore, the pulse
width’s resolution is 28 or 256, so in this case, the finest
possible pulse width adjustment is the period (i.e.
1/pwm_freq) divided by 256. The parameter phases sets the
Figure 4: RTL Design View
number of outputs and their relation to one another. The
number of PWM outputs is phases, and these outputs are
After the HDL synthesis phase of the synthesis
360°/phase’s out-of-phase with one another.
process, you can display a schematic representation of your
synthesized source file. This schematic shows a
representation of the pre-optimized design in terms of
generic symbols, such as adders, multipliers, counters,
AND gates, and OR gates, that are independent of the

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 www.ijemr.net ISSN (ONLINE): 2250-0758, ISSN (PRINT): 2394-6962

targeted Xilinx® device. Viewing this schematic may help of the cascaded inverter. Fig 6 shows the sinusoidal wave
you discover design issues early in the design process. and 1800 phase shift sinusoidal wave (inverse sinusoidal
wave) as a reference signals.
III. SIMULATION AND RESULTS
The output and the result of proposed method is
show in the ModelSim. ModelSim is a multi-language HDL
simulation environment by Mentor Graphics, for simulation
of hardware description languages such
as VHDL, Verilog and System C, and includes a built-in C
debugger. ModelSim can be used independently, or in
conjunction with Altera Quartus or Xilinx ISE. Simulation
is performed using the graphical user interface (GUI), or
automatically using scripts.
For any type of switching generation the first basic
phenomena is generation of sin wave so first generate the
sine wave on the ModelSim. Further implement the
different switching technique for PWM and other for hybrid Figure 6: Sinusoidal wave as a reference signal
implementation. Figure 5 shows the VHDL coded
ModelSim output of sine wave. In the VHDL inbuilt i-sim The three carrier signals (such as sawtooth waves)
simulator but that is not sufficient to show the sin wave in are generated using an up-counter design. The first
the simulator that’s why for the representation of sin wave sawtooth carrier signal is generated from 20-bit up counter
use the ModelSim simulator. and these signals phase are shifted to 1200 for second
sawtooth carrier signals and 2400 for third sawtooth carrier
signals. Fig 7 shows each sawtooth wave starts from
different amplitude with 1200 phase shift. This sawtooth
wave amplitude is -2500 V, -800 V, and +900 V to +2500
V.

Figure 5: Sine Wave implementation

The Xilinx Block set is a powerful graphical

modeling tool which allows digital complex systems to be
designed using a block diagram methodology. The system
generator allows the modeling of digitized systems, which Figure 7: each saw tooth wave starts from different
can be transformed into ModelSim atmosphere and targeted amplitude
at a Xilinx FPGA board. Automatic generation of the bit
stream is supported with the synthesis and implementation The Very High speed integrated circuits Hardware
tools run within the ModelSim as well as Xilinx Description Language (VHDL) can be used to model a
environment. The design is verified and tested both in digital system at many levels of abstraction, ranging from
ISE/Xilinx –iMPACT and ModelSim. The system is the algorithmic level to gate level with high degree of
investigated by resistive and inductive (RL-load) loads. The complexity. Figure 8 shows the decimal value, bit
simulation results are investigated and the waveform of waveforms of ADC reference speed value, amplitude and
output voltage and load currents obtained contains fewer frequency. It also shows sinusoidal wave, 1800 phase shift
harmonic. The desired reference speed RMS value is sinusoidal wave (inverse sinusoidal) for reference signals,
converted to digital fixed point value for digital-design. The up-counter, 1200 phase shift up counter and 2400 phase
discrete reference value set the amplitude and the frequency shift up-counter for carrier sawtooth signals. The 12-
according to voltage and frequency ratio. The amplitude channel gate control signals are generated from the
and frequency with 14-bit ROM device are generated in comparison of two reference sinusoidal signals and three
two reference sinusoidal signals. These maintain the voltage carrier saw tooth-signals. The VHDL program generated
to frequency ratio constant by controlling the output voltage from the system is generated using Simulink platform. Fig.

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