DESIGN OF HAMMING CODE USING VERILOG

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Abstract - In mathematics, digital communication and applications that need error-control. The design includes both
information theory, error detection and correction has great of the encoder and decoder systems to be used for the serial
practical importance in maintaining information integrity data transmission and reception of the wireless transceiver
across noisy channels. Error coding is considered as a method systems. The design has been simulated and verified using
of detecting and correcting these errors to ensure that the ISim simulator and Verilog HDL. The design can also be seen
information is transferred intact from its source to its using Spartan-6 FPGA trainer kit for Xilinx 14.3 has been
destination. Error coding is a method of detecting and used for the implementation .
correcting these errors in a wide range of communication
systems in computer memory, magnetic and optical data
Keywords – ASIC, CPLD, Decoder, Encoder, Error

storage media, satellite and deep space communications, Coding, FPGA, Hamming Code, Verilog HDL

network communications, cellular telephone networks, and

almost any other form of digital data communication. Digital
data is transmitted over a channel and there is often noise in I. INTRODUCTION
the channel. The noise may distort the messages to be sent.
Therefore, what the receiver receives may not be the same as
what the sender sends. The goal of error coding is to improve A. Error correction
the reliability of digital communication by error detection and Data that is either transmitted over communication channel is
correction. There are various error correcting techniques to not completely error free. This change in the data is caused
detect and correct the error. One of the popular technique due to external interference, signal distortion, attenuation or
based on forward error correction is Hamming from noise. There are two types of errors. Firstly single error
Code.Hamming code is an error-correction code that can be in which only one bit is changed. And secondly the burst error
used to detect single and double-bit errors and correct single- in which more than one bits are changed. There are various
bit errors that can occur when binary data is transmitted from error detection and correction techniques such as Cyclic
one device into an-other. This paper presents design and Redundancy Checks (CRC), Parity check, LRC, VRC and
development of (11,7,1) Hamming code using verilog Hamming Code. This work focuses on Hamming code.
Hardware description language. Here "11" corresponds to the
total number of Hamming code bits in a transmittable unit B. Hamming Code
comprising data bits and redundancy bits, 7 is the number of A commonly known linear Block Code is the Hamming code.
data bits while‘1’ denotes the maximum number of error bits Hamming codes can detect and correct a single bit-error in a
in the transmittable unit. This code fits well into small field- block of data. In these codes, every bit is included in a unique
programmable gate arrays (FPGAs), complex programmable set of parity bits [2]. The presence and location of a single
logic devices (CPLDs) and application-specific integrated parity bit-error can be determined by analyzing parities of
circuits (ASICs) and is ideally suited to communication combinations of received bits to produce a table of parities
each of which corresponds to a particular bit-error errors.For example, a 7-bit ASCII code requires four
combination. This table of errors is known as the error redundancy bits that can be added at the end of the data unit or
syndrome. If all parities are correct according to this pattern, it interspersed with the original data bits to form the (11, 7, 1)
can be concluded that there is not a single bit-error in the Hamming code. In Fig. 1, these redundancy bits are placed in
message (there may be multiple bit-errors). If there are errors positions 1, 2, 4 and 8 (the positions in an 11-bit sequence that
in the parities caused by a single bit-error, the erroneous data are powers of ‘2’). For clarity in the examples below, these
bit can be found by adding up the positions of the erroneous bits are referred to as ‘r1,’ ‘r2,’ ‘r4’ and ‘r8.’In the Hamming
parities. Hamming codes are easy to implement and are used code, each ‘r’ bit is the parity bit for one combination of data
in Hamming codes are generally used in computing, bits as shown below:
telecommunication, and other applications including data
r1: bits 1, 3, 5, 7, 9, 11
compression, and turbo codes. They are also used for low cost
and low power applications. r2: bits 2, 3, 6, 7, 10, 11

II.IMPLEMENTATION OF HAMMING CODE r4: bits 4, 5, 6, 7

A. Designing (n, k, t) Hamming code r8: bits 8, 9, 10, 11

The (n, k, t) code refers to an ‘n’-bit code word having ‘k’
Each data bit may be included in more than one calculation. In
data bits (where n > k) and ‘r’ (=n–k) error-control bits called
the sequences above, for example, each of
‘redundant’ or ‘redundancy’ bits with the code having the
capability of correcting ‘t’ bits in the error (i.e., ‘t’ corrupted the original data bits is included in at least two sets, while the
bits). If the total number of bits in a transmittable unit (i.e., ‘r’ bits are included in only one set (see Fig. 2).
code word) is ‘n’ (=k+r), ‘r’ must be able to indicate at least
‘n+1’ (=k+r+1) different states. Of these, one state means no
error, and ‘n’ states indicate the location of an error in each of
the ‘n’ positions. So ‘n+1’ states must be discover-able by ‘r’
Fig. 1: Positions of redundancy bits in hamming code
bits; and ‘r’ bits can indicate 2r different states. Therefore, 2r
must be equal to or greater than ‘n+1’:

2r e” n +1

or

2r e” k + r +1

The value of ‘r’ can be determined by substituting the value

of ‘k’ (the original length of the data to be transmitted). For
example, if the value of ‘k’ is ‘7,’ the smallest ‘r’ value that
can satisfy this constraint is ‘4’:
Fig. 2: Redundancy bits calculation
2^4 e” 7+4+1
C. CALCULATION OF ‘r’ VALUES

B.The (11, 7, 1) Hamming code Fig. 3 shows the Hamming code implementation for an ASCII
The Hamming code can be applied to data units of any length. character. In the first step, each bit of the original character is
It uses the relationship between data and redundancy bits placed in its appropriate position in the 11-bit unit. In the
discussed above, and has the capability of correcting single-bit subsequent steps, the even parities for the various bit
combinations are calculated. The parity value for each
combination is the value of the corresponding ‘r’ bit.

Fig. 3: Example of redundancy bits calculation

D.ERROR DETECTION AND CORRECTION

Suppose that by the time the above transmission is received,

the seventh bit has changed from ‘1’ to ‘0.’ The receiver takes
the transmission and recalculates four new parity bits, using Fig. 4 Example of finding error bit
the same sets of bits used by the sender plus the relevant
parity ‘r’ bit for each set (Fig. 4). Then It assembles the new
parity values into a binary number in the descending order of II. Verilog HDL Program
‘r’ position (r8, r4, r2, r1). In the given example, this step
Verilog is a general-purpose hard ware d escrip tio n
gives us the binary number ‘0111’ (‘7’ decimal), which is the
language that is easy to learn and use. It is similar in syntax to
precise location of the corrupted bit. Once the bit is identified,
the ‘C ’ p ro grammi ng la n guage. Verilog allows different
the receiver can complement its value and correct the error.
levels of abstraction to be mixed in the same model. Thus
The beauty of the technique is that it can be easily
a designer can define a hardware model in terms of switches,
implemented in hardware and the code is corrected before the
gates, register transfer level (RTL) or algorithmic/ b e h a v i o u r a l
receiver knows about it. When the memory location is read,
c o d e . V e r il o g should not be confused with VHDL, which
again,the entire ECC(error correcting code) is read.. We
is yet another HDL whose first letter stands fo r ‘ver y hi gh-
recompute the values of the check bits from the data the ECC
sp eed inte grated circuit’ (VHSIC)
bits and compare them, using a bit wise exclusive OR, with
the check bits rad from memory. If the comparison result is The Hamming Encode is the (11, 7, 1) Hamming code encoder
0000, the recomputed check bits match the read check bits or that converts a 7-bit ASCII code into an 11-bit code word
redundancy bits, so all is well. However, if one of the stored and the Hamming_ Decode.v is the (11, 7, 1) Hamming code
ECC bits is flipped from the original, the comparison result is decoder that converts an 11-bit code word back into a 7 -
called the syndrome, will be other than 0000. It turns out to be bitASCII code after correcting the single bit error, if any.
binary index of the ECC bit that has flipped. Thus, we can use Both these programs have been developed in Verilog HDL
the syndrome value to correct the error by flipping the indexed and simulated using Xlinx ISE 14.3. The simulated outputs of
value. the encoder and the decoder are shown in Figs 5 and 6,
respectively.
 III. RESULT: Decoder

A. SIMULATION RESULTS:

Encoder

Decoder

C.IMPLEMENT DESIGN:
B.RTL SCHEMATIC:

Encoder
 The authors thank thier authorities of Dayananda Sagar
College Of Engineering,Bangalore, Karnataka, India for
encouraging us for this research work and project work.

REFERENCES
1. Leena, Mr. Subham Gandhi and Mr. Jitender Khurana,
“Implementing (7,4) Hamming Code using CPLD on VHDL”
International Journal of New Trends in Electronics , Vol. 1,
Issue 1, Aug. 2013.

2.Xilinx “Synthesis and Simulation Design Guide”, Xilinx

Tech UG626 2012.

3.Digital design, An embedded systems approach using

Verilog, Peter J. Ashenden, ISBN:978-81-909-563-0

4.Nuh Aydin: An Introduction to Coding Theory via

Hamming Codes. Department of Mathematics Kenyon
College.

5.Ming- Bo Lin “ Digital System Design and Practices using

Verilog HDL and FPGA”, Wiley-India , ISBN:978-81-265-
3694-8 .

TOTAL WORD COUNT(STATISTICS)

Pages 5
IV. CONCLUSION
The hamming code for the given bit sequence is written and Words 1916

the wave form is observed , the input sequence is of 4 bit, 2 r

Characters(no space) 9032
>= k+r+1 => r = 4, (11,7,1) therefore redundant bits are 4
er1,r2,r3,r4 , hamming code sequence is of 11 in length. In the Characters(with space) 10894
7th bit error has occurred, Once the bit is identified, we can
complement its value and correct the error. The encoder and Paragraphs 78

decoder Verilog code are written , in Xilinx we got the

Non-Asian words 1825
required o/p and the decoded bit sequence is matching.The
Hamming encoding and decoding both are verified for Asian Characters 91
different data input in the format (11,7,1) in both simulation
and implementation in FPGA.

VI.ACKNOWLEDGMENT