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Memory Reference Instructions Execution

This document summarizes memory reference instructions and their execution in a computer's instruction cycle. It discusses: 1) The format of computer instructions, which have 16 bits made up of an opcode and address. Memory reference instructions are identified by the opcode and use direct or indirect addressing. 2) The phases of an instruction cycle, which fetches and decodes instructions before reading the effective address and executing the instruction. 3) How different memory reference instructions like AND, ADD, LDA, STA, BUN, BSA, and ISZ are executed over multiple clock cycles using control signals from a control unit. The control unit sequences through the clock signals to perform the required micro-operations.

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Aditya Singh
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138 views13 pages

Memory Reference Instructions Execution

This document summarizes memory reference instructions and their execution in a computer's instruction cycle. It discusses: 1) The format of computer instructions, which have 16 bits made up of an opcode and address. Memory reference instructions are identified by the opcode and use direct or indirect addressing. 2) The phases of an instruction cycle, which fetches and decodes instructions before reading the effective address and executing the instruction. 3) How different memory reference instructions like AND, ADD, LDA, STA, BUN, BSA, and ISZ are executed over multiple clock cycles using control signals from a control unit. The control unit sequences through the clock signals to perform the required micro-operations.

Uploaded by

Aditya Singh
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
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MEMORY

REFERENCE
INSTRUCTION
EXECUTION
by NIKITA SINGLA
SID- 18103066
Stored Program
Organisation
Organise a computer
 One processor
 An instruction code :
1. operation/ opcode
2. address

4 bits
(opcode)

16-bit
memory
12 bits
(address)
Computer Instructions
 Each format has 16 bits
 Total number of instructions
for basic computer=25
 Memory reference instruction:
if I=0 -> direct address
if I=1 -> indirect address
 Register reference instruction:
recognised by operation
code 0111
 Input-output reference
instruction:
recognised by operation
code 1111
MEMORY
REFERENCE

REGISTER
REFERENCE

INPUT/OUTPUT
REFERENCE
Control unit and
time signals
Control unit consists :
 2 decoders
 A sequence counter
 Control logic gates
Time Signals:
 Outputs of SC ->16 time
signals
 SC can be:
- incremented
- cleared
If SC is not cleared time
signals will continue….
.

Figure: Control circuit for instruction fetch. This is a part of the control
circuit and demonstrates the kind of wiring needed
INSTRUCTION CYCLE
(Fetch and
Decode)
Phases in instruction cycle:
1) Fetch an instruction
2) Decode it
3) Read effective address
4) Execute the instruction

T0: AR <- PC

T1: IR <- M[AR] , PC <-PC+1

T2: D0,……,D7 <- Decode IR(12-


14), AR <- IR(0-11), I <-IR(15)
Memory-Reference Instructions
 Effectiveaddress is in AR and is placed
during: T2 when I=0, or T3 when I=1
 Execution of MRI starts from T4
 Execution requires -> micro operations
 AND to AC:
- performs AND logic operation • DR <- M[AR]
D0T4
- uses operation decoder D0
- two time signals needed D0T5 • AC <- AC^DR, SC <- 0

 ADD to AC:
- performs sum
D1T4 • DR <- M[AR]
- uses operation decoder D1
- two time signals needed D1T5 • AC <- AC+DR , E <- Cout , SC <- 0

 LDA: Load to AC:


- transfers memory word to AC
- uses operation decoder D2 D2T4 • DR <- M[AR]
- two time signals needed D2T5 • AC <- DR, SC <- 0
 STA: Store AC:
- stores content of AC into
memory • M[AR] <- AC, SC <- 0
D3T4
- uses operation decoder D3
- one time signals needed
 BUN: Branch Unconditionally:
- specifies an instruction out of sequence
- uses operation decoder D4 D4T4 • PC<- AR, SC <- 0
- one time signals needed

 BSA: Branch and Save Return Address:


- branches to a portion called a
subroutine or procedure
- return to original program is
accomplished by indirect BUN
- return address is stored in :
D5T4 • M[AR] <- PC, AR <- AR+1
processor register or stack
- uses operation decoder D5 D5T5 • PC <- AR, SC <- 0

- two time signals needed


 ISZ : Increment and Skip if Zero
- increments the word specified by
effective address : •DR<-M[AR]
D6T4
if result=0,PC is incremented by 1
(in order to skip an instruction) D6T5
•DR <- DR+1

- uses operation decoder D6 •M[AR] <- DR, if (DR=0) then (PC<-PC+1),


D6T6 SC<-0
- three time signals needed
THANK YOU
- NIKITA SINGLA
SID : 18103066

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