Where & how 8259 PIC can be used to handle interrupts.

THE 8259A PROGRAMMABLE INTERRUPT CONTROLLER

The 8259A programmable interrupt controller designed to work with Intel microprocessors 8085, 8086 and 8088.
The 8259A interrupt controller can

1. Manage eight interrupts according to the instructions written into its control registers. This is equivalent to
proving eight interrupt pins on the processor in place of one INTR (8085) pin.

2. Vector can interrupt request anywhere in the memory map. However, all eight interrupts are spaced at the
interval of either four or eight locations. This eliminates all the major drawback of the 8085 interrupts in which
all interrupts are vectored to memory locations on page 00H

3. Resolve eight levels of interrupt priorities in a variety of modes, such as fully nested mode, automatic
rotation mode, and specific rotation mode.

4. Mask each interrupt request individually.

5. Read the status of pending interrupts, in-service interrupts, and masked interrupts.

6. Be set up to accept either the level-triggered or the edge-triggered interrupt request

7. Be expanded to 64 priority levels by cascading additional 8259As.

8. Be set up to work with either the 8085 microprocessor mode or the 886/8088 microprocessor mode.

The 8259A is upward-compatible with its predecessor, the 8259. The main difference between the two is that
the 8259A can be used with Intel's 8086/88 16-bit microprocessor. It also includes additional features such as the
level-triggered mode, buffered mode, and automatic-end-of interrupt mode. To simplify the explanation of the
8259A, illustrative examples will not include the cascade mode or the 8086/88 mode and will be limited to modes
continuously used with the 8085.

 Explain the operation of 8259 PIC with the help of its block diagram.
 Explain different types of interrupts in brief.

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DATA BUS BUFFER:- If the data format is not matched it temporarily holds the data. For eg: Printer can accept
only 1 bit data but at a time more than 1 bit data may be sent. In such case data bus buffer stores the bits
that printer cannot accept at the moment.

READ/WRITE LOGIC :- This is a typical Read/Write control logic. When the address line A0 is at logic 0, the
controller is selected to write a command or read a status. The Chip Select logic and A0 determine the port
address of the controller.

CONTROL LOGIC :- This block has two pints: INT (Interrupt) as an output, and INT (Interrupt Acknowledge) as an
input. The INT is connected to the interrupt pin of the MPU. Whenever a valid interrupt is asserted, this signal
goes high.

INTERRUPT REGISTERS AND PRIORITY RESOLVER:- The interrupt Request Register (IRR) has eight input lines (IR0-
IR7) for the interrupts. When these lines go high, the requests are stored in the register. The In-Service Register
(ISR) stores all the levels that are currently being serviced, and the Interrupt Mask Register (IMR) stored the
masking bits of the interrupt lines to be masked. The Priority Resolver (PR) examines these three registers and
determines whether INT should be sent to the MPU.

CASCADE BUFFER/COMPARATOR :-This block is used to expand the number of interrupt levels by cascading two or
more 8259As.

Priority Modes and Other Features :- Many types of priority modes are available under software control in the
8259A, and they can be changed dynamically during the program by writing appropriate command words.
Commonly used priority modes are discussed below:

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 1. Fully Nested Mode: This is a general-purpose mode in which all IRS (interrupt Requests) are arranged from
highest to lowest, with IR0 as the highest and IR7 as the lowest.
2. Automatic Rotation Mode: In this mode, a device, after being serviced, receives the lowest priority.
Assuming that the IR2 has just been serviced, it will receive the seventh priority, as shown below:
IR0 IR1 IR2 IR3 IR4 IR2 IR3 IR4
1 6 7 0 1 2 3 4

3. Specific Rotation Mode: This mode is similar to the automatic rotation mode, except that the user can
select any IR for the lowest priority, Thus fixing all other priorities.

8259 PROGRAMMABLE INTERRUPT CONTROLLER

It is used when several I/O devices transfer data using interrupt & they are connected to some interrupt
line of Microprocessor. INTEL 8259 is a single chip programmable interrupt controller. It is compatible with
8085, 8086 & 8088 Microprocessors. It is a 28 pin IC which uses NMOS technology. It requires 5v supply to
operate. Architecture of INTEL 8259.

The detailed pin description of INTEL 8259 is given below.

CS (Chip select): A LOW signal on this pin indicates that chip has been selected.
WR (Write): If WR signal is LOW then INTEL 8259 will be enable to accept command word from CPU.
RD (Read): A LOW signal on this pin enable a 8259 to send status signal on data bus to CPU.
D7-D0 (Data lines): It is bidirectional data bus. Control, status & interrupt vector information are
transferred via this bus.
CAS0-CAS2: These are cascaded lines, which are used when more than one 8259 IC are to be connected.
SP/EN (Slave Program/Enable): It is related to cascade control. It is used to differentiate between master
and slave controller.
INT (Interrupt): this signal is used to interrupt CPU.
INTA (Interrupt Acknowledgement): Microprocessor acknowledges the requested interrupt through this pin.
IR0-IR7 (Interrupt Request): I/O devices send interrupt request through these lines.

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A0 (Address Line): It is in conjunction with RD, WR & CS. INTEL 8259 uses it to interrupt command words
the CPU writes & the status which CPU wants to read.
OPERATION OF 8259:- Eight I/O devices can be connected to 8259 through IR0-IR7 lines. One or more I/O
devices can send interrupt request at the same time to the interrupt controller. Depending upon the
priority of interrupt the request of I/O device which has highest priority is sent to the Microprocessor on
INT line. In return Microprocessor sends an acknowledgement signal via INTA line. On receipt of INTA
signal all the interrupts of lower priority are discarded. And the address of the interrupt service subroutine
(ISS) for the concerned I/O device is sent by 8259. If there are more than eight devices to transfer data
using interrupt then two 8259 chips can be connected in series, such connection is known as cascading.
The 8259 IC which is connected to the processor is known as Master & the IC which is connected to the
master is known as Slave.

Maskable and non-maskable interrupts

Maskable interrupt Non Maskable interrupt

Hardware interrupt that may be ignored by setting a Hardware interrupt that Lacks an associated bit-
bit in an interrupt mask register’s (IMR) Bit- mask mask, so that it can never be ignored.

Can be disabled or ignored by the CPU Cannot be disabled or ignored by the CPU.

May be vectored or non –vectored. All are vectored.

When a maskable interrupt occurs, it can be handled When non maskable interrupts occurs, the current
After the execution of the current instruction. instructions and status is stored in stack for the CPU
to handle the interrupt.

Used to interface with peripherals devices & for low Used for the emergency purpose. For eg. Power
priority tasks. failure, smoke detector etc & for higher priority
tasks such as watchdog timers

RST 6.5, RST 7.5, RST 5.5 of 8085 microprocessor are Trap of 8085 microprocessor is an example for non-
some maskable interrupts maskable interrupts.

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