Embedded Systems Laboratory [EE - 481]

Submitted by

Group-3

1. Ette Sampath Reddy(116EE0336)

2. Boda Ramu(116EE0334)
3. Bandi Nishitha Reddy(116EE0335)
4. Amresh (716EE4099)

Under the guidance of

Dr. Supratim Gupta

Department of Electrical Engineering

National Institute of Technology, Rourkela.

 Contents Table:

Sl. No Experiment Name Date Remarks Signature

ADC and DAC interfacing with
1 08-08-2019
8051-MC
2 FIR low pass filter of 2nd order 12-09-2019
3 IIR low pass filter of 5th order 24-10-2019
 ADC-0808 and DAC-0808 Interfacing With
8051 Microcontroller

Objective:
Develop a RTOS to measure the input and output (after DAC) amplitude and frequency, tabulate
20 readings and find the simulation of the system.
Software used:
• Proteus 8 Professional
• Keil uVision

Theory:

The 8051 Microcontroller is one of the most popular and most commonly used microcontrollers
in various fields like embedded systems, consumer electronics, automobiles, etc. A
Microcontroller is a VLSI IC that contains a CPU (Processor) along with some other peripherals
like Memory (RAM and ROM), I/O Ports, Timers/Counters, Communication Interface, ADC, etc.
The clock (crystal) of the microcontroller circuit is set to 11.059 MHz The power on reset circuit
should be used in the microcontroller circuit to damp out the transients during switching on the
supply

OPAMP (741) stands for operational amplifier it is used as an amplifier as well as to perform
operations (arithmetic operations like addition, subtraction, logarithm, exponential etc), in our
project we are using it with DAC which has current as default output, OPAMP is used to convert
that as voltage.

ADC is the Analog to Digital converter, which converts analog data into digital format; usually it
is used to convert analog voltage into digital format. Analog signal has infinite no of values like a
sine wave or our speech, ADC converts them into particular levels or states, which can be measured
in numbers as a physical quantity. Instead of continuous conversion, ADC converts data
periodically, which is usually known as sampling rate. Telephone modem is one of the examples
of ADC, which is used for internet; it converts analog data into digital data, so that computer can
understand, because computer can only understand Digital data. The major advantage, of using
ADC is that, noise can be efficiently eliminated from the original signal and digital signal can
travel more efficiently than analog one. That’s the reason that digital audio is very clear, while
listening. And now if we want the same analog signal at the output which was given as input to
the ADC we can use DAC which will convert the digital data to analog signal
Circuit:

Fig 1. Circuit Diagram

Procedure:
1. Connections were made as per the circuit diagram.
2. Keep the offset voltage for the ADC signal as 2.5V.
3. By varying the frequency of the signal keeping input voltage constant output voltage and
the output frequency were measured.
4. Similarly keeping the input frequency constant input voltage was changed and the output
voltage and output frequency were measured.

Code:

OBJECTIVE OF THE CODE: ADC AND DAC INTERFACING WITH THE 8051
AUTHORS: ETTE SAMPATH REDDY (116EE0336)
BODA RAMU (116EE0334)
BANDI NISHITHA REDDY (116EE0334)
AMRESH (716EE4099)
DATE OF CREATION: 08/08/2019

ALE EQU P3.0 ;ALE PIN CONNECTED TO P3.0

START EQU P3.1 ;START PIN CONNECTED TO P3.1
EOC EQU P3.2 ;EOC PIN CONNECTED TO P3.2

ORG 0000H ;SET START ADDRESS TO 0000H

SJMP MAIN ;JUMP TO MAIN
ORG 0003H ;EXTERNAL INTERRUPT 0 VECTOR
ADDRESS
SJMP ISR ;JUMP TP ISR

MAIN:
MOV P1,#0FFH ;SET PORT 1 AS I/P PORT
MOV P2,#00H ;SET PORT 2 AS O/P PORT
MOV IE,#81H ;ENABLE EXTERNAL INTERRUPT 0
CLR PSW.3
CLR PSW.4 ;SELECT REGISTER BANK 0
SETB ALE
SETB START
CLR ALE
CLR START
LOOP: SJMP LOOP

ISR: PUSH ACC

PUSH PSW
MOV A,P1 ; Output of ADC gets stored in
accumulator
MOV P2,A ; Contents of Accumulator move
to Port2 to which DAC is connected
; For another conversion
SETB ALE
SETB START
CLR ALE
CLR START
POP PSW
POP ACC
RETI ;Returns from ISR
END
Observations:

Table No 1: The Input ADC signal Voltage and Frequency vs Output DAC Voltage and
Frequency

Input Data Output Data

Sl.No Remarks
Amplitude(V) Frequency (Hz) Amplitude(V) Frequency (Hz)

1 2.5 50 2.5 51.51 No distortion

2 0.5 50 0.5 51.81 No distortion

3 1.0 50 0.975 50 No distortion

4 1.5 50 1.5 50 No distortion

5 2 50 2.0 49.50 No distortion

6 3 50 5.0 47.17 Distortion

7 2.5 10 2.5 10 No distortion

8 2.5 30 2.5 30.30 No distortion

9 2.5 80 2.5 81.96 No distortion

10 2.5 100 2.245 96.15 No distortion

11 2.5 200 2.245 206.96 No distortion

12 2.5 60 2.5 60.62 No distortion

13 2.2 60 2.225 60.3 No distortion

14 1.0 60 0.99 60.15 No distortion

15 2.5 40 2.5 40.36 No distortion

16 1.0 40 0.96 40.54 No distortion

17 2.2 40 4.36 39.8 No distortion

18 0.5 40 1.05 40.4 No distortion

19 9.0 50 5.0 48.62 Distortion

20 9.0 100 5.0 98.22 Distortion

Results:
Offset Voltage=2.5V

Fig 2. The output at 50Hz and 2.5V Amplitude (Input in Blue and Output in yellow)

Fig 3. The output at 50Hz and 3V Amplitude (Input in Blue and Output in yellow)

Conclusion: From the given experiment, a sinusoidal input was taken from the source to ADC
where it was converted into digital signal and then fed to a DAC which further converts back it
into analogue signal.

From the observation table, for low amplitude values of input signal the output from the DAC is
approximately same as the input amplitude value irrespective of frequency but for higher values
of input signal sine wave was getting clipped off and we are getting much error in amplitude
 Design of Low Pass Filter with FIR Design of 2nd Order

Objective:
Develop RTOS–with FIFO structure for signal access–to realize the filters in the circuit
developed in Task-1

Software used:
➢ Proteus 8 Professional
➢ Keil uVision
➢ MATLAB R2018a

Theory:

In signal processing, a finite impulse response (FIR) filter is a filter whose impulse response (or
response to any finite length input) is of finite duration, and it settles to zero in finite time. This
is contrary to an infinite impulse response (IIR) filter, which may have an internal feedback and
may continue responding by decaying indefinitely.

The impulse response (I) of an Nth-order discrete-time FIR filter exists for exactly N + 1 samples
before it then settles to zero (from first nonzero element through last nonzero element) . FIR
filters can be discrete in time or continuous in time and maybe digital based or analog based. An
FIR filter is designed by finding the coefficients and filter order that meet required
specifications, which can be in the time domain) or the frequency domain. Matched filters
perform a correlation between the input signal and a known pulse shape. The FIR convolution is
a correlation between the input signal and a time-inverted copy of the impulse response.
Therefore, the matched filter's impulse response is "modelled" by sampling the known pulse-
shape and using those samples in reverse order as the coefficients of the filter.

Kaiser is a one-parameter family of window functions used in finite impulse response filter
design and spectral analysis. The Kaiser window approximates the DPSS window which
maximizes the energy concentration in the main lobe but which is difficult to compute.
This is a huge advantage over other windows, where the window length, ripple size and
transition bandwidth have a three-way trade off. The only disadvantage with the Kaiser window
is that we design for the same ripple size in both passband and stopband.

Circuit:

Fig 4. Circuit Diagram

Procedure:
1. Initially the filter coefficients were calculated using the MATLAB filter designer toolbox.
2. The cut-off frequency is 334Hz and the sampling frequency must be greater than the
twice of the cut-off frequency sampling frequency=800Hz

The circuit is the same as the one designed in Task 1. The code has been altered to implement the
Low-pass FIR filter.

The coefficients are in the range of 0-1 so they are converted 0.8 notation of fixed precision point
and the samples are already in 0.8 notation, so the output which is:

Y[n] = a0*x[n] + a1*x [n-1] + a2*x [n-2] …. (1)

Is in the form of 0.8*0.8 = 0.16, lower 8 bits are ignored, hence we are left with 0.8 output which
is sent to the DAC.

Filter Parameters

Type: Low pass window, FIR

Cut-off frequency = 334 Hz (lowest roll no. of group)

Sampling frequency = 800 Hz

Filter coefficients: 0.13105,0.73789,0.13105

Code:

OBJECTIVE OF THE CODE: Design of FIR Low Pass Filter with of 2nd
Order

AUTHORS: ETTE SAMPATH REDDY (116EE0336)

BODA RAMU (116EE0334)
BANDI NISHITHA REDDY (116EE0334)
AMRESH (716EE4099)
DATE OF CREATION: 12/09/2019

ORG 0000H;
SJMP MAIN
ORG 0003H;
SJMP SAMPLE
MAIN:
MOV P1,#0FFH; SET THE PORT 1 AS THE INPUT PORT
MOV P2,#00H; SET THE PORT 2 AS THE OUTPUT PORT
MOV IE,#81H; ENABLE THE INTERRUPT ENABLE FOR THE EXTERNAL
INTERRUPT !
SETB TCON.0; KEEP THE TRIGGER MODE AS EDGE TRIGGERED
MOV R0,#00H;
MOV R1,#00H;
MOV R2,#00H;
MOV R3,#22H; ASSIGN THE FILTER COEFFICIENT VALUE TO A
REGISTER
MOV R4,#0BDH; ASSIGN THE FILTER COEFFICIENT VALUE TO A
REGISTER
SETB P3.0; SET THE ALE PORT OF ADC
SETB P3.1; SET THE START OF THE ADC FOR THE START OF THE
CONVERSION
CLR P3.0; AFTER THE SET, CLEAR THE ALE
CLR P3.1; AFTER THE SET, CLEAR THE START
LOOP: SJMP LOOP; END OF THE MAIN PROGRAM

SAMPLE:
MOV R0,P1; MOVE THE VALUES FROM THE ADC TO THE R0 REGISTER
MOV A,R0; MOVE THE CONTENTS OF THE REGISTER THE
ACCUMULATOR
MOV B,R3; MOVE CORRESPONDING COEFFICIENT OF THE FILTER
DESIGN TO THE REGISTER B
MUL AB; MULTIPLY THE SAMPLED VALUE WITH THE FILTER
COEFFICIENT
MOV R5,B; MOVE THE PRODUCT INTO THE OTHER REGISTER
MOV A,R1; MOVE THE 1ST PREVIOUS SAMPLE VALUE INTO THE
ACCUMULATOR
MOV B,R4; MOVE CORRESPONDING COEFFICIENT OF THE FILTER
DESIGN TO THE REGISTER B
MUL AB; MULTIPLY THE SAMPLED VALUE WITH THE FILTER
COEFFICIENT
MOV R6,B; MOVE THE PRODUCT INTO THE OTHER REGISTER
MOV A,R2; MOVE THE 2ND PREVIOUS SAMPLE VALUE INTO THE
ACCUMULATOR
MOV B,R3; MOVE CORRESPONDING COEFFICIENT OF THE FILTER
DESIGN TO THE REGISTER B
MUL AB; MULTIPLY THE SAMPLED VALUE WITH THE FILTER
COEFFICIENT
MOV R7,B; MOVE THE PRODUCT INTO THE OTHER REGISTER
MOV A,R5;
ADD A,R6; ADD ALL THE THREE MULTIPIED RESULTS
ADD A,R7;
MOV P2,A; MOVE THE CONTENTS IN TO THE DAC
MOV A,R1; TRANSFER THE PREVIOUS SAMPLE VALUE INTO THE
REGISTER R2
MOV R2,A;
MOV A,R0; TRANSFER THE PRESENT SAMPLE VALUE INTO THE
REGISTER R1
MOV R1,A;

SETB P3.0;
SETB P3.1;
CLR P3.0;
CLR P3.1;
RETI
END
Observations:

Table No 2: The Input ADC signal Voltage vs Output DAC Voltage and latency.

Frequency Input Amplitude Output Amplitude Gain in

Latency (ms) Gain
(Hz) (Vp-p) (Vp-p) dB
50 5 5 0.5 1 0
100 5 5 0.6 1 0
200 5 5 0.4 1 0
300 5 4.95 0.325 0.99 -0.1754
334 5 4.85 0.350 0.97 -0.264
500 5 4.85 0.350 0.97 -0.264
800 5 4.65 0.3 0.93 -0.630
2000 5 2.20 0.350 0.56 -5.036
5000 5 2.76 0.220 0.552 -5.16
10000 5 1.6 - 0.32 -9.89

Results:
Input offset voltage=2.5V

Fig 5. The output at 50Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
Fig 6. The output at 200Hz and 2.5V Amplitude (Input in Blue and Output in yellow)

Fig 7. The output at 334Hz and 2.5V Amplitude (Input in Blue and Output in yellow)

Fig 8. The output at 1000Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
Conclusion: The coefficients of the FIR filter were obtained from FDAtool of MATLAB. Those
coefficients were converted to 0.8 form of fixed point precision. Then using the value of samples
and coefficients the output was calculated and given to DAC. For varying frequency, it was
observed that the amplitude of the output decreased and distortion increased with increasing
input frequency beyond cut-off frequency (334 Hz). As it is a low pass filter the reduction in
output amplitude is justified and the output frequency response is also similar to that of response
obtained in FDAtool. From graphs we observed that as the frequency reached half of the
sampling frequency (800Hz), the distortion increased very rapidly thus satisfying Nyquist
theorem (fs >2*fm) even if fs is just greater than 2*fm there will be lot of distortion which is
observed here
 Implementation of Higher-Order IIR Filter using
8051 Microcontroller

Objective:
Develop RTOS–with FIFO structure for signal access–to realize the filters in the circuit developed
in Task-1-2

Software used:
➢ Proteus 8 Professional
➢ Keil uVision
➢ MATLAB R2018a

Theory:

The most commonly used IIR filter design method uses reference analog prototype filter. It is the
best method to use when designing standard filters such as low-pass, high-pass, bandpass and
band-stop filters it is important class of linear time-invariant discrete-time systems characterized
by the general linear constant-coefficient difference equation.

𝑁 𝑁

𝑦[𝑛] = − ∑ 𝑎𝑘 𝑦(𝑛 − 𝑘) + ∑ 𝑏𝑘 𝑥(𝑛 − 𝑘)

𝑘=1 𝑘=1

By means of Z transform it is characterized by the rational system function,

∑𝑀 𝑏𝑘 𝑧 −𝑘
H(z)=1+∑𝑘=1
𝑁 −𝑘
𝑘=1 𝑎𝑘 𝑧

The filter design process starts with specifications and requirements of the desirable IIR filter. A
type of reference analog prototype filter to be used is specified according to the specifications
and after that everything is ready for analog prototype filter design.

The next step in the design process is scaling of the frequency range of analog prototype filter
into desirable frequency range. This is how an analog prototype filter is converted into an analog
filter.
After the analog filter is designed, it is time to go through the last step in the digital IIR filter
design process. It is conversion from analog to digital filter. The most popular and most
commonly used converting method is bilinear transformation method. The resulting filter,
obtained in this way, is always stable. However, instability of the resulting filter, when bilinear
transformation is used, may be caused only by the finite word-length side-effect.

Circuit:

Fig 9. Circuit Diagram.

Procedure:
1. Initially the filter coefficients were calculated using the MATLAB filter designer toolbox.
2. The cut-off frequency is 334Hz and the sampling frequency must be greater than the
twice of the cut-off frequency sampling frequency=2100Hz

The circuit is the same as the one designed in Task 1. The code has been altered to implement the
Low-pass FIR filter.
The coefficients are in the range of 0-1 so they are converted 0.8 notation of fixed precision point
and the samples are already in 0.8 notation, so the output which is:

𝑁 𝑁

𝑦[𝑛] = − ∑ 𝑎𝑘 𝑦(𝑛 − 𝑘) + ∑ 𝑏𝑘 𝑥(𝑛 − 𝑘)

𝑘=1 𝑘=1

Is in the form of 0.8*0.8 = 0.16, lower 8 bits are ignored, hence we are left with 0.8 output which
is sent to the DAC
Code:
OBJECTIVE OF THE CODE: Design of IIR Low Pass Filter with of 5th
Order

AUTHORS: ETTE SAMPATH REDDY (116EE0336)

BODA RAMU (116EE0334)
BANDI NISHITHA REDDY (116EE0334)
AMRESH (716EE4099)
DATE OF CREATION: 24/10/2019

;DEFINE ADC PINS CONNECTED TO THE PINS OF MICROCONTROLLER

ALE EQU P3.0 ;ALE PIN CONNECTED TO P3.0
START EQU P3.1 ;START PIN CONNECTED TO P3.1
EOC EQU P3.2 ;EOC PIN CONNECTED TO P3.2

ORG 0000H ;SET START ADDRESS TO 0000H

SJMP MAIN ;JUMP TO MAIN
ORG 0003H ;EXTERNAL INTERRUPT 0 VECTOR ADDRESS
SJMP ISR_EX ;JUMP TP ISR_EX

MAIN:
MOV P1,#0FFH ;SET PORT 1 AS I/P PORT
MOV P2,#00H ;SET PORT 2 AS O/P PORT
MOV IE,#81H ;ENABLE EXTERNAL INTERRUPT 0
CLR PSW.3
CLR PSW.4 ;SELECT REGISTER BANK 0
SETB ALE
SETB START
CLR ALE
CLR START

LOOP: SJMP LOOP

ISR_EX:
;SECTION 1 (FIRST II ORDER FILTER)
 CLR PSW.3
CLR PSW.4 ;SELECT REGISTER BANK 0
MOV R0,P1 ;MOVE CONVERTED DATA FROM ADC TO R0
MOV A,#32H ;a0 MOVED TO ACCUMULATOR
MOV B,R0 ;x[n] SAMPLE FROM R0 MOVED TO B
MUL AB ;a0*x[n]
MOV R6,B ;ABOVE MULTIPICATION RESULT MOVED TO
R6
MOV A,#64H ;a1 MOVED TO ACCUMULATOR
MOV B,R1 ;x[n-1] SAMPLE FROM R1 MOVED TO B
MUL AB ;a1*x[n-1]
MOV R7,B ;ABOVE MULTIPICATION RESULT MOVED TO
R6
MOV A,#32H ;a2 MOVED TO ACCUMULATOR
MOV B,R2 ;x[n-2] SAMPLE FROM R2 MOVED TO B
MUL AB ;a2*x[n-2]
MOV A,B ;ABOVE MULTIPICATION RESULT MOVED TO
ACCUMULATOR
ADDC A,R6 ;a2*x[n-2]+a0*x[n]
ADDC A,R7 ;a0*x[n]+a1*x[n-1]+a2*x[n-2]
MOV R3,A ;ABOVE SUM FROM ACCUMULATOR MOVED TO
R3

MOV A,R1
MOV R2,A ;TRANSFER x[n-1] SAMPLE TO R2
MOV A,R0
MOV R1,A ;TRANSFER x[n] SAMPLE TO R1

MOV A,#94H ;b1 MOVED TO ACCUMULATOR

MOV B,R4 ;y[n-1] SAMPLE FROM R0 MOVED TO B
MUL AB ;b1*y[n-1]
MOV A,B ;ABOVE MULTIPICATION RESULT MOVED TO
ACCUMULATOR
ADDC A,R3 ;a0*x[n]+a1*x[n-1]+a2*x[n-2]-b1*y[n-
1]
MOV R6,A ;ABOVE SUM MOVED TO R6
MOV A,#6CH ;b2 MOVED TO ACCUMULATOR
MOV B,R5 ;y[n-2] SAMPLE FROM R0 MOVED TO B
MUL AB ;b2*y[n-2]
MOV R7,B ;ABOVE MULTIPICATION RESULT MOVED TO
R7
MOV A,R6 ;a0*x[n]+a1*x[n-1]+a2*x[n-2]-b1*y[n-
1] SUM MOVED TO ACCUMULATOR
; CLR PSW.0
SUBB A,R7 ;a0*x[n]+a1*x[n-1]+a2*x[n-2]-b1*y[n-
1]-b2*y[n-2]
 MOV R6,A ;ABOVE SUM MOVED FROM ACCUMULATOR TO
R6

MOV A,R4
MOV R5,A ;TRANSFER y[n-1] SAMPLE TO R5
MOV A,R6
MOV R4,A ;TRANSFER y[n] SAMPLE TO R4

;SECTION 2 (SECOND II ORDER FILTER)

CLR PSW.3
SETB PSW.4 ;CHANGE THE REGISTER BANK TO BANK 2
FOR SECTION 2

MOV R0,A
MOV A,#25H
MOV B,R0
MUL AB
MOV R6,B
MOV A,#50H
MOV B,R1
MUL AB
MOV R7,B
MOV A,#25H
MOV B,R2
MUL AB
MOV A,B
ADDC A,R6
ADDC A,R7
MOV R3,A

MOV A,R1
MOV R2,A
MOV A,R0
MOV R1,A

MOV A,#97H
MOV B,R4
MUL AB
MOV A,B
ADDC A,R3
MOV R6,A
MOV A,#2DH
MOV B,R5
MUL AB
MOV R7,B
MOV A,R6
; CLR PSW.0
 SUBB A,R7
MOV R6,A

MOV A,R4
MOV R5,A
MOV A,R6
MOV R4,A

;SECTION 3 (I ORDER FILTER)

SETB PSW.3
SETB PSW.4 ;CHANGE THE REGISTER BANK TO BANK 3
FOR SECTION 3

MOV R0,A
MOV A,#5DH
MOV B,R0
MUL AB
MOV R6,B
MOV A,#5DH
MOV B,R1
MUL AB
MOV A,B
ADDC A,R6
MOV R3,A

MOV A,R0
MOV R1,A

MOV A,#45H
MOV B,R4
MUL AB
MOV A,B
ADDC A,R3
MOV R6,A

MOV A,R6
MOV R4,A

MOV P2,A ;OUTPUT y[n] OF 5TH ORDER FILTER

MOVED TO P2

SETB ALE
SETB START
CLR ALE
CLR START
RETI
END
Observations:
Table-3: Table showing the Output Amplitudes of IIR filter for various Input frequencies.
Frequency Input Amplitude Output Amplitude Gain in
Latency (ms) Gain
(Hz) (V) (V) dB
50 4 3.8 1.3 0.95 -0.44
100 4 3.8 1.15 0.95 -0.44
200 4 3.7 1.3 0.925 -0.625
300 4 2.4 1.2 0.6 -4.436
334 4 2.275 1.2 0.568 -4.91
500 4 0.975 2.05 0.2375 -12.48
800 4 0.720 - 0.180 -14.89
1000 4 0.185 - 0.046 -26.744

Results:

Fig 10. The output at 50Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
Fig 11. The output at 200Hz and 2.5V Amplitude (Input in Blue and Output in yellow)

Fig 12. The output at 500Hz and 2.5V Amplitude (Input in Blue and Output in yellow)

Fig 13. The output at 1000Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
Problems Faced
1. Due to the higher number of coefficients and past values of input and output that had to
be stored, a single register bank was not enough. We had to use a second bank as well.
This led to increased complexity of the code.
2. Distortions were higher as compared to the FIR filter, causing problems while taking
readings. There were especially large distortions at f = 200 Hz. Even at the other
frequencies, the distorted sinusoids were interspersed by flat lines in between.
3. Selection of Fs.
4. They are harder to implement using fixed-point arithmetic.
5. Clock frequency of ADC0808 should not be less like 2KHz,instead it should be like
640kHz or 1MHz.

Conclusion:
Output filtered signal was similar to the input signal for low frequency signals and for higher
frequency signals output amplitude is attenuated according to the frequency response.