Scribd
Upload
184 views5 pages

Lab8 2-Bit Binary Adder-Subtractor

This document provides instructions for a lab activity on designing binary adders. The objectives are to design and implement a half adder, full adder using half adders, extend the design to a 2-bit binary adder, verify the functionality of a 4-bit binary adder IC, and write gate-level Verilog code for a 4-bit binary adder. The pre-lab, lab tasks, and post-lab requirements are outlined, including designing the circuits using logic gates, implementing them in hardware, drawing schematics, and testing. Students are expected to complete the pre-lab questions, tasks during the lab, and submit a full report.

Uploaded by

Mazoon Butt
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
Download as docx, pdf, or txt
184 views5 pages

Lab8 2-Bit Binary Adder-Subtractor

This document provides instructions for a lab activity on designing binary adders. The objectives are to design and implement a half adder, full adder using half adders, extend the design to a 2-bit binary adder, verify the functionality of a 4-bit binary adder IC, and write gate-level Verilog code for a 4-bit binary adder. The pre-lab, lab tasks, and post-lab requirements are outlined, including designing the circuits using logic gates, implementing them in hardware, drawing schematics, and testing. Students are expected to complete the pre-lab questions, tasks during the lab, and submit a full report.

Uploaded by

Mazoon Butt
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
Download as docx, pdf, or txt
Download as docx, pdf, or txt
You are on page 1/ 5

Department of Electrical Engineering

Faculty Member: ____________________ Dated: ________________

Semester: __________________________ Section: ________________

Group No.:

EE-221: Digital Logic Design

Lab 8: 2-bit binary Adder / Subtractor

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7


Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performanc of data in Tool Usage Safety and Team marks
e Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

EE-221: Digital Logic Design Page 1


Lab 8: 2-bit binary Adder / Subtractor

This Lab Activity has been designed to familiarize the students with design and working of
binary adders using basic logic gates.

Objectives:

 Design and Implementation of Half Adder


 Design and Implementation of a Full Adder using Half Adders
 Extending the design to add 2-bit binary numbers
 Verification of 4-bit adder IC
 Gate-Level Verilog code for 4-bit adder

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva
session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The
students will get hard copy of lab report, complete the Pre-lab task before coming to the
lab and deposit it with teacher/lab engineer for necessary evaluation. Alternately each
group to upload completed lab report on LMS for grading.
 The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely patched
circuit will simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back components
before leaving.
 The Total duration for the lab is 3 hrs.
 A lab with in-complete lab tasks will not be accepted.
 The students will complete lab task and submit complete report to Lab Engineer before
leaving lab.
 There are related questions at the end of this activity. Give complete answers.

Pre-Lab Tasks: (5 marks)


EE-221: Digital Logic Design Page 2
1. What do you understand by half and full adders and why are these circuits so named?

2. Give the truth table and circuit for half adder.

3. Design a full adder using the above designed half adders.

4. Can you extend your design to n-bit binary addition? How does input carry propagates through
full adder stages for such design and influences the speed? How can you overcome this
problem?

EE-221: Digital Logic Design Page 3


Lab Tasks: (5 makrs)

5. Implement a full adder on hardware. Give the truth table and schematic using logic diagram of
the circuit as well. Your hardware implementation should have a visual display of both inputs
and outputs.

6. Extend your design to 2-bit binary adder. Draw the schematic of the circuit, pin number each
gate input/output and carry out its hardware implementation. Your hardware implementation
should have a visual display of both inputs and outputs.

7. Get the 4-bit binary adder IC from the lab and verify its functionality. Give IC number and pin-
layout of the IC.

EE-221: Digital Logic Design Page 4


8. Give the Gate-Level Verilog Code for above adder and show the results on Simulation. Your
code should contain following modules:
half adder
full adder (by instantiating half adder)
4_bit_ binary_ adder (by instantiating full adder)
test bench_ 4_bit_binary_adder (for 4_bit_ binary_ adder )

Verilog Code:

Any Observations/Comments

EE-221: Digital Logic Design Page 5

You might also like