UNIT-I

8085 Microprocessor
Contents
•General definitions
•Overview of 8085 microprocessor
•Overview of 8086 microprocessor
•Signals and pins of 8086 microprocessor
The salient features of 8085 µp are:
•It is a 8 bit microprocessor.
•It is manufactured with N-MOS technology.
•It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory locations
through A0-A15.
•The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7.
•Data bus is a group of 8 lines D0 – D7.
•It supports external interrupt request.
•A 16 bit program counter (PC)
•A 16 bit stack pointer (SP)
• Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
•It is enclosed with 40 pins DIP (Dual in line package).
Overview of 8085 microprocessor
 8085 Architecture
•Pin Diagram
•Functional Block Diagram
Instruction Set:

8085 instruction set consists of the following instructions:

 Data moving instructions.

 Arithmetic - add, subtract, increment and decrement.
 Logic - AND, OR, XOR and rotate.
 Control transfer - conditional, unconditional, call subroutine, return from subroutine
and restarts.
 Input/Output instructions.
 Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

Addressing mode
• Register - references the data in a register or in a register pair.
Register indirect - instruction specifies register pair containing
address, where
the data is located.
Direct, Immediate - 8 or 16-bit data.

advantages of 8086 over 8085 are :

1.pipelining is employed making the execution faster.
2.databus width increased to 16 bits
3.higher memory of 1MB.
4.some instructions such as MUL or DIV are available for multiplication and division.
5.increased instruction set making the programming easier
8086 Microprocessor
•It is a 16-bit µp.
•8086 has a 20 bit address bus can access up to 220 memory locations (1 MB) .
•It can support up to 64K I/O ports.
•It provides 14, 16 -bit registers.
•It has multiplexed address and data bus AD0- AD15 and A16 – A19.
•It requires single phase clock with 33% duty cycle to provide internal timing.
•8086 is designed to operate in two modes, Minimum and Maximum.
•It can prefetches upto 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
•It requires +5V power supply.
•A 40 pin dual in line package

Architecture of 8086
•8086 has two blocks BIU and EU.
•The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
•EU executes instructions from the instruction system byte queue.
•Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.
•BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
•EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,
Flag register.
BUS INTERFACR UNIT:
• It provides a full 16 bit bidirectional data bus and 20 bit address bus.
•The bus interface unit is responsible for performing all external bus operations.

Specifically it has the following functions:

•Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and
Bus control.
•The BIU uses a mechanism known as an instruction stream queue to implement a pipeline
architecture.
•This queue permits prefetch of up to six bytes of instruction code. When ever the queue of
the BIU is not full,it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction.
•These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle.
•After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.
•The EU accesses the queue from the output end. It reads one instruction byte after the other
from the output of the queue. If the queue is full and the EU is not requesting access to operand in
memory.
•These intervals of no bus activity, which may occur between bus cycles are known as Idle
state.
 •If the BIU is already in the process of fetching an instruction when the EU request it to read
or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle
before initiating the operand read / write cycle.
•The BIU also contains a dedicated adder which is used to generate the 20bit physical
address that is output on the address bus. This address is formed med by combining the
current contents of the code segment CS register and the current contents of the instruction
pointer IP register.
•The BIU is also responsible for generating bus control signals such as those for memory read
or write and I/O read or write.
EXECUTION UNIT:
The Execution unit is responsible for decoding and executing all instructions.
•The EU extracts instructions from the top of the queue in the BIU, decodes them,generates
operands if necessary, passes them to the BIU and requests it to perform the read or write
bys cycles to memory or I/O and perform the operation specified by the instruction on the
operands.
•During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.
•If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.
•When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions
•Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions
from this new location to refill the
SPECIAL FUNCTIONS OF GENERAL PURPOSE REGISTERS

Accumulator register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of
the word, and AH contains the high-order byte. Accumulator can be used for I/O operations
and string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based
indexed or register indirect addressing.
Count register consists of 2 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low-order byte of the
word, and CH contains the high-order byte. Count register can be used as a counter in string
manipulation and shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in
I/O operations. In integer 32-bit multiply and divide instruction the DX register contains
high-order word of the initial or resulting number.
SPECIAL FUNCTIONS OF SPECIAL PURPOSE REGISTERS

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string manipulation
instructions.

The si and di registers (Source Index and Destination Index ) have some special purposes as
well. You may use these registers as pointers (much like the bx register) to indirectly access
memory. You'll also use these registers with the 8086 string instructions when processing
character strings.

The bp register (Base Pointer) is similar to the bx register. You'll generally use this register to
access parameters and local variables in a procedure.

The sp register (Stack Pointer) has a very special purpose - it maintains the program stack.
Normally, you would not use this register for arithmetic computations. The proper operation
of most programs depends upon the careful use of this register.

SEGMENTATION:
Since address registers and address operands are only 16 bits they can only address 64k bytes.
In order toaddress the 20-bit address range of the 8086, physicaladdresses (those that are put
on the address bus)are always formed by adding the values of one of the instruction is
executed? The use of segment registers reduces the size ofpointers to 16 bits.
This reduces the code size but also restricts the addressing range of a pointer to 64k bytes.
Performing address arithmetic within data structures larger than 64k is awkward. This is the
biggest drawback of the 8086 architecture. We will restrict ourslves to short programs where
all of the code, data and stack are placed into thesame 64k segment (i.e. CS=DS=SS).
Most of the registers contain data/instruction offsets within 64 KB memory segment. There
are four different 64 KB segments for instructions, stack, data and extra data. To specify
where in 1 MB of processor memory these 4 segments are located the processor uses four
segment registers:
Memory
•Program, data and stack memories occupy the same memory space. As the most of the
processor instructions use 16-bit pointers the processor can effectively address only 64
KB of memory.
• To access memory outside of 64 KB the CPU uses special segment registers to specify
where the code, stack and data 64 KB segments are positioned within 1 MB of memory
(see the "Registers" section below).

•16-bit pointers and data are stored as:

address: low-order byte
address+1: high-order byte
•Program memory - program can be located anywhere in memory. Jump and call
instructions can be used for short jumps within currently selected 64 KB code segment,
as well as for far jumps anywhere within 1 MB of memory.
•All conditional jump instructions can be used to jump within approximately +127
to -127 bytes from current instruction.
•Data memory - the processor can access data in any one out of 4 available segments,
which limits the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks).
•Accessing data from the Data, Code, Stack or Extra segments can be usually done by
prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by
default may use the ES or SS segments instead of DS segment).
•Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading word data
from even byte boundaries requires only one memory access.
•Stack memory can be placed anywhere in memory. The stack can be located at odd
memory addresses, but it is not recommended for performance reasons (see "Data
Memory" above).

Reserved locations:
•0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer
in format segment: offset.
•FFFF0h - FFFFFh - after RESET the processor always starts program execution at the
FFFF0h address.

segment registers to the 16-bit address to form a 20-bit address.

The segment registers themselves only contain themost-significant 16 bits of the 20-bit value
that iscontributed by the segment registers. The least significantfour bits of thesegment
address are alwayszero.
By default, the DS (data segment) is used fordata transfer instructions (e.g. MOV),
CS(codesegment) is used with control transfer instructions(e.g. JMP or CALL), and SS is
used with the stackpointer (e.g. PUSH or to save/restore addresses duringCALL/RET or INT
instructions).
Exercise: If DS contains 0100H, what address will be written by the instruction MOV
[2000H],AL? If CX contains 1122H, SP contains 1234H, and SS contains 2000H, what
memory values will change and what will be their values when the PUSH CX
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP)
and base pointer (BP) registers is located in the stack segment. SS register can be changed
directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX,
BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be
changed directly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions. ES register can be changed directly using POP
and LES instructions.

It is possible to change default segments used by general and index registers by prefixing
instructions with a CS, SS, DS or ES prefix.
8086 FLAG REGISTER
Flags is a 16-bit register containing 9 1-bit flags:

 Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
 .Direction Flag (DF) - if set then string manipulation instruction willauto-decrement
index registers. If cleared then the index registers will be auto-incremented.
 Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts
 Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
 Sign Flag (SF) - set if the most significant bit of the result is set.
 Zero Flag (ZF) - set if the result is zero.
 Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the
AL register.
 Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
 Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation