Notes
Notes
Rowerse hearkoucn voltage.
. Gooitehing Chanachoushes
Dyromie_hancetenisties
eS
oD
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quan ON and tenn OFF procesc gine wal,
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pom es warol “og4- she
The hansiton time
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ae pr cconel on slate Zs called
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Htewe. intenvals
L® Veta tine (te)
@ Rise time (ts)
O Spend tive (pd
ton = belt Ew Ep
ODelay time (tol) .
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J
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ts called Commutation pracess Core) From aff roe:
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o a Rewenpive (tv)
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for Heencnond
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7 A See Current.
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For Os.
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bub A 2O ir @
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foo He +
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tp fomp Ainnors
a. he ‘voltage stabiligons
oe2.2 POWER TRANSISTORS
In recent years, transistors have become available in high voltage and high current
rating. These transistors are called power transistors. The transistors, which are used as
switching elements, are operated in the saturation region, resulting in low on-state voltage
drop. The switching speed of transistors is higher than that of thyristors and they are used in
de-de and de - ac converters, with inverse parallel connected diodes to provide bidirectional
current flow. However, their voltage and current ratings are lower than those of thyristors
and therefore, transistors are normally used in low and medium power applications.
The power transistors have controlled turn - on and turn - off characteristics. These
are turned on when a current signal is given to base, or control terminal. The transistor
remains in the on - state so long as control signal is present. When this control signal is
removed, a power transistor is turned off.
Power transistors can be classified broadly into three types.
(i) Bipolar junction transistors (BJTs)
(ii) Metal - oxide-semiconductor field effect transistors (MOSFETS)
iii) Insulated gate bipolar transistors(IGBTs)
These three types are now described one after the other.
2.2.1 Bipolar junction transistors
A power BJT is a three layer, two junction npn or pnp semiconductor device. The
term ‘bipolar indicates that current flow consists of a movement of both holes and electrons.
ABBT has three terminals named collector C, emitter E and base B.POWER SEMICONDUCTOR DEVICES 27
A power bipolar junction transistor has a vertically oriented four layer structure of
alternating p-type and n-type doping such as the npn transistor as shown in figure 2.5. It has
three terminals named collector C, emitter E and base B. The NPN, PNP circuit symbols
are shown in figure. The term ‘bipolar’ indicates that current flow consists of a movement
of both holes and electrons. For high voltage and high current applications, NPN transistors
are more widely used because they are easier to manufacture and cheaper to buy.
=
re
+4 ec
F 8
14m Gop
.
Base ¥ 8
thtess 2" Pe ew
f ic
Colecor di 50-200. go em 5 eT
+ x
rho
l
Fig. 2.5 Construction of BJT and Symbol
The vertical structure is preferred for power BITs because it maximizes the cross-
sectional area through which the current in the device is flowing. This minimizes the on-
state resistance and thus the power dissipation in the transistor.
+ The doping levels in each of the layers and thickness of the layers have a significant
effect on the characteristics of the device. The doping in the emitter layer is quite large
(typically 101%cm-3), where as the base doping is moderate (10!6cm-3). The n= region that
forms the collector half of the C-B (collector - base) junction is usually termed as collector
drift region and has a light (1014cm-3) doping level. The n* region that terminates the drift ,
region has a doping level similar to that found in the emitter. The thickness of the drift region
determines the breakdown voltage of the transistor. It is a current controlled device where
the collector current is under the control of base drive current.
2.2.2 Steady - state characteristics
In most power applications, the base is the input terminal, the collector is the output
terminal, and the emitter is common between input and output (common - emitter configuration).
So henceforth, npn transistors will only be considered.
Input characteristics
The plot of base current Ip against base-emitter voltage Vp for a constant value of
Ve is shown in figure 2.6(a). As the base-emitter junction of a transistor is like a diode,28 POWER ELECTRONICS
this curve (Ip vs Vpg) resembles a diode curve. When collector-emitter voltage Vc1:2 is
more than Vp, base current decreases as shown in figure 2.6(b).
Ie
Vee,
Fig. 2.6 (a) and (b) npn Transistor circuit - Input characteristics
Output characteristics
It is represented by variation of collector current Ic with collector emitter voltage
Vce for a set base current Ip. This is shown in figure 2.7. For zero base current, i.e., for
Ip = 0, as collector-emitter voltage Vg is increased, a small leakage (collector) current
exists as shown in figure 2.7. As the base current is increased from zero to Ipi, Ip2 etc.,
collector current also increases as shown in figure 2.7.POWER SEMICONDUCTOR DEVICES 29
Saturation
region
Leakage current
Fig. 2.7 Output characteristics
The figure 2.8 shows two of the output characteristics curves, | for Ip = 0 and 2 for
Ip #0. The curve 2, characterised by low Vee, is called the saturation region. In the
saturation region, the base current is sufficiently high so that the collector - emitter voltage
is low, and the transistor acts as a switch. Both junctions (CB and EB) are forward biased.
Saturation point
Breakdown
140
Breakover
B Vee Ves
Fig. 2.8 Output Characteristics and Loadiine for npn Transistor
The flat part of curve 2, indicated by increasing Vcg and almost constant Ic is the
active region. In the active region, the transistor acts as an amplifier. (CB junction RB and
EB is FB). Almost vertically rising curve is the breakdown region which must be avoided.
For load resistor Re, the collector current Ic is given by2.10 POWER ELECTRONICS
It is the load line equation. It is shown as line AB in figure 2.8. At ideal condition,
when transistor is on, Vez = 0 and Ic= Vec/ Rc. This collector current is shown by point
A on the vertical axis. In the cut - off region, the transistor is off or the base current is not
enough to turn it on and both junctions are reverse biased. Vcc appears across the collector
- emitter terminals and there is no collector current i.e., I= 0. This value is indicated by
point B on the horizontal axis. For the resistive load, the line joining points A and B is the
load line.
Modelling of NPN transistor.
<3
Y beco
§
Bo
ca
E
Fig. 2.9 Model of NPN Transistor 7
‘The model of an NPN transistor is shown in figure 2.9, under large signal de operation.
The equation felating the currents is
Ie = Io+]p v- (10)
The ratio of the collector current Ic to the base current Ip is known as the
current gain B.
Ie
Be bre a)
lB
The collector current has two components. .". one due to the base current and the
other is the leakage current of the collector base junction.
Ic= BIB + Iceo (12)
where Icgo is the collector-to-emitter leakage current with base open circuit and can
be considered negligible compared to Blp,
From eqs (10) and (12),
Ts = Bip + Iczo + Ip
BU +B) + Iceo
Ip (1 + B) ot (13)
mPOWER SEMICONDUCTOR DEVICES 2.14
Ic (1+ 1/B)
=Ic (4)
The collector current can be expressed as
Io = alg
a = | = forward current gain.
3
Je Ip
Ray
res
a B
B= (15)
and
B
OB -- (16)
Transistor Switch
Transistor acts as a switch. It operates either in the saturation region or in the cut-off
region. An ideal switch, the transistor operates at point A in the saturated region as closed
switch with Vcg = 0 and at point B in the cut off region as an open switch with Ic = 0,
figure 2.6. In practical, the large base current will cause the transistor to work in the
saturation region at point A’ with small saturation voltage Vcgs. Here S is denoted as
saturated value. Voltage Ves representes on state voltage drop of the transistor. When the
base signal is removed or reduced to zero, the transistor is turned off and its operation shifts
to B’ in the cut-off region, figure 2.8. When the transistor is off, a small leakage current
Icgo flows in the collector circuit,
From this figure 2.6, by applying KVL we get
Vp — Relp~ Vee
Re lp = Vp~ Vp
Also from figure 2.6.
Vee = Vcr +IcRe2.42 POWER ELECTRONICS
Ver = Vec~leRe
= Veo- BIg Re [°. Ic= Bip}
BR
= Vec~ R~ (Ve - Vee) (17)
8
Ver = Ves + Vag
or = Ven = Vce- Vee (18)
If Ves is the collector-emitter saturation voltage, then collector current Ics is
given by
Ics = wn (19)
and Ips 3 = (20)
where Ips base current that produces saturation.
If the base current Ip is less than Ips, the transistor operates in the active region. The
base current Iy is more than Ips, hard drive of transistor can be obtained. In the hard
saturation, Vcgs becamos low and on-state losses of transistor are reduced. Under hard -
drive conditions, the over drive factor (ODF) is defined as the ratio of Ip and Ips.
Br
The total power loss in the two junctions of a transistor is
Pr = Vee lp + Vee Ic
2.2.3 Switching characteristics) dynamic char chew Ko}
3
Turn-on process
A transistor cannot be turned on instantly because of the internal capacitances. Figure
. 2.10(b) shows switching waveforms of an npn transistor with resistive load between collector
and emitter, figure 2.10(a). The turn - on time of the transistor is sum of delay time and rise
time. .POWER SEMICONDUCTOR DEVICES 2.13
ma
te 4 tet
Fig. 2.10 (a) Fig. 2.10 (b)
Transistor with resistive load switching waveforms for npn transistor
Delay time tg
During the delay time period, base - emitter voltage Ve is applied, the base current
Ig rises to Ips and the collector current Ic is equal to zero or collector - emitter leakage
current Icg0 as shown. This delay is due to the time required to charge base - emitter
capacitance to Veg = 0.7 V.
Rise time t,
During rise time t,, collector current Ic rises to steady state value Ics and the collector
emitter voltage falls from Vcc to Vs. The rise time depends upon the input capacitance.
‘The total turn - on time is
ton= tat ty
The transistor remains on state so long as forward base current is maintained.
Turn - off process
The turn off time of the transistor is the sum of storage time and fall time.
Storage time t,
During storage time t,, the base - emitter voltage Vag is removed at time t), the
collector current does not change and the saturated charge is removed ‘from the base.
Fall time ty
During the fall ime period ty collector current ic decreases to Iogo and the collector
emitter voltage rises to Vcc. The fall time tedepends on the time constant, which is determined2.14 POWER ELECTRONICS
by the capacitance of the reverse - biased emitter - base junction. The total turn-off time is
lon = ts + tp
Emitter Base Collector
\f LITTTTT7 a
Heel SS
Charge
Lae heen
(@) Charge storage in base (b) Charge profile during turn-off
Fig. 2.11 Charge storage in saturated bipolar transistor
‘The figure 2.11 shows the extra storage charge in the base of a saturated transistor.
During turn - off period, the extra storage charge is removed first in time ts. The charge
profile is changed from a to cas shown in fig. During fall time, the charge profile decreases
from profile until all charges are removed.
2.3 POWER MOSFET
A power MOSFET is a voltage controlled device because the output current (drain
current) can be controlled by gate-source voltage (Vgs). The power MOSFET has three
terminals called drain D, source S and gate G. The symbol of power MOSFET is shown in
figure 2.12. Here the arrow direction indicates the direction of electrons flow.
Power MOSFET is a unipolar device because its operation depends upon the flow of ©
majority carriers only. It have a very high input impedance, in the order of 109 ohm. The
gate draws a very small leakage current, in the order of nano amperes. MOSFETs do not
have the problems of secondary breakdown. However, MOSFETs have the problems of
electrostatic discharge and require special care in handling. In addition, it is very difficult to
protect them under short - circuited fault conditions. Power MOSFETS are finding increasing
applications in low - power high frequency converters.
Symbol of the power MOSFET
pd
_|5
Hs
Fig. 2.12 Symbol of Power MOSFET
‘Types of Power MOSFET
The two main types of power MOSFETs are
1. Depletion MOSFET
2. Enhancement MOSFETPOWER SEMICONDUCTOR DEVICES 215
Each type are further classified as
i) n channel MOSFET
ii) p channel MOSFET
Out of these two types, n channel enhancement MOSFET is more common because
of higher mobility of electrons. So henceforth, n - channel enhancement MOSFET will only
be considered.
2.3.1 Basic Structure of n-channel Power MOSFET
The figure 2.13 shows the constructional details of Power MOSFET. It is a planner
diffused metal-oxide-semiconductor (DMOS) structure for n-channel power MOSFET.
$ Ver $
Meta! Source Source
Sticon
“Ny sioxide
Loos :
° VV
° °
. © Substrate
Current path epee
rain
Fig 2.13 Structure of n-channel power MOSFET
The bottom layer is n* substrate. The doping density of this layer is 1019 m3. On nt
substrate, high resistivity n~ layer is epitaxially grown. The n- layer is called the drain drift
region and is typically doped at.1014— 1015 emr3. This drift region determines the breakdown
voltage of the device. On the other side n* substrate, a metal layer is deposited to form the
drain terminal. Now p- regions are diffused in the epitaxially grown n- layer. The doping
density of the p- layer is 1016 cm-3. Further, n* regions are diffused in p~ regions as shown.
The doping density of n* layer is 1019 cm-3. As before, SiO layer is added which is then
etched so as to fit metallic source and gate terminals.
2.3.2 Operation
When the gate - source voltage Vgs is zero, and drain-source voltage Vpp is present,
then n~~- p~ junctions are reverse biased and no current flows from drain to source. Now
the device is considered as a open switch.2.16 POWER ELECTRONICS
When gate terminal is made positive with respect to source, an electric field is created
and electrons form n-channel in the p~ regions as shown. Now the current flows from drain
to source and the current direction is indicated by arrows. The gate voltage Vg is increased
drain current Ip also increases. That is, output current can be controlled by gate voltage.
So Power MOSFET is also called as voltage controlled device. Here the controlling parameter
is gate source voltage Vos.
2.3.3 MOSFET characteristics (static characterisitcs)
The static characteristics of power MOSFET are described briefly. The basic circuit
diagram for n-channel power MOSFET is shown in Figure 2.14(a) where voltage and currents
are as indicated.
a) Transfer characteristics : This characteristic shows the variation of drain current Ip
asa function of gate-source voltage Vgs. Figure 2.14 (b) shows typical transfer characteristic
for n-channel power MOSFET. It is seen that there is threshold voltage Vast below which
the device is off. The magnitude of Vgsr is of the order.of 2 to 3 V.
~<
h (b)
(a) RE Load 1,(A)
|
2 4 6 8 10
Ves
Fig. 2.14 (a) N-Channel Power MOSFET circuit diagram and
(b) its typical transfer characteristics
b) Output characteristics : Power MOSFET output characteristics shown in
Figure 2.15 indicate the variation of drain current Ip as a function of drain - source voltage
Veg as a parameter. For low values of Vpg, the graph between Ip - Vps is almost linear;
this indicates a constant value of on-resistance Rps = Vps/ Ip. For given Vos, if Vps is
increased, output characteristic is relatively flat indicating that drain current is nearly constant.
A load line intersects the output characteristics at A and B. Here A indicates fully-on
condition and B fully-off state. Power MOSFET operates as a switch either at A or at B
just like a BIT.POWER SEMICONDUCTOR DEVICES. 217
Vers? Vese>Vous? Voss
Drain Current | (A)->
B Vos
Drain Source Voltage (Vex)
Fig. 2.
2.3.4 Switching Characteristics
of a Power MOSFET
The figure 2.16 shows the switching characteristics of a Power MOSFET. This
characteristics are influenced to a large extent by the internal capacitance of the device and
the internal impedance of the gate drive circuit.
Vee
Fig. 2.16 Switching characteristics
Turn - on process
The turn - on time is defined as the sum of turn - on delay time and rise time of the
device.2.18 POWER ELECTRONICS
Turn - on delay time tyq
During turn - on delay time tgn period, the input capacitance charges to gate thershold
voltage Vast and the drain current is zero.
Rise time t,
During rise time period, gate voltage rises to Vgsp. Which is the gate source peak
voltage.
This voltage is sufficient to drive the MOSFET into on state. Then drain current
increases from zero to full value of current Ip, Thus the total turn - on time is
ton = tan + ty
‘The turn - on time can be reduced by using low impedance gate drive circuit.
Turn - off process
‘The turn - off process is initiated by the removal of gate source voltage Vis at time
ty, because MOSFET is a majority carrier device. The turn-off time is the sum of turn-off
delay time tarand fall time tp
Turn - off delay time tar
During this period tgp the input capacitance discharges from over drive gate voltage
Vj to Vgsp but the drain current IT does not change.
Fall time t
During fall time tg, the input capacitance again discharges from Vosp to threshold
voltage Vast. Then drain current fall from Ip to zero. So when Vg < Vast power
MOSFET turn - off is completed.
top = tart te
2.3.5 Comparison between MOSFET and BJT
MOSFET. I BIT.
1. Power MOSFET has lower switching | BJT has higher switching losses.
losses.
2. It has more conduction losses. Ithas low conduction losses.
3, It is a voltage controlled devi Itis a current controlled device.
4. It isa unipolar device. Itis a bipolar device.
5. Power MOSFET operate at switching | BJT operate at switching frequencies
frequencies in the MHz range. in kHz range.
6. MOSFET has positive temperature BJT has negative temperature
coefficient. coefficient.
7. Secondary breakwon does not occur BIT has secondary breakdown.
in MOSFET. .
8. MOSFETs are available with ratings BJTs are available with ratings upto
upto 500V, 140A. 1200V and 800A.POWER SEMICONDUCTOR DEVICES 2.19
2.4 INSULATED GATE BIPOLAR TRANSISTOR (IGBT)
IGBT is a new development in the area of power MOSFET technology. This device
combines into it the advantages of both MOSFET and BJT. So an IGBT has high input
impedance like a MOSFET and low-onsiafS poWer loS38 in a BJT. IGBT is free from
second breakdown problem present in BJT. IGBT is also known as metal oxide insulated
gate transistor (MOSIGT), conductively-modulated field effect transistor (COMFET) or
gain-modulated FET (GEMFET). It is also called insulated gate transistor (IGT).
2.4.1, Basic Structure and Working
Figure 2.17 shows the basic structure of an IGBT. It is constructed virtually in the
same manner as a power MOSFET. There is a major difference in the substrate. The nt
layer substrate at the drain in a power MOSFET is now substituted in the IGBT by a p
layer substrate called collector. Like a power MOSFET, an IGBT has also thousands
basic structure cells connected appropriately on a single chip of silicon.
E
Vox
i+-—S
P* Substrate Current path
Metal layer
CF Collector
Figure 2.17 Basie structure of an insulated gate bipolar transistor
When gate is positive with respect to emitter and with gate-emitter voltage more than
the threshold voltage of IGBT, an n-channel is formed in the p-regions as in a power MOSFET,
figure 2.17. This n-channel short circuits the n- region with n* emitter regions. An electron2.20 POWER ELECTRONICS
movement in the n-channel, in turn, causes substantial hole injection from p* substrate layer
into the epitaxial n- layer. A forward current is established as shown in Figure 2.17.
The three layers p*, n- and p constitute a pnp transistor with p* as emitter, n- as base
and p as collector. Also n-, p and n* layers constitute npn transistor as shown in
Figure 2.18 (a). Here n- serves as base for pnp transistor and also as collector for npn
transistor. Further, p serves as collector for pnp device and also as base for npn transistor.
The two pnp and npn transistors can, therefore, be connected as shown in Figure 2.18 (b) to
give the quivalent circuit of an IGBT. Figure 2.18 (c) is the circuit symbol for IGBT with
gate (G), emitter (B) and collector (C) as its three terminals.
Ee; G
Gate
Load
he
‘Metal layer
CF Collector
2 :
pap io
ol
+ apn
q ol Boo
Resistance offered by
‘n-channel
E
(c) Symbol
(b) Equivalent circuit | E
Figure 2.18. IGBT (a) Basic structure, (b) its equivalent circuit and
(©) its circuit symbolPOWER SEMICONDUCTOR DEVICES 2.21
2.4.2 IGBT, static characteristics
The circuit of Figure 2.19 (a) shows the various parameters pertaining to IGBT
characteristics.
Saturation
region
Weer
(b) ()
Figure 2.19 IGBT (a) circuit diagram, (b) VI characteristics and (c) transfer
characteristics.
Static V-I characteristics of an IGBT (n-channel type) shows the plot of collector
current Ic versus collector-emitter voltage Vg for various values of gate-emitter voltages.
These characteristics are shown in Figure 2.19 (b). In the forward direction, the shape of
the output characteristics is similar to that of BJT. But here the controlling parameter is
gate-emitter voltage Vcr because IGBT is a voltage-controlled device.
The transfer characteristic of an IGBT is a plot of collector current Ic versus gate-
emitter voltage Vgg as shown in Figure 2.19 (c). This characteristic is same as power
MOSFET. When Vg is less than the threshold voltage Vey; IGBT is in the off-state.
When the device is off, junction J blocks forward voltage and in case reverse voltage
appears across collector and emitter, junetion J; blocks't.2.22 POWER ELECTRONICS
2.4.3 Switching Characteristics
Switching characteristics of an IGBT during turn-on and turn-off are shown in
Figure 2.20. The turn-on time is defined as the time between the instants of forward blocking
to forward on-state, Turn-on time is composed of delay time tin and rise t, i.€. ton = tan * tr.
Deiay Time
‘The delay time tin is defined as the time for the collector-emitter voltage to fall from
Vee to 0.9 Veg. Here Veg is the initial collector-emitter voltage. Time tin may also be
defined as the time for the collector current to rise from its initial leakage current Ice, to 0.1
Ic, Here Ic is the final value of collector current. During this period, gate emitter voltage
increases from zero to gate emitter thershold voltage (VcET)
Vee
=
‘
¥
5 Figure 2.20 IGBT turn-on and turn-off characteristics
‘4 Rise Time t,
Ni
_ __ Therise time t, is the time during which collector-emitter voltage falls from 0.9 Voce
to 0.1 Vog. Tt is also defined as the time for the collector current to ri8e iroia 0.1 Ic to its
final value Ic, After time ton, the collector current is Ic and the collector-emitter voltage
falls to small value called conduction drop = Vces where subscript S denotes saturated
value.
Turn-off process
The turn-off time consists of three intervals; (i) delay time, tar (ii) initial fall time, tq,
and (iii) final fall time, tp; ie. torr= tart t + tp.POWER SEMICONDUCTOR DEVICES. 2.23
Delay Time tag
‘The delay time is the time during which gate voltage falls from Vg to threshold
voltage Ver. As Vor falls to Vopr during tye, the collector current falls from Ic to 0.9 Ic.
At the end of tgs, collector-emitter voltage begins to rise.
First Fall Time tg
The first fall time te is defined as the time during which collector current falls froin
90 to 20% of its initial value Ic, or the time during which collector-emitter voltage rises from
Vers to 0.1 Vop.
Final Fall Time tp
‘The final fall time ty is the time during which collector current falls from 20 to 10%
of Ic, or the time during which collector-emitter voltage rises from 0.1 Vcg to final value
Vcp. see Figure 2.20.
24.4 Applications of IGBT
IGBTs are widely used in medium power applications such as de and ac motor drives,
UPS systems, power supplies and drives for solenoids, relays and contactors. Though IGBTs
aie more expensive than BJTs, they are becoming popular because of lower gate-drive
requirements, lower switching losses and smaller snubber circuit requirements. IGBT
ower switchi snub
converters are more efficient with less size as well as cost, as compared to converters
based on BITS. Recently, IGBT inverter induction-motor drives using 15-20 kHz switching
frequency are finding favour where audio-noise is objactionable Tn most applications, IGBTs
are replaced by BITs.” At present, IGBTs are available upto 1200 V, 500 A. ~2.8 BIDIRECTIONAL TRIODE THYRISTOR (TRIAC)
We have seen that the conventional thyristor, or SCR, has a reverse-blocking
characteristic that prevents current flow in the cathode-to-anode direction. However, there
are many applications, particularly in a.c.circuits, where bidirectional conduction is required.
Two thyristors may be connected in inverse-parallel, but at moderate power levels the two
antiparallel thyristors can be integrated into a single device structure, as shown in Figure
2.36(a). This device, commonly known as Triac (triode a.c. switch) is represented by the
circuit symbol shown in Figure 2.36(b).
Triac is the word derived by combining the capital letters from the words TRlode and
A.C. As the Triac can‘conduct in both the directions, the terms anode and cathode are not
applicable to Triac. Its three terminals are usually designated as main terminals, MT), MT)
and gate G, as ina thyristor. The terminal MT, is the reference point for measurement of
voltages and currents at the gate terminal and at the terminal MT. The gate is near to
terminal MT}, The V-I characteristic of a Triac is shown in Fig. 2.36(c). This characteristics
of the Triac are based on the terminal MT} as the reference point. The first quadrant is the
region wherein MT} is positive with respect to MT; and vice-versa for the third-quadrant.
‘The peak voltage applied across the device in either direction must be less than the
breakover voltage in order to retain control by the gate. A gate current of specified amplitude
of either polarity will trigger the Triac into conduction in either quadrant, assuming that the
device is in a blocking condition initially before the gate signal is applied. The characteristics
ofa Triac are similar to those of an SCR, both in blocking and conducting states, except for
the fact that SCR conduets only in the forward direction, whereas the Triac conducts in both
the directions. Depending upon the polarity of a gate pulse and biasing conditions, the main
four-layer structure that turns on by a regenerative process could be one of Py Ny P2 Np, Pi
Ny P2 N3 or Py Ny Py Ng.POWER SEMICONDUCTOR DEVICES
MT,
MT,
N
G
jp-——»J er
Py
nT 6
N. a Ohmic contact Mt,
P (b) Circuit symbol
N : <— Metallic lead
(a) MT,
A Na? a? bale
Quadrant |
(MT, negative)
Quadrant
(MT, negative)
025883
(c) Characteristics of a triac
Fig. 2.36 Triac structure and characteristics
2.8.1 Triggering Modes of Triac
Triac can be turned on with positive or negative gate current keeping the MT terminal
atpositive or negative potential. Triggering can be obtained from d.c., rectified a.c., or pulse
sources such as unijunction transistors and switching diodes such as the Diac, silicon bilateral
switch (SBS) and asymmetrical trigger switch. Here we discuss different operating modes
of triac.
1.. MT} positive, positive gate current (Mode 1) When the gate current is positive
with respect to MT}, gate current flows mainly from the gate lead to the terminal through
theP2-Np junction, as shown in Figure 2.37. The device turns on in the conventional manner
asin the case of an SCR. However, in the case of a Triac, the gate current requirement is
higher for turn on at a particular voltage. Because of ohmic contacts of gate and MT;2.52 POWER ELECTRONICS
terminals on the P -layer, some more gate current flows from the gate lead G to the main
terminal MT through the semiconductor P. layer without passing through the PN junction,
The main structure which ultimately tums on through regenerative action is Py Ny P
No. The P, layer is flooded with electrons when the gate current Ig flows across the P2-Np
junction. These electrons diffuse to the edge of the junction J, and are collected by the N,
layer. Therefore, the electrons build a space charge in the N; region and more holes from
P; diffuse into Nj to neutralize the negative space charge. The holes arrive at the junction
Jo. They produce a positive space charge in the P2, region which results in more electrons
iB injected from Nz into P. This results in positive regeneration and ultimately the
structure P; Nj P2 Nz conducts the external current.
tp
G+)
Fig. 2.37 MT, positive, positive gate current
2. MT} positive, negative gate current (Mode 2) A cross-sectional view ot the
structure is shown in Figure 2.38.
When the terminal MT) is positive and gate terminal is negative with respect to
terminal MT) gate curmet flows through P2-N> junction and this gate current Iy forward
biases the gate junction P-N3 of the auxiliary P; Nj P Ng structure. As a result, Triac
starts conducting through P, Nj P N3 layers initially. With the conduction of Py Ny P Na,
the voltage drop across it falls but potential of layer between P2 N3 rises towards the anode
Potential of MT>. As the right hand portion of P is clamped at the cathode potential of MT;
a potential gradient exists across layer Pp, its left hand region being at higher potential than
its right hand region. A current is thus established in layer P2 from left to right which
forward biased P2 No junction and finally the main structure P, Ny Pz Np begins to conduct.POWER SEMICONDUCTOR DEVICES 2.53
The device auxiliary structure, P| N Pz Nz may be considered as a pilot SCR. while
the structure, Py Ny P) Np, may be regarded as the main SCR, both being built in one
common structure. The anvde current of the pilot SCR serves as the gate current for the
main SCR. As compared with turn on process discussed in the above section, the device
with MT> positive but gate current negative is less sensitive and therefore, more gate current
is required.
c-)
Final conduction
+"
(P.N,P,N,)
J, a
Initial conduction
ty
(PNPM) N,
J
P,
MT,(+)
Fig. 2.38 MT, positive, negative gate current
3. MT negative, positive gate current (Mode 3)~-When terminal MT) is negative and
terminal MT, is positive, the device can be turned on by applying a positive voltage between
the gate and terminal MT}. During this mode, the device operates in the third quadrant
when it is triggered into conduction. The turn on is initiated by remote gate control. The main
structure that leads to turn on'is Pz Ny Py Nq with Ng acting as a remote gate as shown in
Figure 2:39. .
The external gate current I, forward biases P Np junction. Layer Np injects electrons
into P2 layer as shown by dotted arrows and are coliected by the junction Py Nj. The
electrons from Np collected by P> Nj junction cause an increase of current through the
Junction P2 Nj. The holes injected from P, diffuse through Ny and arrive in P}. Hence, a
Positive space charge builds up in the P region. More electrons from Na diffuse into P to
neutralize the positive space charge. These electrons arrive at the junction J. They produce
negative space charge in the Ny region which results in more holes being injected from P
into Nj. This regenerative process continues until the structure P2 Ny P; Nq completely254 POWER ELECTRONICS
turns on and conducts the current which is limited by the external load. As the Triac is
turned on by remote-gate Np, the device is less sensitive in the third-quadrant with positive
gate current.
P,
N
Final conduction
een meine co
: P, (P,N,PLNO
x
+
No
MT)
Fig. 2.39 MT, negative, positive gate current
4, MT? negative, negative gate current (Mode 4) A cross-sectional view of the
structure is shown in Figure 2.40. In this mode of operation, N3 acts as a remote gate. The
external gate current Ig forward biases P2 N3 junction and electrons are injected as shown
by the dotted arrows. These electrons from N3 collected by P2 Nj cause an increase of
current across Py Ny. The structure Pz Nj Py Ng turns on by the regenerative action. The
device will turn on due to the increased current in layer Ny. The device is more sensitive in
this mode compared with the turn on by the positive gate current as discussed above.
£e rom the above four operating modes of Triac, it becomes more sensitive of the Triac
ty fest in the first quadrant when turned on with positive gate current-and also in the
thd quadrant when turned on with negative gate current Ig.
ous The sensitivity of the Triacis slightly lower inthe first quadrant when turned on with
AA __ Reative gate current. Futher, the Triac is much less sensitive in the third-quadrant with the
Positive gate current, Thus, the Triac is rarely operated in the first quadrant with negative
gate current and in the third-quadrant with positive gate current. x .
Explain why wWac & Vas ry operctad °
BHO] a achcunt, WoL -ve gare cuysent Cind
Veadant wih ive gare CLG BUNPOWER ELECTRONICS
6a)
MT)
N,
wit ;
Wt 0
P,
N,
P,
N
MT,(-)
Fig. 2.40 MT, negative, negative gate current
Due to the interaction between the two halves of the device, Triacs are limited in
voltage, current, and frequency ratings as compared with conventional thyristors. The Triac
finds widespread use in consumer and light industrial appliances operating from 50 or 60 Hz
ac. supplies at moderate power levels. The plastic encapsulated Triac is a particularly
cheap and compact device and is widely used for controlling the speed of single-phase a.c.
series or universal motors, in such consumer appliances as food mixers and portable drills.
2.82. Advantages and Disadvantages of Triac
Advantages
1. Triacs can be triggered with positive or negative polarity voltages.
2. A Triac needs a single fuse for protection, which also simplifies the construction.
3. A Triac needs a single heat sink of slightly larger size, where as antiparallel
thyristor pair needs two heat sinks.
4. In some de applications, SCR is required to be connected with a parallel diode to
protect against reverse voltage, whereas a Triac used may work without diode,
as safe breakdown in either direction is possible.
Disadvantages
1. Triac have low dv/dt rating compared to SCRs.
2. Since a Triac can be triggered in either direction, a trigger circuit with Triac needs
careful consideration.DYyiwence Hehoeen SceR and
Scr
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