1/25/2020 Interviews question on coverage in system verilog ??

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Interviews Question On Coverage In System Verilog ??

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What is coverage ?

Coverage is defined as the percentage of verification objectives that have been met. It is used as a metric for evaluating the progress
of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also
provides good feedback to the quality and e ectiveness of constrained random testbenches. Broadly there are two types of coverage
metrics – Code Coverage and Functional Coverage. While code coverage is generated automatically by simulators, Functional
coverage is user defined and normally implemented using constructs supported by SystemVerilog language. This section has
questions related to the coverage concepts as well as the SystemVerilog language constructs used for implementing functional
coverage model.

1. What is the di erence between code coverage and functional coverage?

There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and e iciency of
verification process.
1) Code Coverage: Code coverage is a metric used to measure the degree to which the design code (HDL model) is tested by a given
test suite. Code coverage is automatically extracted by the simulator when enabled.
2) Functional Coverage: Functional coverage is a user-defined metric that
measures how much of the design specification, as enumerated by features in the test plan, has been exercised. It can be used to
measure whether interesting scenarios, corner cases, specification invariants, or other applicable design conditions — captured as
features of the test plan — have been observed, validated, and tested. It is user-defined and not automatically inferred. It is also not
dependent on the design code as it is implemented based on design specification.

2. What are the di erent types of code coverage?

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1/25/2020 Interviews question on coverage in system verilog ?? - Hardware Design and Verification

Code coverage is a metric that measures how well the HDL code has been exercised by the test suite. Based on the di erent program
constructs, code coverage are of following types:

1) Statement/Line coverage: This measures how many statements (lines) are covered during simulation of tests. This is generally
considered important and is targeted to be 100% covered for verification closure. In the following example code, you can see there are
4 lines or statements which will be measure in statement/line coverage.

always @ (posedge clk) begin if( A > B) begin

//Line 1 Result = A – B;

//Line 2 end else begin

//Line 3 Result = A + B;

//Line 4 end end

2) Block coverage: A group of statements between a begin-end or if-else or case statement or while loop or for loop is called a block.
Block coverage measures whether these types of block codes are covered during simulation.

end
3) Branch/Decision coverage: Branch/Decision coverage evaluates conditions like if-else, case statements and the ternary operator (?:
) statements in the HDL code and measures if both true and false cases are covered.
4) Conditional Coverage and Expression coverage: Conditional coverage looks at all Boolean expressions in the HDL and counts the
number of times the expression was true or false. Expression coverage looks at the right-hand side of an assignment, evaluates all the
possible cases as a truth table and measures how well those cases are covered. Following is an expression of 3 boolean variables that
can cause the Result variable to be true of false Result = (A && B) || (C) You can create a truth table as follows for all possible cases of A,
B and C that can cause result to be true or false. The expression coverage gives a measure of if all the rows of this truth table are
covered.
5) Toggle coverage: Toggle coverage measures how well the signals and ports in the design are toggled during the simulation run. It
will also help in identifying any unused signals that does not change value.
6) FSM coverage: FSM coverage measures whether all of the states and all possible transitions or arcs in a given state machine are
covered during a simulation

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