Thermometer To Binary Code Endoder For 4 Bit Flash ADC
Thermometer To Binary Code Endoder For 4 Bit Flash ADC
2017, India
I. Introduction
Analog-to-digital converters (ADCs) are the important
functional unit in the signal processing, system on chip and
mixed signal design applications. ADC form the interface
between the analog environment and digital system. Among
various ADC architectures [1-4], the flash ADC [5-7] is used Fig.1 . N bit Flash ADC
for high speed and lower resolution applications. Fig 1 shows
the structure of conventional flash ADC. The flash ADC A. ROM Based Encoder
consists of 2N -1 comparators for N-bit resolution, where the ROM based encoder [10] architecture consists of two stages.
analog input is compared with the reference voltage to give the Initially, the input thermometer code is first converted to one
output as ‘0’ or ‘1’ . The comparator outputs are converted to hot code or 1-out of 2N-1 code. In the next stage, the one hot
binary code using thermometer to binary encoder. Since power code is the address location for the binary ROM. Binary ROM
and delay are the important constraints in IC design, it is is a memory location where the equivalent binary code for the
important to design ADC with high speed and less power. The thermometer code is present. But this architecture has the
encoder in the flash ADC consumes suitable amount of power disadvantage of high power consumption and large delay
and delay. Hence, a novel encoder is presented in this paper because of high static current that flows while pre-setting the
which consumes less power and delay compared to existing ROM encoder.
encoder architectures.
The rest of the paper is organised as follows: Section II B. Wallace Tree Encoder
discusses the existing Encoder architectures. In Section III, Wallace tree encoder [11] encoder basically counts the
proposed encoder design is explained. Section IV presents number of 1s in the input thermometer code. Therefore it
simulation results for the proposed design. Finally, is also called “Ones counter”. Fig 2 shows the Wallace tree
conclusions are drawn in Section V. encoder. The counter topology can be selected based on the
speed of ADC. But the architecture has disadvantage of large
II. Existing Encoders delay and power.
Various encoders [8-9] such as Wallace tree encoder, fat tree
C. Fat-Tree Based Encoder
encoder, multiplexer (MUX) based encoders are used in flash
Fat tree encoder [12] has less delay and area when compared
ADC. These encoders are discussed in following subsections.
to ROM based encoder and wallace tree encoder. Fig 3 shows
the 15 to 4 bit fat tree encoder.
978-1-5090-3704-9/17/$31.00 © 2017 IEEE
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2017 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India
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2017 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India
G4 = T8 for the lower resolution flash ADC. Fig.4 shows how the self-
reconfigurable property is used to design 3-bit encoder from
G3 = T4T12 the 4-bit encoder.
G2 = T2T6 + T6(T10T14)
Here the input line ‘1’of some of the MUXs are connected to
ground terminal, to reduce the number of MUXs and avoid the
need of additional inverters when compared to the existing Fig. 8. 2:1 MUX using transmission gate logic.
MUX based design. The 2:1 MUX and 2 input XOR gates are
implemented in the transmission gate logic style [16] to
achieve low power consumption as shown in fig 8,9.
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2017 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India
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