PSG COLLEGE OF TECHNOLOGY

COIMBATORE - 641004

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

ELECTRONIC DEVICES AND DIGITAL ELECTRONICS LABORATORY(15E311)

POST LAB REPORT ON

STUDY OF BASIC DIGITAL IC'S AND IMPLEMENTATION OF ADDER
AND SUBTRACTOR CIRCUITS
Date of Submission:26.07.2019

Submitted by:

NAME ROLL NO. MARKS AWAREDED

KAVIA SUDHAN 18E123
KISHAN BALAJI .G 18E124
Submitted to:

Dr.SUMATHI. S

PROFESSOR
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING,
PSG COLLEGE OF TECHNOLOGY

MARKS AWARDED FACULTY SIGNATURE

STUDY OF BASIC DIGITAL IC'S AND IMPLEMENTATION OF ADDER
SUBTRACTOR CIRCUITS

AIM:

To study basic digital IC’s and the implementation of adder and subtractor
circuits.

APPARATUS REQUIRED:

IC 74LS08,IC 74LS04,IC 74LS86,IC 74LS32,IC 74LS83,digital trainer kit.

LOGIC GATES:

Logic gates are the heart of digital electronics. A gate is an electronic

device which is used to compute a function on a two valued signal. Logic gates
are the basic building block of digital circuits.

Basically, all logic gates have one output and two inputs. Some logic gates
like NOT gate or Inverter has only one input and one output. The inputs of the
logic gates are designed to receive only binary data (only low 0 or high 1) by
receiving the voltage input.The low logic level represents Zero volts and high
logic level represents 3 or 5 volts positive supply voltage.

By combining logic gates, we can design many specific circuits like flip
flops, latches, multiplexers, shift registers etc. . The manufacturers will follow the
TTL or Transistor – Transistor Logic as standard voltage level, while designing
the ICs.
AND

INPU
OUTPUT
T

A B A AND B

0 0 0

0 1 0

1 0 0

1 1 1

OR

 
 INPU
OUTPUT
T

A B A OR B

0 0 0

0 1 1

1 0 1

1 1 1

NAND

 or 

INPU
OUTPUT
T

A NAND
A B
B
 0 0 1

0 1 1

1 0 1

1 1 0

NOR

INPU
OUTPUT
T

A B A NOR B

0 0 1

0 1 0

1 0 0
 1 1 0

XOR

INPU
OUTPUT
T

A B A XOR B

0 0 0

0 1 1

1 0 1

1 1 0
.XNOR

INPUT OUTPUT
 A B A XNOR B

0 0 1

0 1 0

1 0 0

1 1 1

De Morgan equivalent symbols

By use of De Morgan's laws, an AND function is identical to an OR function with
negated inputs and outputs. Likewise, an OR function is identical to an AND function
with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated
inputs, and a NOR gate is equivalent to an AND gate with negated inputs.
This leads to an alternative set of symbols for basic gates that use the opposite core
symbol (AND or OR) but with the inputs and outputs negated. Use of these alternative
symbols can make logic circuit diagrams much clearer and help to show accidental
connection of an active high output to an active low input or vice versa. Any connection
that has logic negations at both ends can be replaced by a negationless connection and
a suitable change of gate or vice versa. Any connection that has a negation at one end
and no negation at the other can be made easier to interpret by instead using the De
Morgan equivalent symbol at either of the two ends. When negation or polarity
indicators on both ends of a connection match, there is no logic negation in that path
(effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to
the next. This is commonly seen in real logic diagrams – thus the reader must not get
into the habit of associating the shapes exclusively as OR or AND shapes, but also take
into account the bubbles at both inputs and outputs in order to determine the "true" logic
function indicated.
A De Morgan symbol can show more clearly a gate's primary logical purpose and the
polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the
simplified case where a two-input NAND gate is used to drive a motor when either of its
inputs are brought low by a switch. The "signaled" state (motor on) occurs when either
one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND
logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is
of interest. The regular NAND symbol has a bubble at the output and none at the inputs
(the opposite of the states that will turn the motor on), but the De Morgan symbol shows
both inputs and output in the polarity that will drive the motor.
De Morgan's theorem is most commonly used to implement logic gates as combinations
of only NAND gates, or as combinations of only NOR gates, for economic reasons.

INTRODUCTION TO BINARY ADDERAND SUBTRACTOR:

A binary adder and subtractor is combination operation at additional and

subtractional with a circuit that performs the arithmetic operation at additional and
subtractional level with a binary number, this circuit is developed by full order and
corcade producers a binary adder for n-bit adder number.

HALF ADDER:

A half adder is a basic adder circuit by itself it converts perform conditions at

number of times more than 1-bit . It is provision for batteries from proceeding bit.

The input variables designed and added bits the output one the sum and the
carry. If A and B are inputs and sum of carry are output. These are sum at
products oppressions are,

S=A’B+AB’

C=A.B

It can be implemented with exclusive, OR and AND gate.

DESIGN OF HALF ADDER:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
By principle of products at high values,

Sum=A’B+AB’

Carry=A.B

It is a combination that performs arithmetic sum of three bits.It consists of 3 and 2

output. The specified expression.

Sum=A’BC’+AB’C’+ABC

=A’(B’C+BC’)+A(B’C’+BC)

=A’(B+C)+A()

=⊕⊕

This expression is for full adder.

Sum=AB’C+A’BC+AB’C’+ABC

=(A⊕B)⊕C

=AB+(A⊕B)

DESIGN OF FULL ADDER:

A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 1 1 0
0 1 0 0 1
1 0 1 1 0
1 0 0 0 1
1 1 0 0 1
1 1 1 1 1

Sum=A’B’C+A’BC’+AB’C’+ABC

=A’(B’C+BC’)+A(B’C’+BC)

=A’(B⊕C)+A(⊕)

=⊕⊕

Here, 2 EX-OR gates are coupled.

Carry=A’BC+AB’C+ABC’+ABC

=(A’B+BA’)+AB(C’+C)

=C(A⊕B)+AB
=low(4 bit adder)

A 0 0 1 1
B 1 0 0 0
E 1 0 1 1

A4=0 , A3=0 , A2=1 , A1=1

B4=1 , B3=0 , B2=0 , B1=0

E4=1 , E3=0 , E2=1 , E1=1

HALF SUBTRACTION CIRCUIT:

It has 2 input and output. The one input A and B from minuend and subtracted .
A is different output and B is borrow output.

DESIGN OF HALF SUBTRACTION:

Difference=P.Q+P.Q-P⊕Q

Borrow=.Q

P Q DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
FULL SUBTRACTOR CIRCUIT:

It has 3 inputs and 2 outputs. A,B and C are inputs to be subtract in which B
represents next stage.

D-Difference , B-Borrow

D=ABC+ABC+ABC+ABC

B=ABC+ABC+ABC+ABC.

DESIGN OF FULL SUBTRACTOR:

A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Difference=C+B+A+ABC
= (CC+B)+A(+BC)

=A⊕B⊕C.

Borrow=ABC+ABC+ABC+Abc

=C(AB+AB)+AB(C+C)

=C(⊕)+B

Here a combination of EX-OR,NOT,AND,OR gates are used.

H-High(4-bit subtractor)

IC-74LS83 as adder- subtractor:

Sl.no. A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 C M
1 1 0 0 1 0 0 1 1 1 1 0 0 0 0
2 1 1 1 1 1 0 1 0 1 0 0 1 1 0

without EXOR:

Sl.no A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 C M
.
1 1 1 1 1 1 0 1 0 1 0 0 1 1 0
2 0 1 0 1 0 0 0 0 0 1 0 1 0 0

INPUT:

1 1 0 0
1 0 0 0
0 1 0 0

DIFFFERENCE:

A1=1 A2=1 A3=0 A4=0

B1=1 B2=0 B3=0 B4=0

E4=0 E3=1 E2=0 E1=0 Cout=0

IC 74LS04

INPUT OUTPUT
0 1
1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

IC 74LS08

IC 74LS86

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
IC 74LS32

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
PROCEDURE:

The circuit diagram and truth table of OR, AND, NOT, EXOR gates in IC’S are
taken from the datasheet. Here IC74LS04(NOT GATE), IC74LS08(AND GATE),
IC74LS32(OR GATE), IC74LA86(EXOR GATE) are used. In that, the pair 7 and
14 are connected to ground and +vccrespectively. The circuit diagram and truth
table of half and full adder, half and full subtractor is verified.

OVERFLOW:

When a 2 member with its digital each are added and sum is a number (n+1)
digital there is an overflow occurs. This is true for binary and decimal number
signed (or) unsigned overflow is a problem in digital computers because the no.
of bits that number is infinite as a result contains (n+1) bits cannot be
accommodated by n-bits words.

4-bit binary adder/subtractor:

A binary adder or subtractor is combinational circuit that performs a arithmetic

operation of addition and subtraction with binary numbers . The circuit is included
in complementary circuits.
IC 74S83 as a adder:

Sl.no A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 S4
.
1 0 1 0 1 0 0 0 0 1 0 1 0 0
2 1 0 1 0 1 1 1 1 1 0 1 0 1

WITHOUT EXOR:

Sl.no. A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 S4
1 0 0 1 0 0 0 0 1 0 0 0 1 1
2 1 0 1 0 1 1 1 1 0 1 1 0 1
PRE-LAB QUESTIONS:

1) What do you mean by logic gates? Write the applications?

A logic gate is a elementary building block of digital circuit in electronics building

block of digital circuit in electronics. A logic gate is an idealizes or physical input
that produces a signal logic output.

APPLICATIONS:

● NAND gate is used as burgler alarm, freezer ,warningbrazzers , a push

button and a safety thermostat.
● OR gate is used to detect exceeding of temperature and pressure and
gives a signal.
● AND gate measurement of frequency.
● NOT gate used as insulators.

2) Why do you classify families? Compare RTL’s and CMO’s family.

We classif family because many families were produced as individual

components each containing one or few basic related concepts which relates
basic logic functions, which could be used as a “building blocks” to crete systems
or as so called “glue” to interconnect more complex IC’s.

CLASSIFICATION:

BIPOLAR UNIPOLAR

SATURATED NON-SATURATED

1. RTL 1. Schottky 1. PMO’s

2. CSL 2. DIC 2. NMO’s

3. RRL 3. CMO’s

RTL’s CMO’s
● Power dissipation is typically ● Power dissipitation is usually to
KW per gate.
to KW per gate.

● Propagation delay are when

● Propagation delay are usually
during 9RR\400s load V level
round 25ns to 50ns. Voltage
ranges from 0 to VCC is typically
leads range from 0 to VOP
4.75 to 5.2 V.
(supply voltage).

3) Simplify expressions and verify the truth table.

Y=AB+A(B+C)

=AB+A(B’+C’)

=A(B+B’).(B+C’)A(B+B+C)

=A(B+C)

Y=AB+AC

By demorgan’s law,
[(A+B)’=A’B’]
B’+B=B.

A B C A.B B+C (B+C) A(B+C) AB+A(B+C) AC AB+AC

’
0 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 0
0 1 0 0 1 0 0 0 0 0
0 1 1 0 1 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 1 0 1 1 0 1
1 1 0 1 1 0 1 1 0 1
1 1 1 1 1 0 1 1 1 1

4)Explain 74L5834-bit adder:

● The 8N5474L583 4-bit adder is a high speed.

● 4-bit binary full adder with internal carry look like a head.
● It accepts 4-bit binary adder 1 output form the MSB.
● The l5834 operates 8N5474L583 is recommended for new design. Since it
is identical in function with this device.

5)Difference between full adder and half adder?

Half adder Full adder

● It adds signal binary digits A ● It adds binary number and
and B. It has 2 outputs sum & accounts for values carried is
carry. output.

● A carry signal represents an ● A one bit full adder adds 3-1 bit
overflow into next digits of number full adder usually a
multidigit addition. components in cascade of
adder.

● It adds8, 16, 32 but binary

● The input variable of half adder
numbers.
are called aligned & added bits.
POST LAB QUESTIONS

1. Why half adder is called as half adder and full adder is called as full
adder ?

Ans.

The half adder can add only two input bits (A and B) and has nothing to do
with the carry if there is any in the input. So if the input to a half adder have a
carry, then it will neglect it and adds only the A and B bits. That means the
binary addition process is not complete and that’s why it is called a half adder.

full adders are the ones used for adding, we call them "full" adders.And since
a full adder can be made by joining up two half adders with an OR gate, the
half adder becomes "half" an adder.

2. What is the major difference between half adder and full adder ?

Ans.

Full adder Half adder

1. Full Adder, along with two 1-bit 1. Half Adder adds two 1-bit numbers
numbers can also add the carry given as input but do not add the carry
obtained from previous addition. obtained from previous addition
2. Full Adder consists of two EX-OR 2. Half Adder consists of one EX-OR
gates, two AND gates and one OR gate and one AND gate
Gate.

3. What is the difference between half subtractor and full subtractor ?

Ans.

Full subtractor Half subtractor

The full subtractor is a The half subtractor is a
combinational circuit combinational circuit
which is used to perform which is used to perform
subtraction of three input subtraction of two bits.
bits: the minuend X the minuend X

, subtrahend Y and subtrahend Y

, and borrow B. and two outputs the

difference D

and borrow out B .

4. What is the requirement of full subtractor circuit ?

Ans.

A full subtractor is a combinational circuit that performs subtraction of two bits,

one is minuend and other is subtrahend, taking into account borrow of the
previous adjacent lower minuend bit. This circuit has three inputs and two
outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and
previous borrow, respectively. The two outputs, D and Bout represent the
difference and output borrow, respectively.

5. What are the applications of full subtractor ?

Ans.

Applications of Full Subtractor

● These are generally employed for ALU (Arithmetic logic unit) in

computers to subtract as CPU & GPU for the applications of graphics to
decrease the circuit difficulty.
● Subtractors are mostly used for performing arithmetical functions like
subtraction, in electronic calculators as well as digital devices.
● These are also applicable for different microcontrollers for arithmetic
subtraction, timers, and program counter (PC)
● Subtractors are used in processors to compute tables, address, etc.
● It is also useful for DSP and networking based systems.

6. Define BCD adder and subtractor .

Ans.

BCD adder

A 4-bit binary adder that is capable of adding two 4-bit words having a BCD
(binary-coded decimal) format. The result of the addition is a BCD-format 4-bit
output word, representing the decimal sum of the addend and augend, and a
carry that is generated if this sum exceeds a decimal value of 9. Decimal
addition is thus possible using these devices.

BCD subtractor

A 4-bit binary subtractor that is capable of subtracting two 4-bit words having
a BCD (binary-coded decimal) format. The result of the subtraction is a BCD-
format 4-bit output word, representing the decimal sum of the minuend and
subtrahend, and a borrow that is generated if this difference exceeds a
decimal value of 9. Decimal subtraction is thus possible using these devices.
RESULT:

Basic digital IC'S and the implentation of adder and subtractor circuits are studied
and verified.