(2½ Hours) [Total Marks: 75]

N. B.: (1) All questions are compulsory.

(2) Make suitable assumptions wherever necessary and state the assumptions made.
(3) Answers to the same question must be written together.
(4) Numbers to the right indicate marks.
(5) Draw neat labeled diagrams wherever necessary.
(6) Use of Non-programmable calculators is allowed.

1. Attempt any three of the following: 15

a. Describe a Microprocessor based system.

Describe function of each

b. Explain the terms:-

i) Word
ii) Byte
iii) Nibble
iv) Machine language
v) Assembly language
c. Explain Tristate device logic and Buffer.

d. Write a short note on classification of memory.

 Describe each in a single line.
e. Draw a neat label functional block diagram of 8085 microprocessor and explain the
flags of the flag register.
f. Explain the timing diagram of The Memory Read Cycle.

1. The microprocessor places a 16 bit address on the address bus which selects
only register. The lower order is seen on AD 0 - AD7. The higher order is
seen on A 15 - A9
2. Attempt any three of the following: 15
a. Explain the working of the OUT instruction in 8085 microprocessor.
b. Explain the memory mapped I/O with STA 8000H stored at memory address
2050H.
The device selection has the following steps :-
c. List and explain the various data transfer instruction.

d. What is a instruction , instruction word size and their types based on size ?
e. Explain the following instruction
I)ADI : Add Immediate Data to Accumulator \

ii) JC : Jump on Carry

Example JC 2050 transfers control to instruction stored at 2050H when the
carry flag is set to 1
iii) XRA : EX-OX the content of the Register with accumulator

iv) ORI : OR Immediate data to Accumulator

 v) JNZ : Jump on no Zero
Example JNC 2050 transfers control to instruction stored at 2050H when the
ZERO flag is set to 0

f. Write an assembly program for 8085 microprocessor to add the content of C030H
and C031H . Store the sum in C040H and carry at C041H.
MVI A,00H
MVI B,00H
MVI C,00H
LDA C030H
MOV B,A
LDA C031
ADD B
JNC HERE
INR C
HERE: STA C040
MOV A,C
STA C041
HLT

3. Attempt any three of the following: 15

a. Write an assembly program for 8085 microprocessor to transfer the contents of 10
memory location from C030H- C039H to C040H - C041H.
MVI C, 0AH
LXI H, CO30H
LXI D, CO40H
HERE: MOV A,M
STAX D
INX H
INX D
DCR C
JNZ HERE
HLT
b. Explain the various Rotate Instruction for 8085 microprocessor
 Example :rotate the contents of the accumulator right, if it contain AFH and the
carry flag is reset to 0

c. Calculate the time delay for the 8085-based Microcomputer with 2 MHz clock
frequency.
Label Mnemonics Operand T cycle
MVI C,FFH 7
LOOP: DCR C 4
JNZ LOOP 10/7
d. Draw and explain a flowchart for a zero to nine counter.

e. What is a stack ? What are the two operations on the stack?

f. Explain the execution of a CALL instruction for 8085 microprocessor and its effect
on the stack pointer and program counter.
4. Attempt any three of the following: 15
a Write an assembly program for 8085 microprocessor to convert 72BCD to its binary
equivalent.
MVI A, 72H
MOV B,A
ANI 0FH
MOV C,A
MOV A,B
ANI F0H
RRC
RRC
RRC
RRC
MOV D,A
XRA A
MVI E,0AH
HERE : ADD E
DCR D
JNZ HERE
ADD C
STA C040H
HLT
b Explain the following instruction :-
i) LHLD and SHLD 02
02
01

ii) XCHG and XTHL

XCHG : Exchange the content of the HL register Pair with DE Register
Pair respectively
XTHL : Exchange the H and L with the top of the Stack

iii) SBB
c Explain the following :-
i) Cross Assembler 03
02

1. Call an editor program and create a source file in assembly language

2. Call a Cross Assembler to Assemble the source file
3. Call a link program to generate the executable file
4. Execute the program
ii) Loader
d What is the function performed by a debugger?

e Explain the steps of 8085 microprocessor interrupt process.

f Write a short not on 8085 microprocessor vectored interrupts.

5. Attempt any three of the following: 15
a. Explain the internal structure of the Pentium Pro Processor.

The Pentium Pro is structured differently than earlier microprocessors. Early microprocessors
contained an execution unit and a bus interface unit with a small cache buffering the execution
unit for the bus interface unit. This structure was modified in later microprocessors, but the
modifications were just additional stages within the microprocessors. The Pentium architecture is
also a modification, but more significant than earlier microprocessors. Figure shows a
block diagram of the internal structure of the Pentium Pro microprocessor.
The system buses, which communicate to the memory and I/O, connect to an internal level
2 cache that is often on the main board in most other microprocessor systems. The level 2 cache
in the Pentium Pro is either 256K bytes or 512K bytes. The integration of the level 2 cache
speeds processing and reduces the number of components in a system.
The bus interface unit (BIU) controls the access to the system buses through the level 2
cache, as it does in most other microprocessors. Again, the difference is that the level 2 cache is
integrated. The BIU generates the memory address and control signals, and passes and fetches
data or instructions to either a level 1 data cache or a level 1 instruction cache. Each cache is 8K
bytes in size at present and may be made larger in future versions of the microprocessor. Earlier
versions of the Intel microprocessor contained a unified cache that held both instructions and
data. The implementation of separate caches improves performance because data-intensive
programs
no longer fill the cache with data.

b. List any five Pentium instructions and explain the function of any two.
Instruction Function
CMPXCHG8B Compare and exchange eight bytes
CPUID Return CPU identification code
RDTSC Read time-stamp counter
RDMSR Read model-specific register
WRMSR Write model-specific register
RSM Return from system management interrupt

The CMPXCHG8B instruction is an extension of the CMPXCHG instruction added to the

 80486 instruction set. The CMPXCHG8B instruction compares the 64-bit number stored in
EDX and EAX with the contents of a 64-bit memory location or register pair. For example, the
CMPXCHG8B DATA2 instruction compared the eight bytes stored in memory location DATA2
with the 64-bit number in EDX and EAX. If DATA2 equals EDX:EAX, the 64-bit number stored
in ECX:EBX is stored in memory location DATA2. If they are not equal, the contents of DATA2
are stored into EDX:EAX. Note that the zero flag bit indicates that the contents of EDX:EAX
were equal or not equal to DATA2.

The CPUID instruction reads the CPU identification code and other information from
the Pentium. To use the CPUID instruction, first load EAX with the input value
and then execute CPUID. If a 0 is placed in EAX before executing the CPUID instruction, the
microprocessor returns
the vendor identification in EBX, EDX, and EBX. For example, the Intel Pentium
returns“GenuineIntel” in ASCII code with the “Genu” in the EBX, “ineI’ in EDX, and “ntel” in
ECX. TheEDX register returns information if EAX is loaded with a 1 before executing the CPUID
instruction.

The RDTSC instruction reads the time-stamp counter into EDX:EAX. The time-stamp
counter counts CPU clocks from the time the microprocessor is reset, where the time-stamp counter
is initialized to an unknown count. Because this is a 64-bit count, a 1GHz microprocessor can
accumulate a count of over 580 years before the time-stamp counter rolls over. This instruction
functions only in real mode or privilege level 0 in protected mode.

The RDMSR and WRMSR instructions allow the model-specific registers to be read or
written. The model-specific registers are unique to the Pentium and are used to trace, check
performance, test, and check for machine errors. Both instructions use ECX to convey the register
number to the microprocessor and use EDX:EAX for the 64-bit-wide read or write. Note that the
register addresses are 0H–13H. See Table 18–5 for a list of the Pentium model-specific registers and
their contents. As with the RDTSC instruction, these model-specific registers operate in the
real or privilege level 0 of protected mode.

c. Explain the CPUID instruction in Pentium II.

CPUID Instruction
Table below lists the values passed between the Pentium II and the CPUID instruction. These are
changed from earlier versions of the Pentium microprocessor. The version information returned
after executing the CPUID instruction with a logic 0 in EAX is returned in EAX. The family ID is
returned in bits 8 to 11; the model ID is returned in bits 4 to 7. The stepping ID is returned in bits 0
to 3. For the Pentium II, the model number is 6 and the family ID is a 3. The stepping number refers
to an update number—the higher the stepping
number, the newer the version. The features are indicated in the EDX register after executing the
CPUID instruction with a zero in EAX. Only two new features are returned in EDX for the Pentium
II. Bit position 11
indicates whether the microprocessor supports the two new fast call instructions, SYSENTER and
SYSEXIT. Bit position 23 indicates whether the microprocessor supports the MMX instruction set.
Bit 16 indicates whether the microprocessor supports the page attribute table or PAT. Bit 17
indicates whether the microprocessor supports the page size
TABLE CPUID instruction for the Pentium II.
Input EAX Output Register Contents
0 EAX Maximum allowed input to EAX for CPUID
0 EBX “uneG”
0 ECX “Inei”
0 EDX “letn”
1 EAX Version number
1 EDX Feature information
2 EAX Cache data
2 EBX Cache data
2 ECX Cache data
2 EDX Cache data

Extension found with the Pentium Pro and Pentium II microprocessors. The page size extension
allows memory above 4G through 64G to be addressed. Finally, bit 24 indicates whether the fast
floating-point save (FXSAVE) and restore (FXRSTOR) instructions are implemented.
d. Compare Core i3, i5 and i7 processors.
e. What are the features of the SPARC Architecture?
SPARC includes the following principal features:
 .A linear, 32-bit address space.
 . Few and simple instruction formats — All instructions are 32 bits wide, and
are aligned on 32-bit boundaries in memory. There are only three basic
instruction formats, and they feature uniform placement of opcode and register
address fields. Only load and store instructions access memory and I/O.
 . Few addressing modes — A memory address is given by either “register +
register” or “register+immediate.”
 . Triadic register addresses— Most instructions operate on two register
operands (or one register and a constant), and place the result in a third
register.
 . A large “windowed” register file — At any one instant, a program sees 8
global integer registers plus a 24-register window into a larger register file.
 The windowed registers can be described as a cache of procedure arguments,
local values, and return addresses.
 . A separate floating-point register file — configurable by software into 32
single-precision (32-bit), 16 double-precision (64-bit), 8 quad-precision
registers (128-bit), or a mixture thereof.
 . Delayed control transfer— The processor always fetches the next instruction
after a delayed control-transfer instruction. It either executes it or not,
depending on the control-transfer instruction’s “annul” bit.
 . Fast trap handlers— Traps are vectored through a table, and cause allocation
of a fresh register window in the register file.
 . Tagged instructions — The tagged add/subtract instructions assume that the
two least-significant bits of the operands are tag bits.

f. What are the various data format in the SPARC Architecture?

The SPARC architecture recognizes three fundamental data formats (or types):
. Signed Integer— 8, 16, 32, and 64 bits

. Unsigned Integer— 8, 16, 32, and 64 bits

. Floating-Point — 32, 64, and 128 bits

The format widths are defined as:

. Byte — 8 bits

. Halfword— 16 bits

. Word/Singleword — 32 bits

. Tagged Word— 32 bits (30-bit value plus 2 tag bits)

. Doubleword— 64 bits

. Quadword— 128 bits

The Signed Integer formats encode two’s-complement whole numbers. The

Unsigned Integer formats are general-purpose in that they do not encode any particular
data type; they can represent a whole number, string, fraction, boolean
value, etc. The Floating-Point formats conform to the IEEE Standard for Binary
Floating-Point Arithmetic, ANSI/IEEE Standard 754-1985. The Tagged formats
define a word in which the least-significant two bits are treated as tag bits.
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