Q-> What is the difference between $random and $urandom?

Ans:-

-> $random returns a signed 32-bit integer; $urandom and $urandom_range return
unsigned 32-bit integers.

-> The random number generator for $random is specified in IEEE Std 1800-2012. With
the same seed you will get exactly the same sequence of random numbers in any
SystemVerilog simulator.
That is not the case for $urandom and $urandom_range, where the design of the
random number generator is up to the EDA vendor.

-> Each thread has its own random number generator for $urandom and $urandom_range,
whereas there is only one random number generator for $random shared between all
threads
(ie only one for the entire simulation).
This is really important, because having separate random number generators for each
thread helps you simulation improve a property called random stability.

Q-> What is expect statements in assertions ?

Ans:-

-> An expect statement is very similar to an assert statement, but it must occur
within a procedural block (including initial or always blocks, tasks and
functions), and is
used to block the execution until the property succeeds.

task mytask;
...
if (expr1)
expect (my_property)
pass_block();
else // associated with the 'expect',
// not with the 'if'
fail_block();
...
endtask

Unlike an assert statement, an expect statement starts only a single thread of

evaluation. It comes out of the blocking mode only if the property succeeds or
fails.

Q-> The 'bind' Directive

Ans:- It is sometimes desirable to physically separate a property (which is

primarily a verification entity) from a design (whose primary objective is to
translate itself to a working silicon).

-> A bind directive can tie them together even though they are in two separate
files.

-> A bind directive can tie a module, an interface or a program instance with a
module or module instance and can be specified in a module, an interface, or a
compilation-unit scope.
-> A property can be specified within a module differnt from the design module.
These modules can then be tied together using a bind directive. The following
example shows how to do it.

Let us assume design_module_1 is the instance of a design module design_module.

 bind design_module prop_module prop_module_1 (arg1, arg2, ...);
bind design_module_1 prop_module prop_module_1 (arg1, arg2, ...);

In the first case, all instances of the design_module get the properties defined
within prop_module_1 instance of prop_module. In the second case,
only instance design_module_1 receives these properties.

Q-> What is System Verilog DPI (Direct Programming Interface)

Ans:- Direct programming interface or DPI is a interface between the System Verilog
and the C language. It allows you to call the sytem verilog functions in C language
and Vice Versa

-> you can reuse your existing c code with system verilog

Sytem Verilog :

module hello();
import "DPI-C" function void print_hello();

initial
begin
print_hello();
end

endmodule

C :

===

void print_hello() {
printf("Hello World From C \n");
}

How to run :

Step 1. Compile your C code

gcc -shared -o hello.so hello.c
Step 2. Compile your SV code
vlog -sv hello.sv
Step 3. link and load
vsim -c hello -sv_lib hello
Step 4. Run
VSIM> run -all

output :
VSIM 1> run -all
# Hello World From C
# ** Note: $finish : hello.sv(7)
# Time: 0 ns Iteration: 0 Instance: /hello

GCC option :

-shared

Produce a shared object which can then be linked with other objects to form an
executable.

Explanation :

->In the above example we are calling a C funtion print_hello() in system

verilog code. Following are the points to note :

we need to import the C function in system verilog with statement 'import "DPI-
C"'
we should have actual funtion implementiaon in C file
Call the C funtion in your system verilog code
remember to link library at loading time
import declaration can occur anywhere where a SystemVerilog task or function
definition is allowed

NOTE : C function should not comsume time like the system verilog functions

Imported Functions :

Functions implemented in foreign language can be called in system verilog, such

functions are called Imported functions

Exported Functions :

System verilog functions that are called from foeign language should appear in
exported function declerations

Q-> What are system tasks ?

Ans:- Their names begin with a dollar sign ($). The synthesis tools parse and
ignore system functions.
-> System Task are:-
-> $display, $strobe, $monitor
-> $time, $stime, $realtime
-> These return the current simulation time as a 64-bit integer, a 32-bit
integer, and a real number, respectively.
-> $reset, $stop, $finish
-> $reset resets the simulation back to time 0; $stop halts the simulator and
puts it in interactive mode where the user can enter commands; $finish exits the
simulator back to the operating system.
-> $scope, $showscope
-> $scope(hierarchy_name) sets the current hierarchical scope to
hierarchy_name. $showscopes(n) lists all modules, tasks and block names in (and
below, if n is set to 1) the current scope.
-> $random
->Generates a random integer every time it is called. If the sequence is to be
repeatable, the first time one invokes random giving it a numerical argument (a
seed).
Otherwise the seed is derived from the computer clock.
-> $dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall
->These can dump variable changes to a simulation viewer like Debussy. The dump
files are capable of dumping all the variables in a simulation. This is convenient
for debugging, but can be very slow.
-> $fopen, $fdisplay, $fstrobe $fmonitor and $fwrite :- These commands write more
selectively to files.
-> $fopen opens an output file and gives the open file a handle for use by the
other commands.
-> $fclose closes the file and lets other programs access it.
-> $fdisplay and $fwrite write formatted data to a file whenever they are
executed. They are the same except $fdisplay inserts a new line after every
execution and $write does not.
-> $strobe also writes to a file when executed, but it waits until all other
operations in the time step are complete before writing. Thus initial #1 a=1; b=0;
$fstrobe(hand1, a,b); b=1; will write write 1 1 for a and b.
-> $monitor writes to a file whenever any of its arguments changes.

Q-> What is systemverilog assertion binding and advantages of it ?

Ans:- // Need to discuss with another member

Q-> What are parameterized classes ?

Ans:- Please add to ans from our local system

Q-> How to generate array without randomization ?

Ans:- Please ans this question
Q-> What is modport and explain usage of it?
Ans:- Modports in SystemVerilog are used to restrict interface access within a
interface. The keyword modport indicates that the directions are declared as if
inside the module.

->Modports can have

input : Ports that need to be input.
output : Ports that need to be output.
inout : Ports that need to be inout
ref : Ports that need to be ref.

Adding modports to an interface does not require that any of the modports be used
when the interface is used. If no modport is specified in the module header or in
the port
connection, then all the nets and variables in the interface are accessible with
direction inout or ref, Below example shows this in greater detail.
Q-> What is clocking block? // I need to read cummings paper for the same
Ans:- Specifying the timing and synchronisation requirements of a design in a
testbench.
A clocking block is a set of signals synchronised on a particular clock. It
basically separates the time related details from the structural, functional and
procedural
elements of a testbench. It helps the designer develop testbenches in terms of
transactions and cycles. Clocking blocks can only be declared inside a module,
interface or program.

Q-> What is the difference between clocking block and modport?

Ans:- These are two distinct constructs, but there is a slight convenience when
used together.
->A modport is like a sub-interface to an interface connection. Without
modports, interface connections have universal access to all things defined in
interface.
Modports define a subset of signals for access, as well as their direction. You
can think of a modport the same way a module provides a port declaration list as
its
"boundary" for connections. An SV interface can have multiple "boundaries",
each defined as a separate modport.
A clocking block groups signals and creates a set of corresponding signals that
are used for sampling and driving values synchronous to a particular clock.
You define the signals to be sampled as 'inputs' and the signals to drive as
'outputs'. When you put a clocking block in a modport, you get access to all the
corresponding
clocking block signals as inputs or outputs - there's no need to list them
individually.
Q-> What are the different types of verification approaches ?
Ans:- Need to read Ramdas Book / Chris Sper Book

Q-> What is the purpose of a testbench ?

Ans:- A testbench allows us to verify the functionality of a design through
simulations. It is a container where the design is placed and driven with different
input stimulus.
-> Generate different types of input stimulus
-> Drive the design inputs with the generated stimulus
-> Allow the design to process input and provide an output
-> Check the output with expected behavior to find functional defects
-> If a functional bug is found, then change the design to fix the bug
-> Perform the above steps until there are no more functional defects

Q-> What are the basic testbench components?

Ans:-
Component Description
Generator Generates different input stimulus to be driven to DUT
Interface Contains design signals that can be driven or monitored
Driver Drives the generated stimulus to the design
Monitor Monitor the design input-output ports to capture design activity
Scoreboard Checks output from the design with expected behavior
Environment Contains all the verification components mentioned above
Test Contains the environment that can be tweaked with different
configuration settings

Q-> What are the different layers of layered architecture?

Ans:- Need to read Ramdas Book / Chris Sper Book

Q-> What is the difference between $rose and @ (posedge) ?

Ans:- There is no such thing as $posdege(a). There is @(posedge a). This is an
event control that blocks a process waiting for an update to 'a' where the LSB goes
from zero to non-zero.
$rose(a) is a sampled function that must be used in the context of some other
synchronous event. It returns true if the LSB of 'a' was zero in the previous cycle
and is now
1 ub the current cycle. Otherwise it returns false.

Q-> Write an assertion for glitch detection.

Ans:- Use $stable
ex:- assert property (@(posedge clk) enable == 0 |=> $stable(data)); OR @(posedge
d_in) $sample(d_in) == 0 @(negedge d_in) $sample(d_in) == 1

Q-> What is the use of extern ?

Ans:- Class definitions can become very long with a lot of lines between class and
endclass. This makes it difficult to understand what all functions and variables
exist
within the class because each function and task occupy quite a lot of lines.
Using extern qualifier in method declaration indicates that the implementation is
done outside the body of this class.

Q-> What is scope randomization ?

Ans:- // Need to read randomization chapter
-> The scope randomize function, std::randomize(), enables users to randomize
data in the current scope without the need to define a class or instantiate a class
object.
Syntax:- scope_randomize ::= [ std:: ] randomize ( [ variable_identifier_list ] ) [
with constraint_block ]
Arguments to this function specify the variables that are to be assigned random
values.
ex:-
module m;
int i;
byte j;
int ok;

initial begin
ok = std::randomize(i,j);
...
end
endmodule

Note:- The std::randomize() function returns 1 if it successfully sets all the

random variables to valid values; otherwise, it returns 0. If it is called without
arguments, then returns status.

-> Randomization of Scope Variables std::randomize() with Constraints

->The user can define constraints to generated random variables using with
form.

ex:-
int x;

task gen_t(int min,max);

int ok;
ok = std::randomize(x) with {x > min; x < max;}
endtask

Q-> Static and Automatic Lifetime of Variable and Methods

Ans:- Static : For a variable static lifetime is , its memory never de-allocated
until simulation ends.
Automatic : For a variable Automatic lifetime is , it is stack storage of variable
(for multiple entry to a task, function or block, it will have stack storage) and
its memory
will be de-allocated once execution of that method or block is over.

->Default Lifetime of variable :

1. Class variable : Automatic
2. Method variable : Automatic
3. Local variable of loop : Automatic
4. Module or Program block variable : Static
5. Variable declared in initial of always block : Static

-> Class Variable:- Default all variable and class method are automatic. Each
instance of class will have its own copy of variable. If it is declared as static
only one copy will
be created and all instance will use that copy. Static variable can be accessed
with out creating object of class. It can be accessed with out making object and by
scope resolution operation.

-> Method Variable:- Default lifetime of variable declared in method (Function and
Task) is automatic. Scope of the variable is limited to execution of that method.
Its lifetime is automatic as its memory will be deallocated when the task and
function gets over.
-> Loop Variable:- Default local variable of loop is automatic. Its scope is
limited to execution of call and its memory deallocated when execution of loop is
over.

-> Module or Program Block:- Default lifetime of variable is Static for Module and
Program. They will have memory till end of simulation and its scope will be limited
to that module or program called.

Default lifetime of Method :

1. Method in module or program block : Static
2. Method in class : Automatic

-> Method in module and program block:- Default life time of method in program and
module block is static. This is to keep it same with existing verilog reference.
So for module function lifetime is static. Its variable and return type is static.
So if we call recursive function, it will not create multiple stack entry for call
of function and stack memory for internal variable.

Q-> Can we write systemverilog assertions in class ?

Ans:- Immediate assertions can be placed anywhere a procedural statement is
allowed.
->Concurrent assertions can be placed anywhere you are allowed to put an initial or
always construct, and with some restrictions, within an initial or always
construct.
->Concurrent assertions are limited by the fact that most implementations
synthesize them into state machines and the compilers need to statically know about
each instance of an assertion before simulation starts.
->Class instances (objects) are dynamically constructed during simulation.

Q-> What is the difference between associative and dynamic array?

Ans:- A dynamic array gets created with a variable size and stays that size in a
contiguous block of memory.
Its elements are indexed starting with integer 0. This is most efficient way of
accessing a block of memory, especially when you need to access to the entire
array.

-> Each element of an associative array gets allocated as you access them. So there
is a lot more overhead for the creation of an associative array versus the same
size dynamic array. And since the elements of an associative array are not always
in a contiguous block of memory, there is overhead in accessing each element. (i.e.
have to check if the element is allocated, and then where is it located)

-> The benefit of an associative array is since each element gets allocated
individually, you don't need to allocate a contiguous set of array elements.
This is useful when you only plan to access a relatively few (sparse) elements of
an memory address space.
Another benefit is that you don't have to use an integer as an index to each
element. You can associate any type of key, like a string to access each element.

Q-> What are the advantages of cross coverage?

Ans:-

Q-> What are in line constraints?

Ans:- // Need to read randomization chapter
-> Constraints will be written inside the class. inline constraint allows user to
add extra constraints to an existing constraints written inside the class.
Inline constraints will be written outside the class i.e along with the randomize
method call.
Q-> What are constraints? Is all constraints are bidirectional?
Ans:- // Need to read randomization chapter

Q-> What is randomization and what can be

Ans:- // Need to read randomization chapter

Q-> What is input skew and output skew in clocking block ? // I need to short
answer for the same
Ans:- A skew number for an input denotes when that input is sampled before the
clocking event (such as posedge or negedge) occurs. For an output, it is just the
opposite -
it denotes when an output is synchronized and sent after the clocking event.

-> 1step
A 1step is a special unit of time. It denotes a negative time delay from the
edge of a clock when all inputs are steady and ready to be sampled.
In terms of scheduling semantics, a 1step unit denotes the Postponed region
immediately before a clock edge.

-> Default input and output skews

The default skew statement in the above example is optional. A clocking block
without this statement (as shown below) is still legal.

clocking clock1 @(posedge clk1);

input a1, a2;
output b1;
endclocking

In this case, the default input skew is 1step and the default output skew is 0.

-> Overwriting default skews

Even if there is a default statement for skews in a clocking block, it can be

overwritten later in the block.

For example, the example below overwrites the default input skew for signal a1 (to
1step) and output b1 (to 5 ns), but the input skew for a2 remains unchanged at 2
ns.

clocking clock1 @(posedge clk1);

default input #2ns output #3ns;
input #1step a1;
input a2;
output #5ns b1;
endclocking

-> Skew value of #0

A skew value of #0 changes the way input values are sampled and output values are
synchronized, even though both will still be done at the simulation time when a
clock event occurs.
A skew value of #0 for any input means that the input will be sampled at the
Observed region. An output skew value of #0 indicates that the output will be
synchronized out in the Non-blocking assignment (NBA) region.
-> Parameterized skew value

Skew value (or values) in a clocking block is parameterizable. The following

exampleshows this.

clocking clock1 @(posedge clk1);

parameter INPUT_SKEW = 2;
parameter OUTPUT_SKEW = 3;
default input #INPUT_SKEW output #OUTPUT_SKEW;
input #1step a1;
input a2;
output #5ns b1;
endclocking

Q-> What is the advantage of seed in randomization?

Ans:- // Need to read book for randomization

Q-> What are illegal bins? Is it good to use it and why?

Ans:- Illegal bins are bins that would not want to came in our test scenario. It
should never hit illegal_bins. If it does, your testbench or design has a problem
and all coverage is meaningless.
I would avoid using illegal_bins as a checker because unlike an assertion or a UVM
error, there is no facility to control reporting of illegal_bin errors.

Q-> When you will say that verification is completed?

Ans:- Its continue process of fulfilling the milestone of the verification plan in
the cycle of product release.
(our verification is done, if you met all your goals defined in your verification
plan.)

Q-> What is the importance of coverage in systemverilog verification?

Ans:-

Q-> What is coverage and what are different types?

Ans:- Coverage is used to check whether the Test-bench has satisfactory exercised
the design or not. There are two types of coverage
1. Code coverage 2. Functional coverage

Q-> What is constraint solve-before?

Ans:-

Q-> What is inheritance and polymorphism?

Ans:- // Need to Update

Q-> What is casting?

Ans:- Conversion of one datatype to another datatype.

Q-> What is difference between Mailbox and Queue?

Ans:- Apparently there is not difference between queue and mailbox. Both can store
data (push or put) and we can get stored data from is (pop and get.)
Difference lies when there is multiple thread (or process), putting or getting
element to or from queue.
For a single thread or process there is no difference between queue and mailbox.

I will show you with example below, how it affects.

Mailbox is special class (enhanced functionality of queue) in std package of system

verilog. It can be bounded or unbounded. Bounded means size of mailbox is fixed,
you can not put more element more than its defined size.

mailbox mbx = new(4);

Above mailbox can only store 4 element. If we try to put more element then 4 it
will block the method until space is created.

Bounded Queue : Can we make that??? Yes we can mimic it as below.

task put(input int data);

wait(q.size < 4); // test
q.push_back(data); // set
endtask
task get(output int data);
wait(q.size > 0); // test
q.pop_front(data); // set

endtask

Here we only push element if size is less than 4. If it is single thread doing this
there is no difference (except we have to add wait statement).

But what mailbox is provide is : above test and set operation are performed
atomically (uninterrupted). While for queue it is two different process. (test and
set).

-> There are two problem using that queue approach.

1. The first is that when there are multiple threads waiting on the size of the
queue to change, there is no guaranteed ordering which thread will wake up and
proceed when the
condition is satisfied. Mailboxes/semaphores guarantee that the order that the
threads suspend is the same as the order they wake up (FIFO order First In/First
Out).

2. The other problem is there is no guaranteed ordering of statements between two

or more concurrently running threads.
It's possible for multiple threads to wake up when the queue size changes so that
either q.size < 4 is true for a put(), or q.size > 0 for a get().
All the threads could execute the test and succeed, then all the threads do their
set operation when only one operation should have been allowed.
Mailboxes/semaphores guarantee that put() and get() act atomically so that no other
thread interrupt the test and set operation. So only one thread will succeed in the
put() or get().

Q-> Why always blocks are not allowed in program block?

Ans:- The program block came from the Vera verification language that was donated
to SystemVerilog. In Vera, a program was a single procedure that represented the
"test".
Your test was started at time 0 and when the test terminated, the program
terminated the simulation.
If you needed multiple test threads, you either had to use the fork statement to
start it, or use multiple programs. When the last program terminated, the
simulation terminated.

As part of the integration with SystemVerilog, the program was turned into a
module-like construct with ports and initial blocks are now used to start the test
procedure.
Because an always block never terminates, it was kept out of the program block so
the concept of test termination would still be there.

Today, most people do not utilize this termination feature because the OVM/UVM have
their own test termination mechanisms.
The program block is no longer a necessary feature of the language other than to
help people converting over from Vera to SystemVerilog.

Another Ans:- In a design, an always block might trigger on every positive edge of
a clock from the start of simulation.
A test-bench, on the other hand, goes through initialization, drive and respond to
design activity, and then completes.
When the last initial block completes, simulation implicitly ends just as if you
had executed $finish.
If you had an always block, it would never stop, so you would have to explicitly
call $exit to signal that the program block completed.

Q-> How can you get an assertion pass and fail in the same time slot?
Ans:-

Q-> What is the difference between task and function in class and Module?
Ans:-

Q-> Identify what could be wrong if following function is called in SystemVerilog

constraint as below?
Ans:-

class constraint_container;
rand int unsigned a, b, c;

function int unsigned get_a();

return a;
endfunction

function int unsigned value_of(int unsigned value);

return value;
endfunction

constraint a_constraint {
a == 5;
// I expect "b" to be equal to "a", but, surprise, surprise...
b == get_a();
// I expect "c" will be equal to "a"
c == value_of(a);
}
endclass

module top;
initial begin
automatic constraint_container cc_inst = new();
void'(cc_inst.randomize());
$display($sformatf("a: %0d, b: %0d, c: %0d", cc_inst.a, cc_inst.b, cc_inst.c));
end
endmodule

At first glance one would guess that all three fields will be 5, but one will get
instead:

OUTPUT:
a: 5, b: 0, c: 5

Gotcha: regardless of the seed, b will always be equal to 0!

It looks like get_a() is evaluated before the generation, when a is 0.

SystemVerilog IEEE 1800-2012 standard, chapter “18.5.12 Functions in constraints”:

-> Functions shall be called before constraints are solved, and their return
values shall be treated as state variables.
-> Function calls in active constraints are executed an unspecified number of
times (at least once) in an unspecified order.

-> The conclusion is that functions used by constraints should compute the result
based ONLY on function’s arguments and NOT on class members.

Q-> What is the Difference between param and typedef?

Ans:-

Q-> How to check if any bit of the expression is X or Z?

Ans:- Using $isunknown operator

Q-> What is the scope of local and private variables ?

ANS:- Inside the class and module only. In case of private (variable declared as
protected cannot be accessed outside the class) you can use private member in
extended class but not in module instantiation for example:-

class parent_class;
protected bit [31:0] tmp_addr;

function new(bit [31:0] r_addr);

tmp_addr = r_addr + 10;
endfunction

function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass

class child_class extends parent_class;

function new(bit [31:0] r_addr);
super.new(r_addr);
endfunction

function void incr_addr();

tmp_addr++;
endfunction
endclass

// module
module encapsulation;
initial begin
child_class c_c = new(10);

c_c.incr_addr(); //Accessing protected variable in extended class

c_c.display();
end
endmodule

Q-> What is the concept of forward declaration of a class in SystemVerilog?

Ans:- A forward declaration is a declaration of a object which the programmer has
not yet given a complete definition. However, more often it is taken to refer to
the actual
use of an entity before any declaration. The SystemVerilog language supports the
typedef class construct for forward referencing of a class declaration.
This allows for the compiler to read a file from beginning to end without concern
for the positioning of the class declaration.
EXAMPLE:
class Y ;
X x; // refers to Class X, which is not yet defined
endclass

class X;
int i;
endclass

RESULT

Error : Class X is not defined

When the compiler encounters the handle x of class type X referred to in class Y,
it does not yet know the definition for class X since it is later in the file.
Thus, compilation fails.
To rectify this situation, typedef is used to forward reference the class
declaration.

EXAMPLE:
typedef class X;
class Y ;
X x; // refers to Class X, which is not yet defined
endclass

class X;
int i;
endclass

The typedef of class X allows the compiler to process Y before X is fully defined.
Note that typedef cannot be used to forward reference a class definition in another
file.
This must be done using the inclusion of a header file.

Q-> What is Circular Dependency?

Ans:- A Circular dependency is a situation which can occur in programming languages
wherein the definition of an object includes the object itself. One famous example
is Linked List.

EXAMPLE:
class Y ;
int i;
Y y; // refers to Class Y, which is not yet defined
endclass

As you seen, there is a compilation error. To avoid this situation, typedef is used
to forward reference the class declaration and this circular dependency problem can
be avoided.

Q-> What is pure?

Ans:- a virtual method may or may not be overridden in the derived classes. It
means, it is not necessary for a derived class to override a virtual method.
But there are times when a base class is not able to define anything meaningful for
the virtual method in that case every derived class must provide its own definition
of the that method.
A pure virtual method is a virtual method that you want to force derived classes to
override.
If a class has any unoverridden pure virtuals, it is an "abstract class" and you
can't create objects of that type.
" pure virtual function " or " pure virtual task " declaration is supposed to
represent the fact that the method has no implementation.
There are two major differences between a virtual and a pure virtual function
-> There CAN'T be a definition of the pure virtual function in the base class.
-> There MUST be a definition of the pure virtual function in the derived
class.
ex:- class Base;
pure virtual task disp();
end class

program main
initial begin
Base B;
B = new();
B.disp();
end
endprogram

RESULT:- Error: pure virtual task disp(); must be overridden in derived class

Q-> What are the main regions inside a SystemVerilog simulation time step?
Ans:- Read cummings paper

Q-> Is it possible to override a constraint defined in the base class in a derived

class and if so how?
Ans:- Read 18.5.2 Constraint inheritance in the 1800-2009 LRM

Q-> How can we disable or enable constraints selectively in a class?

Ans:- Constraints can be enabled or disabled by constraint_mode().
All constraints are by default enabled and will be considered by the SystemVerilog
constraint solver during randomization. A disabled constraint is not considered
during randomization.
Syntax:- constraint_mode() can be called both as a task and as a function.
ex:-
class Fruits;
rand bit[3:0] num; // Declare a 4-bit variable that can be randomized

constraint c_num { num > 4; // Constraint is by default enabled, and applied

num < 9; }; // during randomization giving num a value
between 4 and 9
endclass

module tb;
initial begin
Fruits f = new ();

// 1. Print value of num before randomization

$display ("Before randomization num = %0d", f.num);

// 2. Call "constraint_mode" as a function, the return type gives status of

constraint
if (f.c_num.constraint_mode ())
 $display ("Constraint c_num is enabled");
else
$display ("Constraint c_num is disabled");

// 3. Randomize the class object

f.randomize ();

// 4. Display value of num after randomization

$display ("After randomization num = %0d", f.num);
end
endmodule
RESULT:-
Before randomization num = 0
Constraint c_num is active
After randomization num = 8
ncsim: *W,RNQUIE: Simulation is complete.
-> Actually now have 4 different choices for doing this.

1. Override with an empty constraint, and add new constraint. This runs the
risk of having a typo and winding up with both constraints active.
2. Override with a replacement constraint. This shows your intent with the
most clarity.
3. Disable the base constraint using constraint_mode in the extended
constructor. This allows you to turn it back on later if needed in the sequence, or
an extended sequence.
4. Use a soft constraint. This allows you to add new constraints, and only
removes the existing soft constraint if it conflicts.

Q-> Given a Packet class with following constraints, how can we generate a packet
object with address value greater than 200?
Ans:-

Q-> Write constraints to generate elements of a dynamic array(abc as shown in code

below)such that each element of the array is less than 10 and the array size is
less than 10.
Ans:-

Q-> What is the difference between hard and soft constraints?

Ans: -

Q-> What are Semaphores? When are they used?

Ans:-

Q-> What are Mailboxes? What are the uses of a Mailbox?

Ans: -

Q-> What is an “event” in SystemVerilog? How do we trigger an “event” in

SystemVerilog?
Ans:-

Q-> How can we merge two events in SystemVerilog?

Ans:-

Q-> There are two task and both are under fork and join and second task will
execute only when first task finishes its work, how can it be done ?
Ans:- This can be achieved though semaphore, once first task finises it work it
will release its key and other task will pick it up and continue its execution.

Q-> What are inbuilt method of semaphore ?

Ans:- new() – Create a semaphore with a specified number of keys
get() – Obtain one or more keys from the bucket, it is blocking
put() – Return one or more keys into the bucket
try_get() – Try to obtain one or more keys without blocking

Q-> How do we create semaphore ?

Ans:- semaphore <semaphore_name>; <semaphore_name> = new(<numbers_of_keys>);

Q-> What are method of mailbox ?

Ans:-
new(); Create a mailbox
put(); Place a message in a mailbox
try_put(); Try to place a message in a mailbox without blocking
get(); / peek(); Retrieve a message from a mailbox
try_get(); / try_peek(); Try to retrieve a message from a mailbox without
blocking
num(); Returns the number of messages in the mailbox

Q-> What is bounded and unbounded mailbox ?

Ans:- bounded mailbox are with limited size and size is provided by user, unbounded
mail box doesn’t have size constraints.