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This document provides information about the processor, memory system, and cache hierarchy for a computer system. It asks four questions about average memory access times and overall CPI. The processor runs at 1.1 GHz with a base CPI of 1.35. The memory hierarchy includes split L1 caches, a 512KB L2 cache, and 128-bit main memory. The average memory access time is 0.84045 ns for instructions, 2.101 ns for data reads, and 2.101 ns for data writes. The overall CPI including memory accesses is 2.9673.

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317 views2 pages

2

This document provides information about the processor, memory system, and cache hierarchy for a computer system. It asks four questions about average memory access times and overall CPI. The processor runs at 1.1 GHz with a base CPI of 1.35. The memory hierarchy includes split L1 caches, a 512KB L2 cache, and 128-bit main memory. The average memory access time is 0.84045 ns for instructions, 2.101 ns for data reads, and 2.101 ns for data writes. The overall CPI including memory accesses is 2.9673.

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528 acm
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Exercise B.

5 a, b, c, d (page B-63)
You are building a system around a processor with in-order execution that runs at 1.1
GHz and has a CPI of 1.35 excluding memory accesses. The only instructions that
read or write data from memory are loads (20% of all instructions) and stores (10%
of all instructions).
The memory system for this computer is composed of a split L1 cache that imposes
no penalty on hits. Both the I- cache and D-cache are direct-mapped and hold 32 KB
each. The I-cache has a 2% miss rate and 32-byte blocks, and the D-cache is write-
through with a 5% miss rate and 16-byte blocks. There is a write buffer on the D-
cache that eliminates stalls for 95% of all writes.
The 512 KB write-back, unified L2 cache has 64-byte blocks and an access time of 15
ns. It is connected to the L1 cache by a 128-bit data bus that runs at 266 MHz and
can transfer one 128-bit word per bus cycle. Of all memory references sent to the L2
cache in this system, 80% are satisfied without going to main memory. Also, 50% of
all blocks replaced are dirty.
The 128-bit-wide main memory has an access latency of 60 ns, after which any
number of bus words may be transferred at the rate of one per cycle on the 128-bit-
wide 133 MHz main memory bus.
a. What is the average memory access time for instruction accesses?
A:
First, compute the value of L2 miss penalty.
L2 miss penalty = (read a block from main memory) + 0.5 x (write back a dirty block
to memory)
Bus cycle = 1/133 MHz = 7.518 ns.
Transfer rate of memory bus:
128 bits / bus cycle
= 16 bytes / 7.518 ns
= 2.128 bytes / ns
Time for transferring a L2 cache block is 64/2.128 = 30.075 ns
Read a block from main memory = write back a dirty block to memory = 60 + 30.075
= 90.075 ns
L2 miss penalty = 90.075 + 0.5 x 90.075 = 135.1125 ns

Average memory access time = L1 hit time + L1 miss rate x ((L2 hit time) + L2 miss
rate x (L2 miss penalty))
= 0 + 0.02 x (15 + 0.2 x 135.1125)
=0.84045 ns

1
b. What is the average memory access time for data reads?
A:
The miss rate of L1 cache data reads is 5%.
Average memory access time = L1 hit time + L1 miss rate x ((L2 hit time) + L2 miss
rate x (L2 miss penalty))
= 0 + 0.05 x (15 + 0.2 x 135.1125)
=2.101 ns
c. What is the average memory access time for data writes?
A:
The hit rate of L2 cache is 80%.
The time spent on write buffer = (L2 hit time) + 0.2 x (L2 miss penalty)
= 15 + 0.2 x 135.1125
=42.0225 ns
We have a write buffer on the D-cache that eliminates stalls for 95% of all writes.
Thus, Average memory access time = L1 hit time + 0.05 x (write buffer time)
=0.05x(42.0225)
=2.101 ns
d. What is the overall CPI, including memory accesses?
A:
CPI = CPI excluding memory accesses + instruction cache CPI +data cache load CPI +
data cache store CPI
0.84045 ns = 0.924 clock cycles
2.101 ns = 2.311 clock cycles
CPI = 1.35 + 0.924 + 0.2 x 2.311 + 0.1 x 2.311 = 2.9673

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