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This Study Resource Was: Introduction To Digital Logic Eecs/Cse 31L

This document provides instructions for Assignment 3, which involves implementing a 32-bit arithmetic logic unit (ALU) in VHDL at both the structural and behavioral levels. Students are asked to develop a 32-bit ALU using 1-bit ALU components from a previous assignment. The ALU should perform arithmetic and logic functions on two 32-bit inputs based on a 3-bit operation selection and a mode selection. Students must submit a design report, waveform snapshots demonstrating each function, and VHDL code for the 32-bit ALU.

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17 views2 pages

This Study Resource Was: Introduction To Digital Logic Eecs/Cse 31L

This document provides instructions for Assignment 3, which involves implementing a 32-bit arithmetic logic unit (ALU) in VHDL at both the structural and behavioral levels. Students are asked to develop a 32-bit ALU using 1-bit ALU components from a previous assignment. The ALU should perform arithmetic and logic functions on two 32-bit inputs based on a 3-bit operation selection and a mode selection. Students must submit a design report, waveform snapshots demonstrating each function, and VHDL code for the 32-bit ALU.

Uploaded by

Nubia Diaz
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
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Introduction to Digital Logic

EECS/CSE 31L

Assignment 3

EECS Department
Henry Samueli School of Engineering
University of California, Irvine

February, 2, 2015

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Due on Monday 2/9/2015 5:00pm. Note: this is a one-week assignment

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Implementing a 32-bit ALU [100 points + 5 bonus points]
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The goal of this assignment is to practice multi-component logic design in VHDL and learn how to build
a 32-bit Arithmetic and Logic Unit (ALU) at both structural and behavioral levels.
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1.1 Assignment Description


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The objective of this project is to assess your understanding of how to implement a complicated combi-
national hardware block using the codes you have developed in the last assignment. In this assignment
you are supposed to implement a 32-bit ALU using 1-bit ALU component you have already developed
in Assignment-2. Also consider using GENERATE statement for instantiating 1-bit ALU components.
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In this assignment you are supposed to develop your own testbench for 32-bit ALU verification.
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1.1.1 ALU Entity

Code 1: Sample entity of 32-bit ALU in VHDL


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ENTITY alu_32bit IS
PORT (
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A : IN S T D _ L O G I C _ V E C T O R (31 DOWNTO 0);


B : IN S T D _ L O G I C _ V E C T O R (31 DOWNTO 0);
opsel : IN S T D _ L O G I C _ V E C T O R (2 DOWNTO 0);
mode : IN STD_LOGIC ;
output : OUT S T D _ L O G I C _ V E C T O R (31 DOWNTO 0);
cout : OUT STD_LOGIC
);
END alu_32bit ;

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1.1.2 ALU Description
The ALU is supposed to have the following functionalities both in Arithmetic and Logic computing. a
and b are 32-bit data inputs, shown as A and B in the entity description, respectively. Output is the
output port.

Table 1: ALU operation description


mode opsel Micro-operation Description
0 000 a+b Add
0 001 a + b̄ Sub with borrowed carry
0 010 a Move
0 011 a + b̄ + 1 Sub
0 100 a+1 Increment

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0 101 a−1 Decrement

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0 110 a+b+1 Add & Increment

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1 000 a AN D b bit-wise AND
1 001 a OR b bit-wise OR

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rs e1 010 a XOR b bit-wise Exclusive OR
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1 011 ā Compliment
1 101 shl 32-bit shift left
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1.2 Assignment Deliverables


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Your submission should include the following:

• Design report of 32-bit ALU including any assumptions you have made and the list of errors you
have got and how you have solved them.
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• Waveform snapshot for each function with a brief explanation


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• VHDL code file

Note1: Remember to name your files as assignment3 STUDENT-ID alu.vhd and assign-
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ment3 STUDENT-ID alu.pdf.


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Note2: Compress all your files in “zip” or “rar” format and then submit the compressed file.

Note3: Remember to upload the “.tex” file if you have prepared your report using Latex.

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