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Design, implementation and verification of 32-Bit ALU with VIO

Conference Paper · January 2018

DOI: 10.1109/ICISC.2018.8399122

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 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

Design, Implementation and Verification of 32-Bit

ALU with VIO

Dharmavaram Asha Devi Sai Sugun L

Department of Electronics & Communication Engineering Department of Electronics & Communication Engineering
Sreenidhi Institute of Science & Technology, Sreenidhi Institute of Science & Technology,
Hyderabad, India Hyderabad, India
ashadevi.d@rediff.com sslkm13@gmail.com

Abstract—Any Digital design can be represented as RTL form functionality developed by Xilinx. There are two fundamental
by using either VHDL or Verilog_HDL. Such designs can be intellectual property (IP) cores present in ChipScope which
simulated, synthesized, implemented and finally can be verified give real-time observability and controllability. For
by using popular front end tool Xilinx and FPGA development observability ChipScope has a logic analyzer soft core called
boards. In such cases, if the design specification is large enough
to face the difficulty to verify the functionality on the target
the integrated logic analyzer (ILA). For controllability
board, then we can use the virtual I/O concept. The Virtual ChipScope has the soft core called the virtual input output
Input/Output (VIO) debug feature can both monitor and drive core (VIO)[1],[2]. Thus with the latest feature available in the
internal FPGA signals in real time. This feature is used when Xilinx Tool, the proposed 32-bit ALU is examined and drive
there is no possibility to access on physical input and output internal FPGA nodes deep in the design, all done real-time and
devices on the target hardware, we can use this debug feature to in-circuit.
drive and monitor signals that are present on the real hardware.
In the proposed work a 32-bit ALU is designed simulated and II. VIO DESIGN CONCEPT
verified through VIO. This work is designed with Verilog HDL,
and implemented with Xilinx Vivado System Design Suite 2017.1
and Nexys DDR4 FPGA development board is used.

Keywords— FPGA (Field Programmable Gate Array), HDL

(Hardware Description Language), RTL (Register Transfer Level)
design VIO (Virtual Input Output).

I. INTRODUCTION

Simulation can be a step backwards for FPGA development.

This is because FPGAs have reprogramability built in.
Generally, FPGA designers use this feature to verify their
design in-circuit. This is of a great value because one can not Fig.1 Block Diagram of VIO
only save time in generating the simulation testbench, and can
actually verify the design against real time data. The limitation
for in-circuit verification is that observability and The VIO core is a customizable IP that can used to monitor
controllability is negligible. Observation and control are the and drive internal FPGA signals in the real time. The number
two actions used in the Integrated Circuit test field to refer to and size of the input and output ports are customizable to
the facility of access to an internal gate. Observability is the interface with the design under test. Since as the VIO core is
facility of being able to monitor the output of a gate. synchronous to the design being monitored and/or driven, all
Controllability is the facility of being able to change the inputs design clock constraints that are applied to our design and are
of a gate[1]. In-circuit observation and controlling actions are also applied to the components inside the VIO core.
not limited to individual gates, it can spread across entire Features:
modules that can encapsulate hierarchies of many more i. Facilitates Virtual_LEDs and other status indicators
modules. To point the controllability and observability through input ports.
drawbacks of in-circuit verification, there is a ChipScope

978-1-5386-0807-4/18/$31.00 ©2018 IEEE 495

 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

ii. Provides optional activity detectors on input ports in order Table.1: Functional description of 32-Bit ALU
to detect rising and falling transitions between samples.
iii. Provides virtual buttons and other controls through output S.No. S: Selection of the operation For S=
ports. 1. Addition 0
iv. It provides the custom output initialization which allows us 2. Subtraction 1
to specify the value of the VIO core outputs immediately 3. Multiplication 2
following device configuration and start-up. 4. Modulus 3
v. Run time reset of the VIO core to its initial values. 5. Division 4
6. Increment 5
Two types of signals are available in the VIO core: 7. Decrement 6
i. Input probes 8. Logical AND 7
ii. Output probes 9. Logical OR 8
Input Probes: These inputs to the VIO core registered using 10. Logical XOR 9
the design clock that is attached to the CLK input port. The 11. Logical NAND 10
input values are read back one by one and displayed in the 12. Logical NOR 11
Vivado_ logic analyzer feature. 13. Logical XNOR 12
Output Probes: These are the outputs from the VIO core and 14. Logical Right Shift 13
are driven to the user design. The output probes of VIO can be 15. Logical Left Shift 14
initialized to any desired value during the generation time. 16. Logical Negation 15
Activity Detectors: Each VIO core input has additional cells 17. Default Don’t Care
to capture the presence of transitions on the input. Because the
design clock is most likely much faster than the sample period Step2: Verification of the Design using Simulation Process
of the Analyzer, it is possible for the signal being monitored to
transition many times between successive samples. The To do the simulation, testbench module [3] is created for the
activity detectors capture the behavior and the results are 32-Bit ALU design module. Then RUN the testbench module
displayed along with the value in the VLA. to observe the functional behavior of the ALU design.

III. IMPLEMENTATION PROCEDURE OF 32-BIT ALU

Step1: Create an RTL design for 32-Bit ALU using Verilog

HDL with the I/O specifications is as shown in Fig.2.

Fig.3 Waveform Results for the selected operation 6

Step3: Create VIO Block and assign appropriate input and

output signals. Here, A(32-Bit), B(32-Bit) and S(4-Bit) are
the outputs of VIO Block which are to be used to drive the
actual inputs of ALU(DUT). The output of actual design
Fig.2 Design block of 32_bit ALU (DUT) out (32-Bit) is considered as input of the VIO.

The functional Description of the 32-Bit ALU is described in Step4: Create one top level Design which includes both VIO
the Table.1. and DUT as shown in Fig.4.

978-1-5386-0807-4/18/$31.00 ©2018 IEEE 496

 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

Schematic after synthesis is shown in Fig.6 it is also called

Technology schematic. This is a schematic representation of
an NGC file shown in Fig.7. It is represented in terms of logic
elements optimized to the target architecture or "Technology".
For example, in terms of LUTs, carries logic, I/O buffers, and
other technology-specific components. It is generated after the
optimization and technology targeting phase of the synthesis
process. Synthesized schematic allows us to see a technology-
level representation of HDL optimized for a specific Xilinx
architecture, which may help to discover design issues [2].

Fig.4 Top Module which consists of both VIO and DUT

Note: Common clock is to be given to both VIO and DUT

modules to maintain synchronism.

Step5: Create Xilinx Design Constraint file

Design constraints define the requirements that must be met
by the compilation flow in order for the design to be
functional on the board. All constraints are not used by all
steps in the compilation flow. For example, physical
constraints are used only during the implementation steps (that
is, by the placer and the router). The reason is that, the Vivado
Integrated Design Environment (IDE) synthesis and
implementation algorithms are timing-driven. Hence, one Fig.6 Technology Schematic of Top Module
must create proper timing constraints [1],[2].
We can use Xilinx Design Constraint file for RTL schematic is generated after the HDL synthesis phase of
• Synthesis only the synthesis process. It shows a representation of the pre-
• Implementation only optimized design in terms of generic symbols, such as adders,
• Both synthesis and implementation multipliers, counters, AND gates, and OR gates, that are
independent of the targeted Xilinx device. An RTL description
Therefore to create an XDC, elaborate RTL Design and do is usually converted to a gate-level description of the circuit
“IO Planning” at the I/O Ports window.

Fig.5 Creating an XDC using GUI at I/O Ports

For Top-Module only ‘clk’ is the input scalar pin which is E3 Fig.7 Synthesized Schematic
for ARTIX-7 FPGA used in target Nexys DDR4 board.
by a logic synthesis tool[4],[5],[6]. The results of the synthesis
Step6: Synthesize the Design are then used by placement and routing tools to create a

978-1-5386-0807-4/18/$31.00 ©2018 IEEE 497

 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

physical layout. To verify the correctness, Logic simulation

tools are used.

Step7: Implement Design

Implementation process consists of three steps:
i. Translate is a process of merging multiple design files into
a single netlist file. Input net lists plus constraints is nothing
but logic design file. Constraints are assigning the ports and
pins to the design. This entire information is available in
XDC, Xilinx Design Constraints File.
ii. Map means Group logical symbols from the netlist (gates)
into physical components (slices and IOBs). Fig.10 Case_ii when S=0 (Subtraction Operation)
iii. Place and Route is also known as PAR, which Place
components onto the chip, connect the components, and
extract timing data into reports[7],[8],[9].
Step8: Generate bitsteam and program the target device.

Fig.11 Case_iii when S=3 (a % b)

Fig.8 Pop up window after successful generation of Bitstream

After programming the FPGA, hardware VIO window will

open where we can observe the output values for various
combinations of the test vectors[10],[11].

IV. RESULTS AND DISCUSSION

Virtual Output results were observed at the Hardware VIO
Window. Five example cases : addition, subtraction, modulus,
division and increment operations are shown in the Fig.9- 13.
Fig.12 Case_iv when S=4 (Division Operation)

Fig.9 Case_i when S=0 (Addition Operation)

Fig.13 Case_v when S=5 (Increment operation, ie. Out = a+1)

978-1-5386-0807-4/18/$31.00 ©2018 IEEE 498

 Proceedings of the Second International Conference on Inventive Systems and Control (ICISC 2018)
IEEE Xplore Compliant - Part Number:CFP18J06-ART, ISBN:978-1-5386-0807-4; DVD Part Number:CFP18J06DVD, ISBN:978-1-5386-0806-7

Computer Science (IJETTCS), ISSN 2278-6856, Volume 1, Issue 2, July

– August 2012.
[6] T.R. Padmanabhan and B. Bala Tripura Sundari, Design through Verilog
HDL – WSE, 2004 IEEE Press.
[7] Stephen. Brown and Zvonko Vranesic, “Fundamentals of Logic Design
with Verilog” – TMH, 2005.
[8] Thomas and Moorby, “The Verilog Hardware Description Language”,
kluwer academic publishers, 5th edition, 2002.
[9] J. Bhaskar, “A Verilog Primer’’, BSP, 2nd edition 2003.
[10] Dharmavaram Asha Devi, FPGA Design Flow for 8-bit ALU using
Xilinx ISE, International Journal of Modren Electronics and
Communication Engineering, ISSN:2321-2152, Volume.No.4,
Issue.No.2, March 2016.
[11] Pong P Chu “FPGA Prototyping By Verilog Exampes” A John Wiley &
Fig.14 Utilization Report Sons, Inc., Publication.
[12] Vishwas V. Balpande, Abhishek B. Pande, Meeta J. Walke, Bhavna D.
Choudhari, Kiran R. Bagade “Design and Implementation of 16 Bit
V. CONCLUSION AND FUTURE SCOPE Processor on FPGA” International Journal of Advanced Research in
Computer Science and Software Engineering, Volume 5, Issue 1,
The proposed design 32_Bit ALU is designed successfully January 2015. ISSN: 2277- 128X.
with Verilog HDL without any functional errors or warnings.
The functional simulation is done successfully with XSim Author Details:
(Xilinx Simulator). In order to verify the emulation results,
Dharmavaram Asha Devi awarded as an Associate Member of
VIO concept is used. It is implemented IETE in Dec-2000 from the Institute of
Electronics & Telecommunication
with one top module, in which VIO and 32_Bit_ALU are Engineering, New Delhi, India. After
instantiated as shown in Fig.5. The advantage of this concept that, she served as lecturer in the
is we can verify the functionality of our design dynamically by Department of ECE in JNTU Anantapur
applying the various combinations of input patterns where for two years. Later she studied M.Tech.
in Digital Systems and Computer
physical accessing of I/Os is not available. Hence, we can Electronics in JNTU Anantapur and
conclude that FPGA Design flow for the 32_Bit ALU had awarded in 2005. Later she joined as an
been completed. Assistant Professor in Intell Engineering College Anantapur.
Apart from her teaching she had done her research work in
As the front end part had been completed, we can go for Embedded System based Soil Analysis, for which she got
physical design process of the proposed design. It can be tried awarded with a Doctorate Degree from Sri Krishnadevaraya
University, Anantapur in Dec 2011.
with different technology nodes right from 180nm on wards.
She served Intell Engineering College in various
REFERENCES disciplines like Assistant Professor, Associate Professor and
Head of the Department(2005-2010), and Professor (Jan 2012
[1] Xilinx, Virtual Input/Output v3.0 LogiCORE IP Product Guide (PG159),
Vivado Design Suite, PG159 October 4, 2017 from www.xilinx.com . to Dec 2012). At present, she is working as Professor in the
Department of ECE, Sreenidhi Institute of Science and
[2] Vivado Design Suite User Guide: Getting Started , UG910 (v2017.1)
April 5, 2017.
Technology, Hyderabad, India.
[3] Samir Palnitkar, Verilog HDL A Guide to Digital Design and Synthesis, She has published many papers in National and
Second Edition, IEEE 1364-2001 Compliant, Pearson Publications. International level with her research work done in Embedded
[4] AnkitMitra, Design and implementation of low power 16 bit ALU with c
Systems and VLSI Designs.
lock gating, International Journal of Advanced Research in Computer
Engineering & Technology (IJARCET), 2(6), June 2013. Sai Sugun L is UG Research Scholar
[5] Shikha Khurana, Kanika Kaur IMPLEMENTATION OF ALU USING in the Department of ECE, Sreenidhi
FPGA, International Journal of Emerging Trends & Technology in Institute of Science & Technology,
Hyderabad. He is an Aspiring
Machine Learning Researcher. His
Antenna and Wave Propagation lab
solutions have been approved by
scilabs.

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