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VHDL Half and Full Adder Testbench

This document contains VHDL code that defines and simulates half adder and full adder circuits. It defines the components, ports, and signals for each circuit. It also includes a stimulus process that applies different input combinations to the circuits and waits 10 ns between each change to simulate the circuit behavior over time.

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Himanshu Sahu
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162 views3 pages

VHDL Half and Full Adder Testbench

This document contains VHDL code that defines and simulates half adder and full adder circuits. It defines the components, ports, and signals for each circuit. It also includes a stimulus process that applies different input combinations to the circuits and waits 10 ns between each change to simulate the circuit behavior over time.

Uploaded by

Himanshu Sahu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY hatb IS
END hatb;

ARCHITECTURE behavior OF hatb IS

COMPONENT hlfadder
PORT(
a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

BEGIN

uut: hlfadder PORT MAP (


a => a,
b => b,
sum => sum,
carry => carry
);

--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';

--Outputs
signal sum : std_logic;
signal carry : std_logic;

stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
a<='0';
b<='0';
wait for 10 ns;
a<='0';
b<='1';
wait for 10 ns;
a<='1';
b<='0';
wait for 10 ns;
a<='1';
b<='1';

end process;

END;
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
full adder
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY faatb IS
END faatb;

ARCHITECTURE behavior OF faatb IS

COMPONENT fa1tb
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

signal a : std_logic := '0';


signal b : std_logic := '0';
signal cin : std_logic := '0';

signal sum : std_logic;


signal carry : std_logic;

BEGIN

uut: fa1tb PORT MAP (


a => a,
b => b,
cin => cin,
sum => sum,
carry => carry
);

stim_proc: process
begin

wait for 10 ns;


a<='0';
b<='0';
cin<='0';
wait for 10 ns;
a<='0';
b<='0';
cin<='1';
wait for 10 ns;
a<='0';
b<='1';
cin<='0';
wait for 10 ns;
a<='0';
b<='1';
cin<='1';
wait for 10 ns;
a<='1';
b<='0';
cin<='0';
wait for 10 ns;
a<='1';
b<='0';
cin<='1';
wait for 10 ns;
a<='1';
b<='1';
cin<='0';
wait for 10 ns;
a<='1';
b<='1';
cin<='1';
wait for 10 ns;
a<='0';
b<='0';
cin<='0';

end process;

END;

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