Optimal Quantization Employing Programmable

Flash Analog to Digital Converters

Venkatesh Krishnan, Chris Duffy, David Anderson, and Paul Hasler
School of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA 30332, USA.

Abstract— In this paper, a novel implementation of optimal may be obtained by spacing quantization levels closely where
scalar quantizers using a programmable floating–gate flash the signal amplitudes are more likely to occur than where
analog to digital converter (ADC) is described. The optimal they are not. Such a non–uniform quantizer that has been
quantization levels for a given signal class are determined
according to the Lloyd–Max algorithm. The optimal quantization optimized for a particular distribution of the signal amplitude
decision levels are then programmed as the reference voltages levels, characterized by the probability density function, fx (x),
for comparators in the floating–gate flash ADC. A test–bench is known as the Max quantizer [1].
involving the programmable flash ADC and an FPGA interface State-of-the-art hardware implementations of ADCs typi-
to a PC is designed. The proposed setup is tested for several signal cally employ some form of flash architecture in which the
classes including speech signals and gaussian random signals. It is
demonstrated that significant ADC performance gain, quantified input analog signal is converted into an N bit digital signal
in terms of the Signal to Noise Ratio, may be obtained when using 2N − 1 comparators (l0 and l2N +1 do not require com-
optimal scalar quantization is implemented on the floating–gate parators). The comparators determine the difference between
flash ADC. the input signal and its particular reference voltage set to the
quantization levels.
In low–power and/or high–speed systems, analog–to–digital One of the most important issues to consider when design-
converters (ADCs) are often the weak link in the system ing a Flash ADC is the effect of offsets. These offsets may
design. While digital processors are becoming faster and more be introduced from the resistive biasing network, mismatches
power-efficient at the rapid rates dictated by Moore’s and in the comparators, or from other sources. Several traditional
Gene’s laws respectively, ADCs are not improving at the methods used to correct for these offsets require complicated
same rate. Therefore, in many systems the ADC consumes a compensation circuitry that greatly increase the cost and area
significant fraction of the total power or is the limiting factor of the ADC. A programmable flash ADC was developed and
in some respect. This paper describes a method of making the presented in [2] that provides an alternative to these methods,
most efficient use of an ADC by optimizing the quantization by implementing the high speed data converters using floating-
levels on a programmable flash converter. gate circuits.
The process of conversion of an analog signal into its
I. P ROGRAMMABLE F LASH ADC S
digital equivalent involves quantization of the signal amplitude
sampled at fixed intervals of time, T , into a set of discrete D5 D4 D3 D2 D1 D0

signal levels. The sampled analog signal x[n] = x(nT ) is Vin

quantized to its equivalent N bit digital representation by

mapping it to one of the possible 2N reconstruction levels,
Schmitt
Floating Trigger
Node

x̂i , i = 1, ..2N . This is done by comparing x[n] to 2N + 1 Ctot

decision levels, lk , k = 0, ...2N . If lk−1 ≤ x[n] ≤ lk , then

x[n] is quantized to the reconstruction level x̂k . A uniform Floating
Schmitt
Trigger
ENCODER
64:6
quantizer is one in which the reconstruction and decision levels
Node

Ctot
are uniformly spaced. In other words,
lk − lk−1= ∆, k = 0, ...2N
lk + lk−1
x̂k = , k = 1, ...2N (1)
2
Schmitt
Floating Trigger
Node

The performance of a scalar quantizer may be characterized in Ctot

terms of the Signal to Noise Ratio (SNR) of the reconstruction,

defined by, Fig. 1. The structure of the floating-gate flash ADC chip. The 2N − 1

2
comparators and digital circuitry provide a thermometer code to the encoder,
(x[n]) dictating the appropriate digital output.
SN R =
n 2 , where lk−1 ≤ x[n] ≤ lk (2)
n (x[n] − x̂k )
While a uniform quantizer is straightforward, a higher SNR In flash analog-to-digital converters, 2N -1 parallel compara-

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 tors receive an input signal and a fraction of the reference row is selected it is possible to tunnel or inject the e-pot
voltage, Vref . This fraction of Vref acts as a limit between two in order to change the floating-node voltage/comparator trip
quantization levels and provides the comparator’s trip point point.
with respect to the input signal. Each comparator discerns A basic e-pot structure consists of an operational amplifier
whether the input has exceeded its trip point. With the assis- with its positive terminal connected to an external reference
tance of some digital circuitry, the comparator array generates voltage. Its negative terminal has no dc path to ground,
a 2N -1 bit thermometer code that an encoder interprets as the resulting in a floating-node. Connected to the negative terminal
appropriate digital output. is a pFET transistor used for hot-electron injection, a tunneling
A resistive ladder typically provides the desired 2N -1 capacitor, and a feedback capacitor. To decrease an e-pot’s
fractions of the reference. However, we utilize a floating- output voltage, electrons are removed from its floating–gate
gate flash ADC (proposed in [2], [3]) as shown in Fig.1. by the process of Fowler-Nordheim tunneling [5]. To increase
The negative input of each comparator is left floating: the the e-pot’s output voltage, electrons are added to the floating–
comparator’s negative input (i.e. its trip point) is programmed gate through the process of hot-electron injection. To perform
in a method similar to electronic potentiometers (or e-pots) injection, a large voltage is placed across the source and
[4]. Unlike the uniform quantization of a resistive-ladder flash drain of the injection pFET. At the same time the gate
ADC, the e-pot-like comparators permit arbitrary selection of voltage is kept slightly below the source, keeping the pFET in
the quantization levels. the subthreshold regime during injection. Some of the holes
that have diffused across the channel will strike Si atoms
A. Analog to Digital (A/D) Conversion Mode and create a hole-electron pair. If the kinetic energy of the
When the flash ADC is configured for analog to digital electrons exceeds 3.1eV, the Si-SiO2 energy barrier potential,
(A/D) conversion, as shown in Fig. 1 and Fig. 2(b), it is the electron will be injected into the oxide and onto the
arranged similarly to a standard flash converter. The parallel floating-node [6].
capacitance of Cf , the gate capacitance of the injection pFET,
the capacitance of the tunneling junction, and any other C. Programming the Flash Converter
parasitic capacitance sum up as one large capacitance, Ctot , The floating–gate flash converter depends heavily on the
on which the floating-gate charge is stored. It is useful to view ability to program the individual reference voltages of the
this capacitor as an ideal voltage source providing the desired comparators. When operating in program mode, as shown in
analog value. Fig. 1, each individual comparator is configured as an e-pot,
Not only are the comparators crucial in the analog-to-digital or as a non-inverting charge amplifier. To simplify the analysis
conversion process, but they are also utilized as the high-gain the gate capacitance of the injection pFET, the tunneling
amplifiers within the current integrators required to fix the capacitance and any other parasitic capacitances are combined
amount of charge at the floating nodes that provides the trip into one capacitor, Ctot . Analyzing the circuit shows,
points. Viewing Fig. 1, the reader can also easily identify
the other necessary components of a typical flash converter. Ctot · Vin + Cf · (Vref − Vout ) − Qconst = 0 (3)
The analog input signal is Vin . The Schmitt trigger increases and rearranging this we find,
the gain and adds hysteresis to the comparator output. The
INV-NOR-INV simplifies the encoding process by comparing Vout = (Ctot + Cf )/Cf · Vin − Qconst /Cf . (4)
the output of two adjacent rows of the converter. Suppose the
While operating in A/D conversion mode, the individual
input signal is at value that is higher than the voltage stored
converter cells are configured as comparators, with Ctot and
on the first comparator, but lower than that of the second.
Cf connected in parallel from the negative terminal to ground.
The output of the first Schmitt trigger will be low (because
Since there is no DC path to ground, the negative terminal
the Schmitt trigger is inverting), and the output of the second
is floating, and the charge that was stored on it during
will be high. The INV-NOR-INV senses where this change
programming will still be present. As a result, the output
(from all high values to all low values) in comparator outputs
voltage can be expressed as a function of Vin and the floating-
occurs. The output of the INV-NOR-INV stage at which the
node voltage, or Vtrip .
transition occurs is high, while all of the other outputs are low.
This selects the particular encoder row corresponding to the Vout = f (Vin − Vf g ) = f (Vin − Vtrip )
correct 6-bit digital word.  
Qconst
B. Program Mode = f Vin − . (5)
Ctot + Cf
The backbone of the floating–gate flash ADC converter is its This expression illustrates that the charge stored on the
ability to program the reference voltage for each comparator. floating-node is equal to the trip point voltage multiplied by the
In order to do this, each comparator is configured as an e-pot, sum of the capacitances. Plugging the expression for Qconst
as shown in Fig. 1, with each floating-node programmed to a into (4), the output voltage during programming becomes,
different trip voltage. To select an individual comparator for
programming, a 6-bit decoder is included. Once a particular Vout = (1 + Ctot /Cf ) · (Vin − Vtrip ). (6)

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 Program Mode A/D Conversion Mode
Vin Vin

Vtun Vtun

Vout Vout
Ctun Ctun

VDD VDD
Cf

S S Cf S S
Vinj Vinj
(a) (b)

Fig. 2. The two ways to configure the flash ADC. In programming mode the device is a current integrator, while in A/D conversion mode the device is an
open-loop comparator.

The output voltage is equivalent to the input voltage minus

the trip point voltage, multiplied by the capacitive gain of the 3

charge amplifier.
2.5
II. O PTIMAL Q UANTIZERS
In this section, the iterative Lloyd-Max design algorithm 2
for determining the decision levels of an optimal quantizer is
described.
1.5
To design an optimal quantizer for a signal x(t) with a
known probability density function fx (x), the quantization re-
construction and decision levels that minimize a mean squared 1

distortion function, D given by,

 +∞ 0.5
2
D = (x − x̂) fx (x)dx
−∞
2 

N
lk 0.8 1 1.2 1.4 1.6 1.8
2
= (x − x̂k ) fx (x)dx (7) Fig. 3. A merged sweep (input voltage versus output voltage) of the flash’s
i=k lk−1
comparators when it is optimally programmed for a speech signal. It is
noteworthy that the distribution of trip points (and hence quantization levels)
have to be determined. is dense in the middle but sparse at the edges.
It can be easily shown that the optimal quantization levels,
x̂k , and the optimum decision levels, lk , are given by
x̂k+1 + x̂k
lk = (8) described in Section II. Two different signals are used to
2⎡ ⎤ evaluate the performance of the proposed set–up: a random
 lk
⎣ xfx (x) ⎦ dx gaussian distributed signal that is bandlimited to 4000 Hz
x̂k = (9)
lk−1
lk
f (y)dy and a speech signal generated by the sound–card of a PC.
lk−1 y
In each case, a sufficiently long record of the signal is used in
Since the determination of the PDF is cumbersome, [7] the training to determine the respective quantization decision
suggested replacing the statistical expectations in (8)and (9) levels.
with their averages over a long period of time. Thus the The floating–gate flash ADC has been fabricated on a
optimum decisions are obtained by iteratively applying (8) silicon IC from MOSIS. Furthermore, a test board has been
and (9) to a long sequence of training signal. The decision designed to program the ADC. The ADC is first configured
levels are then programmed into the flash ADCs as described in program mode. For a given signal, the corresponding
in Section I-C. optimal quantization decision levels are programmed into the
floating–gate flash ADC as described in Section I. Next, the
III. E XPERIMENTAL S ETUP AND R ESULTS floating–gate flash ADC is configured in the Analog to Digital
A 6–bit floating–gate flash ADC is programmed to the Conversion mode. The trip points set while in program mode
optimum quantization decision levels and its performance is are then measured. Fig.3 shows the distribution of trip points
analyzed. The 65 decison levels of the 6–bit floating–gate flash when the flash is programmed to optimally process a speech
ADC are determined using the Lloyd–Max training algorithm signal. The latched 6 bit digital output of the flash ADC,

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 corresponding to each sample, is read into the PC through an [6] P. Hasler, B. A. Minch, and C. Diorio, “Adaptive circuits using p-FET
FPGA interface. The FPGA samples the output header pins floating-gate devices,” in Proceedings of the 20th Anniversary Conference
on Advnaced Research in VLSI, Atlanta, GA, March 1999, pp. 215–229.
of the flash ADC at a predetermined sampling rate. The 6– [7] S. P. Lloyd, “Least squares quantization in PCM,” IEEE Transactions on
bit samples are then transferred to the PC through an ethernet Information Theory, pp. 129–137, March 1983.
interface. The collected samples are then analyzed for their
accuracy.
The performance of the floating–gate flash ADC is evaluated
in terms of the SNR (Eq. 2) for each of the above mentioned
signal types. These results are presented in Table. I. It is
observed that experimental measurements using the floating–
gate flash ADC closely match the theoretically expected per-
formance enhancement of the optimal quantizer over uniform
quantizers.

Signal Type Theoretical Measured

Uniform Optimal Uniform Optimal
Quant. Quant. Quant. Quant.
Random 36.4120 37.8582 35.1182 36.8289
Speech 35.4562 39.7533 34.4963 39.6117
TABLE I
P ERFORMANCE E VALUATION OF THE 6– BIT F LOATING –G ATE F LASH
ADC

It is observed that the optimal quantizer implemented on the

programmable flash ADC yields a significant gain in terms of
the SNR as compared to the uniform quantizer. The measured
SNR is marginally lower than the theoretically expected value
since there is some error in programming the quantization
levels. (We will essentially remove these errors for the final
paper.)
IV. C ONCLUSIONS
This paper describes the implementation of an optimal
(Lloyd–Max) quantizer on a programmable floating–gate
ADC. The programmable reference voltage levels of the com-
parators in the floating–gate flash ADC enable implementation
of an optimal scalar quantizer. Such an optimal quantizer
reconstructs the input signal more accurately in the voltage
range where the signal amplitudes are more likely to occur
than where they are not. Experimental results are provided
to demonstrate improved quantization performance obtained
when the optimal quantizer for the signal is implemented on
the floating–gate flash ADC.
R EFERENCES
[1] J. Max, “Quantization for minimum distortion,” IRE Transactions on
Information Theory, pp. 7–12, March 1960.
[2] P. Brady and P. Hasler, “Investigations using floating-gate circuits for flash
ADCs,” in The Midwest Symposium on Circuits and Systems, Tulsa, OK,
2002, vol. II, pp. 83–86.
[3] P. Brady and P. Hasler, “Offset compensation in flash ADCs using
floating-gate circuits,” in IEEE International Symposium on Circuits and
Systems, Vancouver, CA, 2004, p. submitted.
[4] R. R. Harrison, J. A. Bragg, P. Hasler, B. A. Minch, and S. Deweerth,
“A CMOS programmable analog memory cell array using floating-gate
circuits,” IEEE Transactions on Circuits and Systems II, vol. 48, no. 1,
pp. 4–11, Jan. 2001.
[5] M. Lenzlinger and E. H. Snow, “Fowler–Nordheim tunneling into
thermally grown SiO2 ,” Journal of Applied Physics, vol. 40, no. 1, pp.
278–283, 1969.

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