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Assignment 1 Digital IC Design

This document contains 4 problems related to digital IC design. Problem 1 involves calculating noise margins and switching threshold for a given CMOS inverter. Problem 2 involves determining width-to-length ratios to achieve a target switching threshold and calculating limits of the threshold given transistor parameter variations. Problem 3 calculates delay time for an inverter's output to fall from 3.3V to 1.65V. Problem 4 determines fall time using two methods for an inverter with a 5V supply and 1pF load.

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270 views2 pages

Assignment 1 Digital IC Design

This document contains 4 problems related to digital IC design. Problem 1 involves calculating noise margins and switching threshold for a given CMOS inverter. Problem 2 involves determining width-to-length ratios to achieve a target switching threshold and calculating limits of the threshold given transistor parameter variations. Problem 3 calculates delay time for an inverter's output to fall from 3.3V to 1.65V. Problem 4 determines fall time using two methods for an inverter with a 5V supply and 1pF load.

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sidhjaj
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Assignment 1

Digital IC Design
Due on 4th Nov, 2020

1. Consider a CMOS inverter with the following parameters:


nMOS VT0,n= 0.6 V µnCox = 60 µA/V2 (W/L)n =8
pMOS VT0,p= -0.7 V µpCox = 25 µA/V2 (W/L)p =12
Calculate the noise margins and switching threshold (Vth) of this circuit. The
power supply voltage is VDD =3.3 V.
2. Design a COMS inverter circuit:
Use the same device parameters as in problem 1. The power supply voltage
is VDD =3.3 V. The channel length of both transistors is Ln = Lp =0.8 µm.
(a) Determine the (Wn/Wp) ratio so that the switching (inversion) threshold
voltage of the circuit is Vth = 1.4 V
(b) The CMOS fabrication process used to manufacture this inverter allows a
variation of the VT0,n value by ±15% arounds its nominal value, and a
variation of the VT0,p value by ±20% arounds its nominal value. Assuming
that all other parameters (such as µn , µp ,Cox, Wn, Wp) always retain their
nominal values, find the upper and lower limits of the switching
threshold voltage (Vth) of this circuit.
3 Consider the CMOS inverter circuit shown in figure below, with VDD = 3.3 V. The
I-V characteristics of the nMOS transistor are specified as follows: when VGS = 3.3
V, the drain current reaches its saturation level Isat = 2 mA for VDS≥ 2.5 V. Assume
that the input signal applied to the gate is a step pulse that switches
instantaneously from 0 V to 3.3 V. Using the data above, calculate the delay time
necessary for the output to fall from its initial value of 3.3 V to 1.65 V, assuming an
output load capacitance of 300 fF.
4 For the CMOS inverter shown in problem 3 with a power supply voltage of
VDD = 5 V,determine the fall time 𝜏fall, which is defined as the time elapsed
between the time pointvat which Vout = V90% = 4.5 V and the time point at
which VOut = Vl0% = 0.5 V. Use both the average-current method and the
differential equation method for calculating 𝜏fall . The output load
capacitance is 1 pF. The nMOS transistor parameters are given as
µnCox = 20 uA/V2
(W/L)n= 10
VT,n = 1.0 V

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