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Beginning FPGA Programming - Partie76

This document describes a design for a 7-segment display counter controlled by a Raspberry Pi over SPI. The top-level design connects a PLL module to generate a clock, an SPI slave module to communicate with the Raspberry Pi, and a 7-segment counter module. It maps the I/O ports of these modules to the FPGA board pins. The 7-segment counter module contains logic to decode the counter values for display on the 7-segment LED display. The Raspberry Pi code allows sending values over SPI to control the counter display.

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60 views5 pages

Beginning FPGA Programming - Partie76

This document describes a design for a 7-segment display counter controlled by a Raspberry Pi over SPI. The top-level design connects a PLL module to generate a clock, an SPI slave module to communicate with the Raspberry Pi, and a 7-segment counter module. It maps the I/O ports of these modules to the FPGA board pins. The 7-segment counter module contains logic to decode the counter values for display on the 7-segment LED display. The Raspberry Pi code allows sending values over SPI to control the counter display.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
Download as pdf or txt
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Chapter 16 ■ Up in Lights: How to Drive LED Segment Displays

Figure 16-11.  end of the architecture deisgn of the 7 segment display counter

16.4 7 Segment display example design


Every FPGA design needs a top level design to connect all of the modules together and to the outside world
(the board connections). This 7 segment display example also needs a top level design.
We will re-use the SPI slave and PLL design from chapter 15 (Two-way communications with your
raspberry Pi: SPI) and add the 7 segment display counter module from the last section. Figure 16-12 shows
all of the modules within the design and their connections.

Figure 16-12.  segment display design example top level block diagram

16.4.1 Code for the top level design


You can copy the following code from Listing 16-1 and save to a file called seven_segment_top.vhd file. Add
this file to the last chapter’s project and select it as top level design by right clicking on the seven_segment_
top.vhd file in the Project navigator “FILES” and select Set as Top-level Entity.

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Chapter 16 ■ Up in Lights: How to Drive LED Segment Displays

Listing 16-1.  seven_segment_top.vhd 7 segment example top level design


library ieee;
use ieee.std_logic_1164.all;

entity seven_segment_top is
port(
-- Clock ins, SYS_CLK = 50MHz
SYS_CLK : in std_logic;
-- LED outs
USER_LED : out std_logic_vector(8 downto 1);
-- SPI Interface to Raspberry Pi
GPIO_01 : in std_logic; -- SPI CLOCK
GPIO_02 : in std_logic; -- SPI MOSI
GPIO_03 : in std_logic; -- SPI SLAVE SELECT (Active low)
GPIO_04 : out std_logic; -- SPI MISO
-- 7 Segment display interface
GPIO_05 : out std_logic; -- Segement Pin 7-A
GPIO_06 : out std_logic; -- Segement Pin 7-B
GPIO_07 : out std_logic; -- Segement Pin 7-C
GPIO_08 : out std_logic; -- Segement Pin 7-D
GPIO_09 : out std_logic; -- Segement Pin 7-E
GPIO_10 : out std_logic; -- Segement Pin 7-F
GPIO_11 : out std_logic -- Segement Pin 7-G
);
end entity seven_segment_top;

architecture arch of seven_segment_top is

signal locked, clk_29MHz_i, rst_i : std_logic;


signal data_out, SPI_DATA : std_logic_vector(7 downto 0);

signal rspi_clk : std_logic;


signal rspi_mosi : std_logic;
signal rspi_miso : std_logic;
signal rspi_ss : std_logic;

signal wr_enable : std_logic;


signal segments_a2g : std_logic_vector(0 to 6);

begin

clk : entity work.pll_29p5M


port map
(
inclk0 => SYS_CLK, -- 50MHz clock input
c0 => clk_29MHz_i, -- 29.5MHz clock ouput
locked => locked -- Lock condition, 1 = Locked
);

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Chapter 16 ■ Up in Lights: How to Drive LED Segment Displays

rst_i <= locked;

spi_slave_pm : entity work.spi_slave


port map(
sys_clock => clk_29MHz_i,
sys_rst => rst_i,
rspi_sclk => rspi_clk, -- SPI clock from raspberry SPI Master
rspi_ss => rspi_ss, -- SPI chip select from raspberry SPI Master
rspi_mosi => rspi_mosi, -- SPI data from raspberry SPI Master
rspi_miso => rspi_miso, -- SPI data to raspberry SPI Master
wr_enable => wr_enable,
data_out => data_out,
data_in => SPI_DATA
);

rspi_clk <= GPIO_01;


rspi_mosi <= GPIO_02;
rspi_ss <= GPIO_03;
GPIO_04 <= rspi_miso;

USER_LED <= not SPI_DATA; -- Output binary counter value to on


-- board LEDs

seven_segment_counter_pm : entity work.seven_segment_counter


port map(
-- general purpose
sys_clock => clk_29MHz_i,
sys_rst => rst_i,
-- serial I/O side
data_valid => wr_enable,
data_in => data_out,
current_value => SPI_DATA,
-- 7 Segment display interface
segments_a2g => segments_a2g
);

GPIO_05 <= segments_a2g(0); -- Segement Pin 7-A


GPIO_06 <= segments_a2g(1); -- Segement Pin 7-B
GPIO_07 <= segments_a2g(2); -- Segement Pin 7-C
GPIO_08 <= segments_a2g(3); -- Segement Pin 7-D
GPIO_09 <= segments_a2g(4); -- Segement Pin 7-E
GPIO_10 <= segments_a2g(5); -- Segement Pin 7-F
GPIO_11 <= segments_a2g(6); -- Segement Pin 7-G

end architecture arch;

377
Chapter 16 ■ Up in Lights: How to Drive LED Segment Displays

16.4.2 Generate and program the FPGA


We create the project in the same way as chapter 15 or you can add the two new VHDL design files (seven_
segment_counter.vhd and seven_segment_top.vhd) to the same project and set seven_segment_top.vhd as
top-level entity. You can get the Altera Quartus Project Navigator look like figure 16-13.

Figure 16-13.  Seven Segment Top Altera Quartus Project Navigator

You can follow the same method as we used in Chapter 15 to generate the bit file and program the FPGA
for this example design.
After the bit file is uploaded to the FPGA, the 7 segment display should start to count from 0 to 9. We can
control the counter from Raspberry PI SPI master interface.

16.5 Control the 7 segment counter from Raspberry Pi


Based on the setup from Chapter 15 for the Raspberry Pi, we should be able to run the following Python
script to get the 7 segment counter to count 3, 2, 1, 2,3,4,5,6,7,8,9,0…etc.

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Chapter 16 ■ Up in Lights: How to Drive LED Segment Displays

Figure 16-14.  Python script for running the counter example

16.6 Summary
In this chapter, we designed a special version of the 7 segment counter. The counter module includes some
register design, a second counter and combination logic for decoding the 7 segment display. All three
elements are very basic and useful for most of the design. The seven_segment_top.vhd shows most of what
all top level designs do - connect all of the modules to the outside world.
After this chapter, you should know to handle the design flow for a FPGA design which is like the
following.
• Define clock and reset
• Define the input and output requirements
• Create the port list
• Separate the design requirements into multiple stages/steps
• Design each stage/step with one process with VHDL code

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