IxiaReferenceGuide PDF

Ixia Platform Reference Guide
Version 1.0
Release 6.60 EA Patch1
December 2013
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ii Ixia Platform Reference Guide, Release 6.60 EA Patch1

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Table of Contents
About This Guide

Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxiii
Manual Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxiii
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxvi
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxvi
Notes, Cautions, Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxvi
Power Cords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-xxxvi
Battery Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-xxxvi
Ventilation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxvii
Use End Caps on Open Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxvii
Use Ejector Tabs Properly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxxviii
China RoHS Declaration Table—Chassis. . . . . . . . . . . . . . . . . . . . . . . . . .1-xxxix
Chapter 1 Platform and Reference Overview

Ixia Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Ixia Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Reduced vs. Full Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Load Module Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Ixia Load Module Properties . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Card Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
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Maximum number of PGIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
New in Version 6.60 EA Patch1 . . . . . . . . . . . . . . . . . . . . . 1-29
Chapter 2 Theory of Operation: General

Ixia Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Chassis Chain (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Chassis Chain Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
Chassis Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Physical Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Virtual Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Ixia Chassis Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
Port Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Types of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Power over Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Power Sourcing Equipment (PSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Powered Devices (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Discovery Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
PoE Acquisition Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
10GE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
XAUI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Lane Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Link Fault Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Link Alarm Status Interrupt (LASI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
40GE and 100GE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
SONET/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Variable Rate Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
SONET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
DCC—Data Communications Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
SRP—Spatial Reuse Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
RPR—Resilient Packet Ring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
GFP—Generic Framing Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
CDL— Converged Data Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
PPP Protocol Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
LCP—Link Control Protocol Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
NCP—Network Control Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
IPv6 Interface Identifiers (IIDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
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HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-39
Frame Relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-39
DSCP—Differentiated Services Code Point . . . . . . . . . . . . . . . . . . . . . . .2-39
ATM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-41
BERT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-45
Available/Unavailable Seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-46
Port Transmit Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
Streams and Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-47
Packet Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-47
Packet Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-48
Advanced Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-48
Stream Queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-49
Basic Stream Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-49
Streams and the Inter-Stream Gap (ISG) . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-50
Bursts and the Inter-Burst Gap (IBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-50
Packets and the Inter-Packet Gap (IPG). . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-51
Frame Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-51
Virtual LANs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52
Stacked VLANs (Q in Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-54
User Defined Fields (UDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-55
Counter Mode UDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56
Random Mode UDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-57
Value List Mode UDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-58
Range List Mode UDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-59
Nested Counter Mode UDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-60
IPv4 Mode UDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62
Table Mode UDF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-63
Transmit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-65
Repeat Last Random Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-66
Port Data Capture Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-66
Continuous Versus Trigger Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-67
Port Capture Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-68
Forced Collision Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-68
Packet Group Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-69
Split Packet Group Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-70
Latency/Jitter Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-71
Sequence Checking Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-73
Switched-Path Duplicate/Gap Checking Mode. . . . . . . . . . . . . . . . . . . . .2-73
Data Integrity Checking Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-74
Automatic Instrumentation Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-74
Port Transmit/Receive Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-75
Round Trip TCP Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-75
Port Statistics Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-76
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IxExplorer Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

Chassis Chain (Software) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78
Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-79
Port Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Port Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Stream Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Packet Group Statistic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Statistic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Stream Statistic Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-80
MII Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
IxRouter Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
IxExplorer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
Multi-User Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
Statistics Logging and Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
Statistics Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83
Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83
Tcl Software Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85

Operation on the Ixia Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
Operation on a Windows Client . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
Operation on a Unix Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-87
Multiple Client Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
TCL Version Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88
Chapter 3 Theory of Operation: Protocols

Protocol Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
ARP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
IGMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
OSPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
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OSPFv3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
BGP4/BGP+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Internal Versus External BGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
IBGP Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
Communities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
BGP Router Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
BGP L3 VPNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
BGP VPN-IPv4 Address Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
L3 VPN VRFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
RIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
RIP Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
RIPng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
ISISv4/v6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
ISIS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
ISIS Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
ISIS Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
RSVP-TE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
PATH Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Explicit_Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
RESV Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Other Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
RSVP-TE Fast Reroute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Ixia Test Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
LDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
MLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
PIM-SM/SSM-v4/v6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
PIM-SM Source-Group Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
PIM-SSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
PIM-SSM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31
Differences Between PIM-SM and PIM-SSM . . . . . . . . . . . . . . . . . . . . . . . . .3-32
Protocol Elements for PIM-SSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
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Multicast VPNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
MPLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
Advantages of MPLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
How Does MPLS Work? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
MPLS Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Hop-by-Hop Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Explicit Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
Label Information Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
BFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
CFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
FCoE and NPIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

Supported Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Data Center Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Priority Traffic Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Priority-based Flow Control (PFC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
IxExplorer Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
Fibre Channel over Ethernet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
Packet View Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
FCoE Initialization Protocol (FIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
IxExplorer Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
NPIV Protocol Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
Precision Time Protocol (PTP) IEEE 1588v2. . . . . . . . . . . 3-41

Supported Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Supported Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Local Clock synchronization through PTP to another PTP clock . . 3-42
Local clock frequency transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
IxExplorer References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
ATM Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

‘Bridged ATM’ Versus ‘Routed ATM’ . . . . . . . . . . . . . . . . . . . . . . . . 3-46
ATM Encapsulation Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Encapsulation Types by Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
ATM Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
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Generic Routing Encapsulation (GRE) . . . . . . . . . . . . . . . . 3-53

GRE Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
GRE Packet Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
GRE Header per RFC 2784 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54
GRE Header per RFC 2890 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-55
DHCP Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
DHCPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
Ethernet OAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
Chapter 4 Optixia XM12 Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
XM12 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Electrical Grounding requirements for Multi-Chassis system
configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
LEDs/LCD Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
LCD Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
Supported Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
SFF Adapter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Prerequisites for Filler Panel Installation: . . . . . . . . . . . . . . . . . . . 4-13
Filler Panel Installation Procedure: . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Cooling Fan Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
XM12 Sound Reducer Installation. . . . . . . . . . . . . . . . . . . . 4-15
Install XM12 Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Rack Mount Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
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High Performance Upgrade Kit . . . . . . . . . . . . . . . . . . . . . 4-18

Statistics and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Chapter 5 Optixia XM2 Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
XM2 Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
LEDs/LCD Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
LCD Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Supported Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
Rack Mount Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Installing Rack-Mount Ear Brackets . . . . . . . . . . . . . . . . . . . . . . . .5-10
Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
SFF Adapter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Prerequisites for Filler Panel Installation: . . . . . . . . . . . . . . . . . . . . 5-14
Filler Panel Installation Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
.Cooling Fan Speed Control. . . . . . . . . . . . . . . . . . . . . . . . 5-15
Chapter 6 XG12 Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
LCD Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
CPU Slot LED Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Power outage recovery and Automatic booting scenario . . . . . . . . 6-16
Chapter 7 XGS12 Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
XGS12 Chassis Installation Precautions . . . . . . . . . . . . . . . . . . . . 7-10
LCD Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
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CPU Slot LED Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11

Power outage recovery and Automatic booting scenario . . . . . . . 7-13
Chapter 8 Optixia X16 Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
X16 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
LEDs/LCD Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
LCD Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5
Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Rack Mount Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Chapter 9 Optixia XL10 Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
XL10 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Rack Mount Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Chapter 10 IXIA 1600T Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
1600T Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
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LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

Rack Mount Cautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Chapter 11 IXIA 400T Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
400T Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Use of Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Chapter 12 IXIA 400T v2 Chassis

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
400T v2 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Use of Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Chapter 13 IXIA 250 Chassis

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Computer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Test Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Ixia 250 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
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Chapter 14 Ixia 100 Chassis

Ixia 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
IXIA 100 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Rack Mount Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Chapter 15 IXIA Impairment Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Chapter 16 IXIA Xcellon-Lava Load Modules

LED function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
CFP adapter diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

CFP Adapter usage for Xcellon-Lava Ethernet Load Modules . . . 16-8
CFP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-8
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
Updated enumerated types in API for LavaAP support in IxN2X

16-14
2x40 QSFP adaptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
Chapter 17 IXIA Power over Ethernet Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
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Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Test Monitor Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Chapter 18 XOTN Chassis Unit

About OTN Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
XOTN Chassis Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Chapter 19 Ixia GPS Auxiliary Function Device (AFD1)

AFD1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
The AFD1 Kit: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
Successful GPS Synchronization in IxExplorer . . . . . . . . . . . . . . . 19-3
Enabling/Installing GPS Based Synchronization . . . . . . . . . . . . . . . . . . . . . . 19-4
Troubleshooting—GPS Unit ‘Not Ready’ . . . . . . . . . . . . . . . . . . . . 19-6
Worldwide Synchronization . . . . . . . . . . . . . . . . . . . . . . . . 19-7

Calculating Latency Accuracy for AFD1 (GPS) . . . . . . . . . . . . . . . 19-8
Front Panel LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
IXIA AFD1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
Chapter 20 Ixia IRIG-B Auxiliary Function Device (AFD2)

AFD2 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
The AFD2 Kit: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
Successful IRIG-B Synchronization in IxExplorer . . . . . . . . . . . . . .20-4
Enabling/Installing IRIG-B Based Synchronization . . . . . . . . . . . . . . . . . . . . 20-4
Changing Time Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
Troubleshooting— IRIG-B Unit ‘Not Ready’ . . . . . . . . . . . . . . . . . . 20-6
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Worldwide Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 20-7

Calculating Latency Accuracy for AFD2 (IRIG-B) . . . . . . . . . . . . . 20-8
Front Panel LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
IXIA AFD2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
Chapter 21 IXIA 10/100/1000 Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
ALM1000T8 and CPM1000T8. . . . . . . . . . . . . . . . . . . . . . 21-12
Card LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
Chapter 22 IXIA 1GbE and 10GbE Aggregation Load Modules

Application Layer Performance Testing . . . . . . . . . . . . . . . . . . . . . 22-2
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
Non-Aggregated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
Gigabit Aggregated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
10GE Aggregated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
Flexible Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
Real-Time Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
Transmit Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
Packet Stream Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3
Advanced Stream Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3
Extensive Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
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Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4

Sequence and Duplicate Packet Checking. . . . . . . . . . . . . . . . . . . 22-4
Routing/Bridging Protocol Emulation . . . . . . . . . . . . . . . . . . . . . . . 22-4
Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
Chapter 23 IXIA Network Processor Load Modules

Application Layer Performance Testing . . . . . . . . . . . . . . . . . . . . . 23-2
Real-time Transport Protocol (RTP) Feature. . . . . . . . . . . . . . . . . . . . . . . . . 23-2
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
Non-Aggregated (Normal) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
Gigabit Aggregated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
10GE Aggregated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
Flexible Packet Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
Real-Time Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
Transmit Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
Packet Stream Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
Advanced Stream Scheduler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
Extensive Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
Data Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-4
Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-4
Sequence and Duplicate Packet Checking. . . . . . . . . . . . . . . . . . . 23-5
Routing/Bridging Protocol Emulation . . . . . . . . . . . . . . . . . . . . . . . 23-5
Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10
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Chapter 24 IXIA 40/100 Gigabit Ethernet Load Modules

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
Clock In/Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Multilane Distribution Configuration. . . . . . . . . . . . . . . . . . 24-10

PCS Lane Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
Chapter 25 IXIA 10 Gigabit Ethernet Load Modules

LSM 10GE Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
Clock In/Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
Removable Carrier Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
Carrier Card Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-19
XENPAK/XAUI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
NGY Fault Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
IEEE Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20
NGY Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20
Features that force deviation from IEEE spec. . . . . . . . . . . . . . . . . . . . . . . .25-20
Tx Ignores Rx Link Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20
Transmit Ignores Link Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20
10GE LAN Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
Optical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
XAUI Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25
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Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27
Clock In/Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27
XAUI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-28
MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-29
XENPAK Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32
XENPAK Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32
Clock In/Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33
XENPAK Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34
Power Sequencing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34
XAUI Fujitsu to XENPAK Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35
CX4 to XENPAK Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-36
Chapter 26 IXIA 10GE LAN/WAN and OC 192 POS

Load Modules
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
10G MSM Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
Clock In/Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
Trigger Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-6
OC-192c Triple Mode Family . . . . . . . . . . . . . . . . . . . . . . . 26-6

Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9
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Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10

Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
UNIPHY Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15
Clock Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15
Chapter 27 IXIA OC12 ATM/POS Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
OC12 POS 622 Specifications . . . . . . . . . . . . . . . . . . . . . . 27-3
ATM Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
Physical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10
Chapter 28 IXIA 10/100 Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
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Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
Chapter 29 IXIA 100 Load Modules

Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Chapter 30 IXIA Gigabit Load Modules

Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7
Chapter 31 IXIA OC12c/OC3c Load Modules

Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4
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Optical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
Chapter 32 IXIA OC48c Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
OC48c VAR Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5

Frequency Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
Frequency Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6
Optical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7
Chapter 33 IXIA FCMGXM Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
Chapter 34 IXIA Xcellon-Flex Load Modules

Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4
Mechanical Specification of FlexAP10G16S/FlexFE10G16S

Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
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Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8

Led Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9
Mechanical Specification of FlexAP1040SQ Load Modules 34-9

Front Panel Production – 944-1062-02. . . . . . . . . . . . . . . . . . . . . . 34-9
Led Panel Production – 944-1062-02 . . . . . . . . . . . . . . . . . . . . . . 34-10
Mechanical Specification of FlexAP40QP4 Load Modules 34-11

Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11
Led Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-12
Chapter 35 IXIA Xcellon-Multis Load Modules

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2
Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3

XM100GE4CXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
XM100GE4CXP +FAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3
XM40GE12QSFP +FAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4
Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
Application Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-10
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 35-11

Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-11
Led Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-11
Fan-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-12

Fan-out Cable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-12
100GE CXP-to-3x40GE QSFP+ AOC fiber fan-out cables . . . . . . . . . . . . . 35-12
MT-MT 3x40GE passive fiber fan-out cables . . . . . . . . . . . . . . . . . . . . . . . 35-12
CXP point-to-point AOC Cable (no fan-out) . . . . . . . . . . . . . . . . . . . . . . . . 35-13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-13
Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-14
Transceivers and Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-15
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Active Optical Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-15

Fibre Fan-out Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-16
CXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-17
QSFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-18
Chapter 36 IXIA PerfectStorm Load Modules

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2
Platform Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4
Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5

PS10GE8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5
PS10GE8NG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5
PS40GE2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
PS40GE2NG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8
Application Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-10
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 36-11

Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11
LED Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11
Chapter 37 IXIA Xdensity XDM10G32S/8S Load Modules

XDM10G32S Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1
XDM10G8S Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5
Xdensity Four User Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-8
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Chapter 38 IXIA Stream Extraction Modules

Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3
Chapter 39 IxVM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-2
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
Hypervisor / Host OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3
VM Operating Systems (Guest OS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3
Distribution Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3
VM Discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
Update Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
Ixia Application Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4
About the Red Hat and CentOS Kernels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
Licensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5
Not Licensed: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6
IxVM Deployment Models . . . . . . . . . . . . . . . . . . . . . . . . . 39-7

vSphere Deployment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-7
KVM Deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-8
XEN Deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-10
Bare-metal Linux Deployment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11
Windows components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-12
Installing IxVM Components on a Physical computer or Windows VM . 39-13
TCP/UDP Ports Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-13
TCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-13
UDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-14
Windows VM ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-14
Installing IxVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-15

OVA-based Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-15
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Downloading and Installing vSphere. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-15

Creating the Source and Destination Networks . . . . . . . . . . . . . . . . . . . . . .39-16
Deploying the IxVM Appliances (OVAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-17
Configuring Static Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-18
Configuring Discovery Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-19
Optimizing Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-20
KVM Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-22
KVM Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-24

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-24
Other sources of information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-24
Before you begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-24
Hardware requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-24
Software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-24
Time requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-25
CentOS version requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-25
Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-25
Use case 1 – Back to back test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-25
Use case 2 – External connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-26
Use case 1 – Back to back test . . . . . . . . . . . . . . . . . . . . . . . . . . 39-27
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-27
Introduction to libvirt daemon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-27
Establish the QEMU connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-28
Create Ethernet Bridge for Management network. . . . . . . . . . . . . . . . . . . . .39-29
Create Ethernet bridge for test ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-30
Instantiate IxVMPort1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-31
Instantiate IxVMPort2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-32
Create and instantiate IxVM management VM . . . . . . . . . . . . . . . . . . . . . . .39-33
Install Windows 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-34
Pre-requisites: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-34
Installation Steps: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-34
Customize Windows 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-37
IxVM Live CD Installation . . . . . . . . . . . . . . . . . . . . . . . . . 39-45
Install IxOS and IxNetwork . . . . . . . . . . . . . . . . . . . . . . . . 39-52

Install and configure NTP server on the host . . . . . . . . . . . . . . . . . . . . . . . .39-52
Configuring DHCP Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-52
IxOS Topology Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-58
Use Deployment Wizard to select the required topology from the available
IxOS versions to transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-58
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Use the IxOSTransferTopology importer application that is automatically run

at the end of any new IxOS installation . . . . . . . . . . . . . . . . . . . . . . . 39-59
Instantiate IxVM test ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-60
Use case 2 – External connectivity . . . . . . . . . . . . . . . . . . . . . . . . 39-64
........................................................... 39-64
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-64
Introduction to xinet.d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-64
Discover the Windows VM IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-64
Enable remote desktop for IxVM User. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-65
Install xinetd on the host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-66
Create port-forwarding definition file for xinetd . . . . . . . . . . . . . . . . . . . . . . 39-66
Test Microsoft Remote Desktop connection . . . . . . . . . . . . . . . . . . . . . . . . 39-67
Test IxNetwork TCL server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-68
Xen Server Hypervisor Support . . . . . . . . . . . . . . . . . . . . 39-69

Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-69
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Create an IxVM machine39-69
Create and instantiate IxVM management VM . . . . . . . . . . . . . . . 39-70
Xen support in Chassis Builder. . . . . . . . . . . . . . . . . . . . . . . . . . .39-71
Bare-metal (RPM) Installation . . . . . . . . . . . . . . . . . . . . . 39-74

Installing Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-74
Installing IxVM Server, IxExplorer, and IxNetwork . . . . . . . . . . . . 39-74
Installing the IxVM RPM Packages . . . . . . . . . . . . . . . . . . . . . . . . 39-75
Configuring NTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-76

NTP server options for IxVM cards . . . . . . . . . . . . . . . . . . . . . . . . 39-77
Single-port vs. Multi-port Cards . . . . . . . . . . . . . . . . . . . . 39-78

Converting Single-port cards into Multi-port cards . . . . . . . . . . . . 39-78
Create the Additional Test Networks. . . . . . . . . . . . . . . . . . . . . . . 39-78
Add Ports to the Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-79
(IxExplorer): Adding a Multi-port Card . . . . . . . . . . . . . . . . . . . . . 39-79
(IxNetwork): Discovering a Multi-port Card . . . . . . . . . . . . . . . . . . 39-80
Sample Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-81

Install vSphere . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-81
Configure the Source and Destination Networks . . . . . . . . . . . . . 39-82
Deploy a Windows VM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-82
Deploy the Linux OVA Template . . . . . . . . . . . . . . . . . . . . . . . . . . 39-83
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Configure the IxVM card (Linux OVA) Addresses . . . . . . . . . . . . 39-84

Configure the IxVM Chassis Addresses . . . . . . . . . . . . . . . . . . . 39-85
Discover the IxVM Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-86
What to do Next. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-88
Deployment Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-88

Upgrade Virtual Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-88
Upgrade Appliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-89
Select Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-89
Install New Virtual Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-90
Xen support in Deployment Wizard . . . . . . . . . . . . . . . . . . . . . . 39-90
Configure Windows Virtual Controller Settings . . . . . . . . . . . . . . 39-92
Configure Virtual Load Module Settings . . . . . . . . . . . . . . . . . . . 39-93
Configure Host Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-94
Configure Host Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39-94
Jobs Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-95
Troubleshooting and Tips . . . . . . . . . . . . . . . . . . . . . . . . . 39-97

Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-99
Active iptables firewall on host . . . . . . . . . . . . . . . . . . . . . . . . . 39-100
TclAPI Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-102

IxOS Tcl API Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-102
IxOS Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-104
List of DHCP Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-108
Chapter 40 XAir™ XM Module

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2
Appendix A XAUI Connector Specifications

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
Standard Connector Specifications . . . . . . . . . . . . . . . . . . . .A-2
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Front Panel Loopback Connector . . . . . . . . . . . . . . . . . . . . A-4
Standard Cable Specification . . . . . . . . . . . . . . . . . . . . . . . . A-5
SMA Break-Out Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
XAUI Fujitsu to XENPAK Adapter . . . . . . . . . . . . . . . . . . . . A-8
XAUI Tyco Interoperability Backplane HM-Zd Adapter . . . . A-9
Appendix B Available Statistics

Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
IxExplorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Statistics Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Extra Statistics Check Boxes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Key to Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
TCL Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
Statistics Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
Access to Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
C++ Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Statistics Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Access to Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Description of Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9

Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-32
Statistics for 1GbE and 10GbE Aggregation Load Modules . . . . B-159
FCoE Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-161
fcoeRxSharedStat1 and fcoeRxSharedStat2 . . . . . . . . . . . . . . . . . . . . . . . B-162
FIP Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-162
ALM, ELM and CPM Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . B-162
40/100 GE Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-165
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Appendix C GPS Antenna Installation Requirements

Roof Mount Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1
Conduit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Conduit Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Coaxial Bending Radius . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Lightning Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
GPS Mast Location Requirements . . . . . . . . . . . . . . . . . . . . . . . . . C-4
Preferred Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
Requirements if Preferred Location is Not Available. . . . . . . . . . . . . . . . . . . . C-4
Window Mount Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-5

Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5
Appendix D Hot-Swap Procedure

Load Module Hot-Swap Insertion . . . . . . . . . . . . . . . . . . . . .D-1
Load Module Hot-Swap Removal . . . . . . . . . . . . . . . . . . . . .D-2
Appendix E IP Port Assignments on Ixia Chassis and Linux port

CPUs
Applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-1
Services on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-1
Appendix F Laptop Controller

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
Ixia Platform Reference Guide, Release 6.60 EA Patch1 xxxi

Table of Contents
xxxii Ixia Platform Reference Guide, Release 6.60 EA Patch1

About This Guide
The information in this section is provided to help you navigate this guide and
make better use of its content. A list of related documents is also included.
Purpose This guide provides information about Ixia hardware theory, features, functions,
and options, as well as additional test setup details.
Manual Content This guide contains the following sections:
Section Description
About This Guide Provides information on this manual, including its

purpose, content, and related documentation. Also
explains how to contact technical support.
Chapter 1, Platform and Reference Overview Provides a basic overview of Ixia hardware and theory of
operation. Hardware includes descriptions of all
supported chassis and load modules.
Chapter 2, Theory of Operation: General Provides a general overview of the various technologies
used in both IxExplorer and in the IxOS.
Chapter 3, Theory of Operation: Protocols Provides a general overview of the various technologies
used in IxNetwork and IxRouter.
Chapter 4, Optixia XM12 Chassis Provides a detailed description of the features and
systems of the Optixia XM12 chassis.
Chapter 5, Optixia XM2 Chassis Provides a detailed description of the features and
systems of the Optixia XM2 chassis.
Chapter 6, XG12 Chassis Provides a detailed description of the features and

systems of the XG12 chassis.
Chapter 7, XGS12 Chassis Provides a detailed description of the features and

systems of the XGS12 chassis.
Ixia Platform Reference Guide, Release 6.60 EA Patch1 xxxiii

Section Description
Chapter 8, Optixia X16 Chassis Provides a detailed description of the features and
systems of the Optixia X16 chassis.
Chapter 9, Optixia XL10 Chassis Provides a detailed description of the features and
systems of the Optixia XL10 chassis.
Chapter 10, IXIA 1600T Chassis Provides a detailed description of the features and
systems of the 1600T chassis.
Chapter 11, IXIA 400T Chassis Provides a detailed description of the features and
systems of the 400T chassis.
Chapter 13, IXIA 250 Chassis Provides a detailed description of the features and
systems of the 250 chassis.
Chapter 14, Ixia 100 Chassis Provides a detailed description of the features and
systems of the 100 clocking chassis.
Chapter 15, IXIA Impairment Load Modules Provides a detailed description of the features and
capabilities of Xdensity (XDM10G32S) load module.
Chapter 16, IXIA Xcellon-Lava Load Modules Provides a detailed description of the features and
capabilities of Xcellon-Lava load module.
Chapter 17, IXIA Power over Ethernet Load Provides a detailed description of the features and
Modules capabilities of Power over Ethernet load modules.
Chapter 18, XOTN Chassis Unit a: Provides a detailed description of the features and
systems of the XOTN chassis.
Chapter 19, Ixia GPS Auxiliary Function Device Provides a detailed description of the features and
(AFD1) systems of the Ixia Auxiliary Function Device (AFD1).
Chapter 20, Ixia IRIG-B Auxiliary Function Device Provides a detailed description of the features and
(AFD2) systems of the Ixia IRI-B Auxiliary Function Device
(AFD2).
Chapter 21, IXIA 10/100/1000 Load Modules Provides a detailed description of the features and
capabilities of 10/100/1000 Ethernet load modules.
Chapter 22, IXIA 1GbE and 10GbE Aggregation Provides a detailed description of the features and
Load Modules capabilities of 1 Gigabit Ethernet and 10GbE aggregation
load modules.
Chapter 23, IXIA Network Processor Load Modules Provides a detailed description of the features and
capabilities of Xcellon-Ultra NP and Xcellon-Ultra XP
load modules. It also provides card specifications and
description of features when Xcellon-Ultra card is used in
IxN2X mode with added IxN2X capability. The card is
reported as Xcellon-Ultra NG by IxExplorer when it is
running in IxN2X mode. Xcellon-Ultra NP, Xcellon-Ultra
XP, and Xcellon-Ultra NG are all physically similar.
Chapter 24, IXIA 40/100 Gigabit Ethernet Load Provides a detailed description of the features and
Modules capabilities of 40 and 100 Gigabit Ethernet load modules.
Chapter 25, IXIA 10 Gigabit Ethernet Load Modules Provides a detailed description of the features and
capabilities of 10 Gigabit Ethernet load modules.
xxxiv Ixia Platform Reference Guide, Release 6.60 EA Patch1

Section Description
Chapter 26, IXIA 10GE LAN/WAN and OC 192 POS Provides a detailed description of the features and
Load Modules capabilities of OC192c Optical Carrier load modules.
Chapter 27, IXIA OC12 ATM/POS Load Modules Provides a detailed description of the features and
capabilities of ATM load modules.
Chapter 28, IXIA 10/100 Load Modules Provides a detailed description of the features and
capabilities of 10/100 Ethernet load modules.
Chapter 29, IXIA 100 Load Modules Provides a detailed description of the features and
capabilities of 100 Ethernet load modules.
Chapter 30, IXIA Gigabit Load Modules Provides a detailed description of the features and
capabilities of Gigabit Ethernet load modules.
Chapter 31, IXIA OC12c/OC3c Load Modules Provides a detailed description of the features and
capabilities of OC12c/OC3c Optical Carrier load
modules.
Chapter 32, IXIA OC48c Load Modules Provides a detailed description of the features and
capabilities of OC48c Optical Carrier load modules.
Chapter 33, IXIA FCMGXM Load Modules Provides a detailed description of the features and
capabilities of Fibre Channel load modules.
Chapter 34, IXIA Xcellon-Flex Load Modules Provides a detailed description of the features and
capabilities of Xcellon-Flex load modules.
Chapter 35, IXIA Xcellon-Multis Load Modules Provides a detailed description of the features and
capabilities of Xcellon-Multis load modules.
Chapter 36, IXIA PerfectStorm Load Modules Provides a detailed description of the features and
capabilities of PerfectStorm load modules.
Chapter 37, IXIA Xdensity XDM10G32S/8S Load Provides a detailed description of the features and
Modules capabilities of Xdensity (XDM10G32S) load module.
Chapter 38, IXIA Stream Extraction Modules Provides a detailed description of the features and
capabilities of Ethernet Stream Extraction load modules.
Chapter 39, IxVM Provides a detailed description of the features and

capabilities of IxVM load modules.
Chapter 40, XAir™ XM Module Provides the next generation hardware for LTE UE
emulation and allows LTE Advanced feature support.
Appendix A, XAUI Connector Specifications Provides a detailed description of various XAUI

connectors provided by Ixia for various modules.
Appendix B, Available Statistics Lists all the statistics, by module and by technology,
collected by Ixia hardware.
Appendix C, GPS Antenna Installation Describes the recommended installation method for an
Requirements IXIA GPS Antenna.
Appendix D, Hot-Swap Procedure Describes the procedure for removing and reinstalling a
Load Module without requiring the removal of power from
the rest of the chassis.
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Section Description
Appendix E, IP Port Assignments on Ixia Chassis Lists the services assigned to IP ports on Ixia chassis
and Linux port CPUs and port.
Appendix F, Laptop Controller Lists the specifications of the Laptop Controller.
Index Provides a comprehensive index listing for the manual.
Related The following guides help you learn more about the hardware for IxOS. The
Documentation guides are available on the CD shipped with the application, as well as on the Ixia
Website at www.ixiacom.com.
• IxExplorer User Guide: Provides details on the usage of the IxExplorer GUI
for operation with an Ixia chassis and Ixia load modules.
• IxServer User Guide: Provides details on the usage of the IxServer GUI for
operation on an Ixia chassis.
• IxOS Tcl Development Guide: Provides details on the structure and

conventions of the IxExplorer Tcl API and provides detailed information on
all API commands.
• Ixia online Glossary of technical terms is located at www.ixiacom.com/

glossary/.
Technical Support You can obtain technical support for any Ixia product by contacting Ixia
Technical Support by any of the methods mentioned on the inside cover of this
manual. Technical support from Ixia’s corporate headquarters is available
Monday through Friday from 06:00 to 18:00, UTC (excluding American
holidays). Technical support from Ixia’s EMEA and India locations is available
from Monday through Friday, 08:00 to 17:00 local time (excluding local
holidays).
Notes, Cautions, Power Cords

Warnings
Power cords that are included in shipments of Ixia equipment meet the approved/
recognized standards of the national safety organization(s) of the destination
country.
Battery Replacement
Caution: Danger of explosion if battery is incorrectly replaced. You should not

attempt to replace the battery.
Return to Ixia Customer Service for replacement with the same or equivalent
type of battery. Ixia disposes of used batteries according to the battery
manufacturer's instructions.
xxxvi Ixia Platform Reference Guide, Release 6.60 EA Patch1

Ventilation Requirements
The following caution applies to equipment installed into equipment racks.
Caution: Reduced Air Flow: Install the equipment in a rack so that the amount
of air flow required for safe operation of the equipment is not reduced.
Do not block the back or sides of the chassis, and leave approximately two
inches of space around the unit for proper ventilation.
Use End Caps on Open Ports

The metal edges of the SFP port are sharp. To avoid injury, always keep unused
SFP ports covered with end caps. When installing a load module into a chassis or
removing from a chassis, ensure that end caps are in place on unused ports.
Warning: To prevent accidental injury to personnel, do not leave unused SFP

(or SFP+) ports uncovered. When transceivers are not installed, end caps must
be used.
Figure 1-1 shows the precautionary measure to be taken while handling unused
SFP/SFP+ Ports in the laboratory.
Figure 1-1. Unused Ports
Unused SFP/SFP+
ports need end caps
Affected load modules include the following:
• NGY with SFP+ interface, 2/4/8-port, all models
• Dual PHY SFF cards with RJ45 and SFP Gigabit (TXS and STXS)
Ixia Platform Reference Guide, Release 6.60 EA Patch1 xxxvii

• Xcellon-Ultra NP, XP, and NG
• LSM1000XMV 4/8/12/16-port
• LSM1000XMS
• ASM1000XMV
• AFM1000SP
• ELM1000ST
Use Ejector Tabs Properly

Ejector tabs on load modules are to be used only to eject a load module from the
chassis backplane connector. They are not designed to support the weight of the
load module. Ejector tabs can bend or break if used improperly as handles to
push, pull, or carry a load module.
Caution: Do not use ejector tabs as handles to support a load module while
installing and seating into the chassis. The ejector tabs are to be used only to
eject the module from the chassis backplane connector.
xxxviii Ixia Platform Reference Guide, Release 6.60 EA Patch1

China RoHS Declaration Table—Chassis
ሿٙ咊‫ؾ‬ʻ‫ټ‬㲯ʼʳ ‫ڶ੅ڶ‬୭ढ凝ࢨցై(Hazardous Substances or Elements)

(Component Name)
卋 ‫ޤ‬ 叏 ք᪔卲ʳ ‫ڍ‬ᄽ侶૖ʳ ‫ڍ‬ᄽԲ૖ㅘʳ

Lead Mercury Cadmium Chromium Poly- Poly-
(Pb) (Hg) (Cd) VI brominated brominated
Compounds Biphenyls Diphenyl
(Cr6+) (PBB) Ethers (PBDE)
‫ࠫٱ‬䶣ሁ಻ٙʳ
ʻPrinted Circuit Assemblies)ʳ X O O O O O
փຝ优ሁʳʳ
(Internal wiring)
X O O O O O
ࢍਮʳ
(Chassis) O O O O O O
८㺉؆㨆ʳ
(Metal Enclosure) O O O O O O
ᝅ༐ʿᝅ匏ʻ௕ʼʿᝅඝʻʳ匏ʼʿʳ
䨼എʿʳ仟ࡐٙʳ
(Nuts, bolts, screws,
O O O O O O
washers, Fasteners)
䶣ᄭࠎ䬗ᕴ
(Power Supply Unit) O O O O O O
咾஛ʳ
(Fan) O O O O O O
‫૿إ‬ʻছʼ૿ࣨʳ
(Front panel) O O O O O O
O: ।‫ق‬具‫ڶ੅ڶ‬୭ढ凝‫ڇ‬具ຝٙࢬ‫݁ڶ‬凝‫ޗ‬றխऱܶၦ݁‫ڇ‬ʳSJ/T 11363-
2006䰬଱億ࡳऱૻၦ૞‫אޣ‬Հˁ
O: Indicates that this toxic or hazardous substance contained in all of the homogeneous
materials for this part is below the limit requirement in SJ/T11363-2006.
ʳ
X: ।‫ق‬具‫ڶ੅ڶ‬୭ढ凝۟֟‫ڇ‬具ຝٙऱਬԫ݁凝‫ޗ‬றխऱܶၦ၌‫נ‬ʳSJ/T 11363-
2006䰬଱億ࡳऱૻၦ૞‫ޣ‬ˁ
X: Indicates that this toxic or hazardous substance contained in at least one of the
homogeneous materials used for this part is above the limit requirement in SJ/T11363-2006.
Ixia Platform Reference Guide, Release 6.60 EA Patch1 xxxix

xl Ixia Platform Reference Guide, Release 6.60 EA Patch1
Chapter 1: Platform and Reference
1 Overview
The Ixia system is the most comprehensive tool available for testing multilayer
10/100 Mbps Ethernet, Ethernet Gigabit, 10 Gigabit Ethernet, ATM, and Packet
over SONET switches, routers, and networks.
The Ixia product family includes chassis, load modules, the Ixia IxExplorer
software program, and optional Tcl scripts and related software. A chassis can be
configured with any mix of load modules, and multiple chassis can be
daisychained and synchronized to support very large and complex test
environments. The Ixia IxExplorer software provides complete configuration,
control, and monitoring of all Ixia resources in the test network, and the Tcl
scripts allow to rapidly conduct the most popular industry benchmark tests.
The Optixia XM12 provides high port density and hot swappable capability. The
Optixia XM2 provides hot-swappable capability in a more portable format. The
Optixia X16 chassis also provides hot-swappable capability for up to 16 load
modules.
The Optixia XL10 offers the highest port density with support for up to 240
Gigabit Ethernet ports and 54 10-GbE ports in a single chassis. Other chassis
models are the IXIA 400T (supports up to four load modules), the IXIA 250
(supports one built-in module and two extra modules), and IXIA 100 (supports
one card). Depending on network technology, one to 48 ports can be packaged on
a card. A card is also referred to as a load module. For most media, any
combination of load modules may be included in a single chassis. The highly
scalable architecture supports daisy-chaining of up to 256 chassis that may be
locally synchronized. Thus, even the most complex systems can be tested
thoroughly and cost-effectively.
You can configure and control the unit directly through connections to a
keyboard, mouse, monitor, and printer. Also, the unit can be connected to an
Ethernet network, and an administrator can remotely monitor and control it using
the IxExplorer software program. Multiple users can access the unit
simultaneously, splitting the ports within a chassis and controlling the activity
and configuration of all ports and functions.
Ixia Platform Reference Guide, Release 6.60 EA Patch1 1-1

Platform and Reference Overview
1 Ixia Chassis
Front panel displays give immediate indication of link state, transmission or

reception of packets, and error conditions.
Ixia produces a number of load modules which provide data transmission and
reception capabilities for a variety of Ethernet, ATM, and Packet Over Sonet
(POS) speed and technologies. These load modules reside in an Ixia chassis,
which provide different numbers of load module slots and power. This chapter
introduces the Ixia hardware components. The Ixia chassis and load modules are
compared and contrasted.
Ixia Chassis
The following Ixia chassis are currently available for sale:
• XG12 Chassis: The XG12 Chassis is the next generation high performance
chassis platform capable of supporting next generation load modules. It is a
12 slot chassis with increased power and airflow delivery along with
reservations for increased performance to the card. The 12-slot platform
allows for higher port density load modules.
• XGS12 Chassis: The XGS12 Chassis is the next generation high performance
platform capable of supporting all XM form factor load modules, including
full chassis configurations of the Xcellon load modules. It is a 12-slot chassis
with highspeed backplane (160 Gbps between each adjacent two cards)
designed for aggregation across load modules.
• Optixia XM12 Chassis: Capable of holding up to 12 Ixia load modules and
equipped with extra power and fans required for high-powered load modules.
Supports higher port density. Modules can be inserted and removed from the
chassis without shutting the chassis down, and a load module can be removed
without impacting the processes of other load modules. An optional Sound
Reducer (PN 943-0021) can be installed on the rear of the XM12 chassis, to
reduce the fan noise by approximately 10 dB. The XM12 High Performance
version (PN OPTIXIAXM12-02) has two 2.0 kW power supply; the standard
XM12 version has two 1.6 kW power supply.
• Optixia XM2 Chassis: Capable of holding two Ixia load modules and
equipped with extra power and fans required for some high-powered load
modules. Supports higher port density. Modules can be inserted and removed
from the chassis without shutting the chassis down, and a load module can be
removed without impacting the processes of other load modules.
• Optixia X16 Chassis: Capable of holding up to 16 Ixia load modules and
modules. Modules can be inserted and removed from the chassis without
shutting the chassis down, and a load module can be removed without
impacting the processes of other load modules.
• Optixia XL10 Chassis: Capable of holding a combination of high-density Ixia
load modules with 24 ports. It supports up to 240 10/100/1000 Mbps ports. It
is equipped with redundant power supplies. Modules can be inserted and
removed from the chassis without shutting the chassis down, and a load
module can be removed without impacting the processes of other load
modules. The Optixia XL10 chassis includes sufficient power and airflow to
support high-powered load modules.
1-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Ixia Chassis
• IXIA 400T Chassis: Capable of holding up to four Ixia load modules and
modules.
• IXIA 250 Chassis: A portable Field Service Unit (FSU) which includes a
single port (either copper 10/100/1000 or fiber 1000) and capable of holding
up to two additional Ixia load modules. May optionally be equipped with a
built-in CDMA receiver.
The following Ixia chassis are no longer available for sale:

• IXIA 1600T Chassis: Capable of holding up to 16 Ixia load modules and
modules.
• Ixia 100 Chassis: The IXIA 100 is capable of holding one Ixia load module
and includes a built-in GPS or CDMA receiver.
All Ixia chassis have the ability to hold one or more standard load modules. Ixia
load modules provide media dependent and independent ports to Devices Under
Test (DUTs). Any of the chassis may be daisy-chained and provide synchronized
operations. The IXIA 100 chassis includes timing provisions based on GPS
which allows accurate worldwide synchronization without local inter-chassis
connections.
Each chassis contains a self-contained computer running Windows XP

Professional™ and includes a 10/100/1000MB network interface and local disk.
They may include a floppy drive, a CD-ROM drive, or DVD-ROM drive. A
chain of chassis may be controlled through a monitor, keyboard, and mouse
directly connected to any of the chassis or remotely through the network interface
card. Multiple users may safely share ports in a chassis chain. Several of the
high-end load modules consume more power and generate additional heat. Only
a limited number of such modules may be used in selected chassis. The basic
characteristics of these chassis are compared in Table 1-1 on page 1-4. The

1 Ixia Chassis
process of initial chassis configuration is explained in Chapter 1, Platform and

Reference Overview. Each chassis is further described in its own chapter.
Table 1-1. Ixia Chassis Comparison
Chassis # of Special Feature Mounting

slots
XG12 12 The XG12 Chassis is the next generation Rack

high performance chassis platform capable
of supporting next generation load
modules. It is a 12 slot chassis with
increased power and airflow delivery along
with reservations for increased
performance to the card. The 12-slot
platform allows for higher port density load
modules.
XGS12 12 The XGS12 Chassis is the next generation Rack

high performance platform capable of
supporting all XM form factor load modules,
including full chassis configurations of the
Xcellon load modules. It is a 12-slot chassis
with highspeed backplane (160 Gbps
between each adjacent two cards)
designed for aggregation across load
modules.
Optixia 12 12 slots for load modules. Modular Rack

XM12 subcomponents for higher serviceability.
Higher port density. Hot-swappable load
modules. DVD-ROM drive. The XM12 High
Performance verstion (OPTIXIAXM12-02)
has two 2.0 kW power suplies.
Optixia 2 Two slots for load modules. Modular Desktop/

XM2 subcomponents for higher serviceability. Rack
Higher port density. Hot-swappable load
modules. DVD-ROM drive.
DVD Drive is not present in newer versions
of XM2 chassis (starting with 941-0003-07
and 941-0023-02).
Optixia 16 16 slots for load modules. Modular Rack

X16 subcomponents for higher serviceability.
Hot-swappable load modules. DVD-ROM
drive.
Optixia 10 10 slots for large high-density load Free

XL10 modules. Redundant power supplies. Hot- standing/
swappable load modules. CD-ROM drive. Rack
1600T 16 16 slots for load modules. Rack

Floppy drive.
400T 4 Four slots for load modules. Desktop/

Floppy drive. Rack

Ixia Load Modules
Table 1-1. Ixia Chassis Comparison
Chassis # of Special Feature Mounting

slots
250 2 Built-in 10/100/1000 TXS4 or 1000 SFPS4 Desktop/

port. Floppy drive. Portable
100 1 Built-in GPS for worldwide synchronization Rack
Note: Based on power requirements, Ixia chassis do not support all possible
mixes of load modules. The Ixia chassis notifies you of conflicts on chassis
power-up. Contact Ixia support for configuration verification.
Ixia Load Modules

Ixia offers a number of load modules that provide one to 24 ports of technology
and media dependent interfaces to DUTs. The load modules are divided into
logical families. Each family of load modules is discussed in details in its own
chapter in this manual.
• IXIA Impairment Load Modules: Offer 4x1GE, 4x10GE, or 2x40GE Ethernet
interfaces that can emulate 64, 32, or 8 unidirectional network clouds
respectively
• IXIA Xcellon-Lava Load Modules: Provide testing of high-density data center
40 Gigabit Ethernet (40GbE) and 100 Gigabit Ethernet (100GbE) network
equipments.
• IXIA 40/100 Gigabit Ethernet Load Modules: Provide 40 and 100 Gbps
Ethernet with a variety of interfaces.
• IXIA 10 Gigabit Ethernet Load Modules: Provide 10 Gbps Ethernet with a
variety of interfaces.
• IXIA 1GbE and 10GbE Aggregation Load Modules: Provide 10 Gbps and 1
Gbps Ethernet on the same module with a variety of interfaces.
• IXIA 10GE LAN/WAN and OC 192 POS Load Modules: Provide Optical
Carrier interfaces that operate in concatenated mode at OC192 or 10 Gigabit
Ethernet rates. One of the following modes can be used:
• 10 Gigabit Ethernet LAN
• 10 Gigabit Ethernet WAN
• Packet over Sonet (POS)
• Bit Error Rate Testing (BERT)
• IXIA 10/100/1000 Load Modules: Provide either 10 Mbps, 100 Mbps, or 1000
Mbps Ethernet speeds with auto-negotiation (except for Gigabit).
• IXIA Gigabit Load Modules: Provide 1000 Mbps Ethernet speeds.
• IXIA OC12 ATM/POS Load Modules: Provide Asynchronous Transfer Mode
(ATM) functions.

1 Ixia Load Modules
• IXIA 10/100 Load Modules: Utilize a copper interface and provide either 10
Mbps or 100 Mbps Ethernet speeds with auto-negotiation with or without a
per-port CPU.
• IXIA 100 Load Modules: Utilize a fiber interface and provide 100 Mbps
Ethernet with auto-negotiation.
• IXIA OC12 ATM/POS Load Modules: Enables high performance testing of
routers and broadband aggregation devices such as DSLAMs and PPP
termination systems.
• IXIA OC12c/OC3c Load Modules: Provide selectable Optical Carrier
interfaces that operate in concatenated mode at OC3 or OC12 rates. Packet
over Sonet (POS) is implemented on the interfaces.
• IXIA OC48c Load Modules: Provide Optical Carrier interfaces that operate in
concatenated mode at OC48 rates. Either Packet over Sonet (POS) or Bit
Error Rate Testing (BERT) may be performed.
• IXIA Power over Ethernet Load Modules: Provide 10/100/1000 port
emulation of network Powered Devices.
• IXIA Stream Extraction Modules: Provide 10/100/1000 stream capture and
analysis of network devices.
• IXIA FCMGXM Load Modules: Deliver high-density converged data center
infrastructure for testing end-to-end Fibre Channel and Fibre Channel over
Ethernet (FCoE) testing.
• IXIA Xcellon-Flex Load Modules: Deliver high-density, high performance
test solutions.
• IXIA Xcellon-Multis Load Modules: Deliver highest density 40G and 100G
higher speed Ethernet (HSE) test equipment, providing more flexible test
coverage and 4x100GE, 12x40GE, or dual-rate 40GE/100GE, all in a single-
slot load module.
• IXIA PerfectStorm Load Modules: Provides a scalable solution for testing
converged multi-play services, application delivery, and network security
platforms for both wired and wireless networks
• IXIA Xdensity XDM10G32S/8S Load Modules: Provide test solutions for high
density 10GE converged data center switches and routers.
Load modules with part numbers that contain -3 or -M are limited in their
functionality. Newer boards also may have an ‘L’ before the last number in their
part number, signifying the same limited functionality (that is, LSM10GL1-01).
In general, -3 and -M modules do not have the following functions:
• Flows, except where Streams are not supported
• Advanced Streams (however, included with OC48C-3)
• Packet Groups (however, included with OC48C-3)
• Latency (however, included with OC48C-3)
• Sequence Checking (however, included with OC48C-3)
• Data Integrity (however, included with OC48C-M)
• Multiple DLCIs on OC48c load modules
• Convert to streams in capture view

Ixia Load Modules
• Protocol Server for router testing
‘L’ modules do not have the following functions:

• Advanced Routing functions
• Receive port filtering
Reduced vs. Full Some load modules are available in a Reduced Features version, which is
Feature identified by an ‘R’ before the last number in their part number. The following
table illustrates the differences for one family of cards, NGY.
Table 1-2. Comparison of Full/Reduced Features, NGY Cards
Standard eXtra eXtra Reduced

Performance Performance
8-port 2/4-port
PCPU 800 MHz 800MHz 1GHz 400MHz
PCPU Memory 512MB 1GB 1GB 128MB
Capture Memory 512MB 350MB 350MB 64MB
Table UDF Entries 1M 1M 1M 32K
UDF Range List 512K 512K 512K 256K
UDF Value List 512K 512K 512K 256K

Entries
PGID 1M 1M 1M 64K
Load Module The load module names used within the IxExplorer software differ slightly from
Names the load module names used in Ixia marketing literature. Table 1-3 on page 1-7
describes the mapping from load module names to the names in the Ixia price list
and those used in IxExplorer. The reverse mapping, alphabetized, is shown in
Table 1-4 on page 1-12.
Note: Load modules without a price list column entry are no longer available for
purchase.
Table 1-3. Load Module to IxExplorer Card Name Map

Family Load Module Price List Names IxExplorer Card Name
10/100 LM100TX LM100TX 10/100

Ethernet
LM100TX3 n/a 10/100-3
LM100TX8 LM100TX8 10/100 TX8
LM100TXS8 LM100TXS8 10/100 TXS8
LM100MII n/a 10/100 MII

1 Ixia Load Modules

10/100/1000 ALM1000T8 ALM1000T8 10/100/1000 ALM T8

Ethernet
ASM1000XMV12X-01 ASM1000XMV12X-01 10/100/1000 ASM XMV12X
Xcellon-Ultra XP-01 Xcellon-Ultra XP Xcellon-Ultra XP
Xcellon-Ultra NP-01 Xcellon-Ultra NP Xcellon-Ultra NP
Xcellon-Ultra NG-01 Xcellon-Ultra NG Xcellon-Ultra NG
CPM1000T8 CPM1000T8 10/100/1000 CPM T8
ELM1000ST2 ELM1000ST2 10/100/1000 ELM ST2
LM1000T-5 LM1000T-5 Copper 10/100/1000
LM1000TX4 LM1000TX4 10/100/1000 TX4
LM1000TXS4 LM1000TXS4, 10/100/1000 TXS4

LM1000TXS4-256 10/100/1000 TXS4-256
LM1000STX2 LM1000STX2 10/100/1000 STX2
LM1000STX4 LM1000STX4 10/100/1000 STX4
LM1000STXS2 LM1000STXS2 10/100/1000 STXS2
LM1000STXS4 LM1000STXS4, 10/100/1000 STXS4

LM1000STXS4-256 10/100/1000 STXS4-256
LM1000SFP4 LM1000SFP4 1000 SFP4
LM1000SFPS4 LM1000SFPS4 1000 SFPS4

LM1000SFPS4-256 1000 SFPS4-256
LSM1000XMS12-01 LSM1000XMS12-01 10/100/1000 XMS12

LSM1000XMSR12-01 LSM1000XMSR12-01 10/100/1000 XMSR12
LSM1000XMV16-01 LSM1000XMV16-01 10/100/1000 LSM XMV16

LSM1000XMVR16-01 LSM1000XMVR16-01 10/100/1000 LSM XMVR16



LSM1000XMSP12-01 LSM1000XMSP12-01 10/100/1000 LSM XMSP12
LSM1000XMVDC4-01 LSM1000XMVDC4-01 10/100/1000 LSM XMVDC4
LSM1000XMVDC4-NG LSM1000XMVDC4-NG 10/100/1000 LSM XMVDC4NG

Ixia Load Modules

LSM10/100/ LSM10/100/ LSM10/100/1000XMVDC16NG

1000XMVDC16NG 1000XMVDC16NG
OLM1000STX24 OLM1000STX24 10/100/1000 STX24
OLM1000STXS24 OLM1000STXS24 10/100/1000 STXS24
100MB LM100FX n/a 100 Base FX MultiMode

Ethernet
LM100FXSM n/a 100 Base FX SingleMode
Gigabit LM1000SX n/a Gigabit
LM1000SX3 n/a Gigabit-3
LM1000GBIC n/a GBIC
LM1000GBIC-P1 n/a GBIC-P1
ATM LM622MR, LM622MR w/ ATM 622 Multi-Rate

LM622MR-512 OPTATMMR,
LM622MR-512 w/
OPTATMMR
LM622MR w/ ATM/POS 622 Multi-Rate

OPTPOSMR
LM622MR w/ ATM/POS 622 Multi-Rate

OPTATMMR+
OPTPOSMR
OC12c/OC3c LMOC12c/LMOC3c LMOC12c, LMOC12cSM OC12c/OC3c POS
OC48 LMOC48cPOS OC48c POS
LMOC48cPOS-M OC48c POS-M
LMOC48cBERT OC48c BERT
LMOC48POS/BERT OC48c POS/BERT
LMOC48VAR OC48c POS VAR
MSM2.5G1-01 MSM2.5G1-01 2.5G MSM
OC192 LMOC192cPOS OC192c POS
LMOC192cVSR-POS OC192c VSR POS
LMOC192cBERT OC192c BERT
LMOC192cVSR-BERT OC192c VSR BERT
LMOC192cPOS+BERT OC192c POS/BERT
LMOC192cVSR- OC192c VSR POS/BERT

POS+BERT
LMOC192cPOS+WAN OC192c POS/10GE WAN
LMOC192cPOS+BERT+ OC192c POS/BERT/10GE WAN

WAN

1 Ixia Load Modules

10GE LM10GELAN 10GE LAN
LM10GELAN-M 10GE LAN-M
LM10GEWAN 10GE WAN
LSM10G1-01 LSM10G1-01 10GE LSM
LSM10GL1-01 LSM10GL1-01 10GE LSM LAN XFP
LSM10GMS-01 LSM10GMS-01 10GE LSM MACSec
LSM10GXL6-01 LSM10GXL6-01 10GE LSM XL6
LM10GEXAUI 10GE XAUI
LM10GEXAUI+ 10GE XAUI/BERT

BERT
LM10GEXAUI BERT only 10GE XAUI BERT
LM10GEXENPAK 10GE XENPAK
LM10GEXENPAK-M 10GE XENPAK-M
LM10GEXENPAK+BERT 10GE XENPAK/BERT
LM10GEXENPAK- 10GE XENPAK-M/BERT

MA+BERT
LM10GEXENPAK BERT 10GE XENPAK BERT

only
LM10G LM10GUEF, LM10GUEF- 10G UNIPHY,

FEC, LM10GUEF-P, 10G UNIPHY-P
LM10GULF, LM10GUVF 10G UNIPHY-XFP
w/OPT10GELWAN 10G UNIPHY-FEC
LSM10GXM3-01 LSM10GXM3-01 10GE LSM XM3

LSM10GXMR3-01 LSM10GXMR3-01 10GE LSM XMR3

LSM10GXM8XP-01 LSM10GXM8XP-01 10GE LSM XM8XP
LSM10GXM8S-01 LSM10GXM8S-01 10GE LSM XM8S
LSM10GXMR8S-01 LSM10GXMR8S-01 10GE LSM XMR8S
LSM10GXM8GBT-01 LSM10GXM8GBT-01 10GE LSM XM8 10GBASE-T
LSM10GXMR8GBT-01 LSM10GXMR8GBT-01 10GE LSM XMR8 10GBASE-T
NGY-NP8-01 NGY-NP8-01 NGY-NP8 (10GE LSM XM8-NP)


Ixia Load Modules


MSM10G1-02 MSM10G1-02 10G MSM
ASM1000XMV12X-01 ASM1000XMV12X-01 10/100/1000 ASM XMV12X
Xcellon-Ultra XP-01 Xcellon-Ultra XP Xcellon-Ultra XP
Xcellon-Ultra NP-01 Xcellon-Ultra NP Xcellon-Ultra NP
Xcellon-Ultra NG-01 Xcellon-Ultra NG Xcellon-Ultra NG
40GE HSE40GETSP1-01 HSE40GETSP1-01 40GE LSM XMV
100GE HSE100GETSP1-01 HSE100GETSP1-01 100GE LSM XMV
40/100GE HSE40GETSP1-01 HSE40GETSP1-01 40GE LSM XMV
HSE100GETSP1-01 HSE100GETSP1-01 100GE LSM XMV
HSE40/100GETSP1-01 HSE40/100GETSP1-01 40/100GE LSM XMV
HSE40GEQSFP1-01 HSE40GEQSFP1-01 40GE LSM XMV QSFP
Power over PLM1000T4-PD PLM1000T4-PD Power over Ethernet PLM 20W

Ethernet
LSM1000POE4-02 LSM1000POE4-02 Power over Ethernet PLM 30W
Stream AFM1000SP-01 AFM1000SP-01 AFM - Stream Extraction Module

Extraction
Module
Voice Quality VQM01XM VQM01XM Voice Quality Resource Module
Excellon-Flex FlexAP10G16S FlexAP10G16S
FlexFE10G16S FlexFE10G16S
10GE Xdensity XDM10G32S

Ethernet
ImpairNet EIM10G4S EIM10G4S
EIM1G4S EIM1G4S
Xcellon-Lava Lava AP40/100GE 2P Lava AP40/100GE 2P
Lava AP40/100GE 2P Lava AP40/100GE 2P

1 Ixia Load Modules
Table 1-4. IxExplorer Card Name to Load Module Name Map (Alphabetical)
IxExplorer Card Name Load Module Price List Names
10/100 LM100TX LM100TX
10/100-3 LM100TX3 LM100TX3
10/100 MII LM100MII
10/100 TX8 LM100TX8 LM100TX8
10/100 TXS8 LM100TXS8 LM100TXS8
10/100/1000 ALM T8 ALM1000T8 ALM1000T8
10/100/1000 ASM XMV12X ASM1000XMV12X-01 ASM1000XMV12X-01
10/100/1000 CPM T8 CPM1000T8 CPM1000T8
10/100/1000 ELM ST2 ELM1000ST2 ELM1000ST2
10/100/1000 LSM XMSP12 LSM1000XMSP12-01 LSM1000XMSP12-01
10/100/1000 LSM XMVDC4 LSM1000XMVDC4-01 LSM1000XMVDC4-01
10/100/1000 LSM XMVDC4NG LSM1000XMVDC4-NG LSM1000XMVDC4-NG
10/100/1000 LSM XMVDC16NG 10/100/1000 LSM 10/100/1000 LSM

XMVDC16NG XMVDC16NG
10/100/1000 LSM XMV16 LSM1000XMV16-01 LSM1000XMV16-01

10/100/1000 LSM XMVR16 LSM1000XMVR16-01 LSM1000XMVR16-01



10/100/1000 STX2 LM1000STX2 LM1000STX2
10/100/1000 STX24 OLM1000STX24 OLM1000STX24
10/100/1000 STX4 LM1000STX4 LM1000STX4
10/100/1000 STXS2 LM1000STXS2 LM1000STXS2
10/100/1000 STXS24 OLM1000STXS24 OLM1000STXS24
10/100/1000 STXS4 LM1000STXS4 LM1000STXS4,

10/100/1000 STXS4-256 LM1000STXS4-256
10/100/1000 TX4 LM1000TX4 LM1000TX4
10/100/1000 TXS4 LM1000TXS4 LM1000TXS4,

10/100/1000 TXS4-256 LM1000TXS4-256

Ixia Load Modules
10/100/1000 XMS12 LSM1000XMS12-01 LSM1000XMS12-01

10/100/1000 XMSR12 LSM1000XMSR12-01 LSM1000XMSR12-01
100 Base FX MultiMode LM100FX
100 Base FX SingleMode LM100FXSM
1000 SFP4 LM1000SFP4 LM1000SFP4
1000 SFPS4 LM1000SFPS4 LM1000SFPS4,

1000 SFPS4-256 LM1000SFPS4-256
2.5G MSM MSM2.5G1-01 MSM2.5G1-01
10G MSM MSM10G1-02 MSM10G1-02
10G UNIPHY, LM10G LM10GUEF,

10G UNIPHY-P LM10GUEF-FEC,
10G UNIPHY-XFP LM10GUEF-P,
10G UNIPHY-FEC LM10GULF,
LM10GUVF
w/ OPT10GELWAN
10GE LAN LM10GELAN
10GE LAN-M LM10GELAN-M
10GE LSM LSM10G1-01 LSM10G1-01
10GE LSM LAN XFP LSM10GL1-01 LSM10GL1-01
10GE LSM MACSec LSM10GMS-01 LSM10GMS-01
10GE LSM XL6 LSM10GXL6-01 LSM10GXL6-01
10GE LSM XM3 LSM10GXM3-01 LSM10GXM3-01

10GE LSM XMR3 LSM10GXMR3-01 LSM10GXMR3-01

10GE LSM XM8XP LSM10GXM8XP-01 LSM10GXM8XP-01
10GE LSM XM8S LSM10GXM8S-01 LSM10GXM8S-01
10GE LSM XMR8S LSM10GXMR8S-01 LSM10GXMR8S-01
10GE LSM XM8 10GBASE-T LSM10GXM8GBT-01 LSM10GXM8GBT-01
10GE LSM XMR8 10GBASE-T LSM10GXMR8GBT-01 LSM10GXMR8GBT-01
NGY-NP8 NGY-NP8-01 NGY-NP8-01


1 Ixia Load Modules

10GE WAN LM10GEWAN LM10GE123F,

LM10GE124F
10GE XAUI LM10GEXAUI
10GE XAUI BERT LM10GEXAUI BERT only
10GE XAUI/BERT LM10GEXAUI+

BERT
10GE XENPAK LM10GEXENPAK
10GE XENPAK BERT LM10GEXENPAK BERT

only
10GE XENPAK/BERT LM10GEXENPAK+BERT
10GE XENPAK-M LM10GEXENPAK-M
10GE XENPAK-M/BERT LM10GEXENPAK-

MA+BERT
40GE LSM XMV HSE40GETSP1-01 HSE40GETSP1-01
100GE LSM XMV HSE100GETSP1-01 HSE100GETSP1-01
40/100GE LSM XMV HSE40/100GETSP1-01 HSE40/100GETSP1-01
40GE LSM XMV QSFP HSE40GEQSFP1-01 HSE40GEQSFP1-01
Xcellon-Ultra NP Xcellon-Ultra NP-01 Xcellon-Ultra NP
Xcellon-Ultra XP Xcellon-Ultra XP-01 Xcellon-Ultra XP
Xcellon-Ultra NG Xcellon-Ultra NG-01 Xcellon-Ultra NG
AFM1000SP-01 AFM Stream Extraction AFM1000SP-01

Module
ATM 622 Multi-Rate LM622MR LM622MR w/OPTATMMR
ATM/POS 622 Multi-Rate LM622MR w/OPTPOSMR
ATM/POS 622 Multi-Rate LM622MR w/

OPTATMMR+
OPTPOSMR,
LM622MR-512 w/
OPTATMMR+
OPTPOSMR
Copper 10/100/1000 LM1000T-5 LM1000T-5
GBIC LM1000GBIC
GBIC-P1 LM1000GBIC-P1

Ixia Load Modules
Gigabit LM1000SX
Gigabit-3 LM1000SX3
OC12c/OC3c POS LMOC12c/LMOC3c LMOC12c, LMOC12cSM
OC192c BERT LMOC192cBERT
OC192c POS LMOC192cPOS
OC192c POS/10GE WAN LMOC192cPOS+WAN
OC192c POS/BERT LMOC192cPOS+BERT
OC192c POS/BERT/10GE WAN LMOC192cPOS+BERT+W

AN
OC192c VSR BERT LMOC192cVSR-BERT
OC192c VSR POS LMOC192cVSR-POS
OC192c VSR POS/BERT LMOC192cVSR-

POS+BERT
OC48c BERT LMOC48cBERT
OC48c POS LMOC48cPOS
OC48c POS VAR LMOC48VAR
OC48c POS/BERT LMOC48POS/BERT
OC48c POS-M LMOC48cPOS-M
Power over Ethernet LM1000T4-PD LM1000T4-PD
Voice Quality Resource Module VQM01XM VQM01XM

1 Ixia Load Module Properties
Ixia Load Module Properties

The Ixia load modules, or load modules, support a wide range of features, which
are described in Table 1-5.
The full set of supported features per card is described in the spreadsheet Port
Features by Port Type on the Ixiacom.com website, under Support/User Guides/
Spreadsheets.
Table 1-5. Ixia Load Module Feature Descriptions
Feature Feature Usage

Category
Basic Local CPU Each port on the card is supported by an

individual CPU for use in protocol server and
other sophisticated operations.
Layer 2/3 Only The card only supports Layer 2 and 3 control
and operation. No protocols except ARP and
PING are supported.
Layer 7 Only The card only supports Layer 7 usage

through the local CPU. This type of card is
generally only useful for application testing
as in IxLoad and Chariot.
Statistics Checksum errors Support generation and checking of special

Selection (IPv4/TCP/UDP) checksums for IPv4, TCP, and UDP packets.
Data integrity Supports data integrity generation and

checking.
Tx Duration Supports the generation of a transmit

duration statistic.
Per stream stats Statistics are available for each stream.
Receive Capture Received data may be captured to a capture

Modes buffer.
Packet groups Supports generation of packet group IDs in

packets.
Latency S&Fwd Latency measurement offers the option of

LB to FB measuring the time from last data bit out to
first data bit in
Latency S&Fwd Latency measurement offers the option of

LB to FP measuring the time from last data bit out to
first preamble bit in


Category
Inter-arrival Jitter Inter-Arrival Time (IAT) compares the time

between PGID packet arrivals. In this case,
when a packet with a PGID is received, the
PGID is examined. If a packet has already
been received with the same PGID, then the
timestamp of the previous packet is
subtracted from the current timestamp.
The interval between the timestamps is the
jitter, and it is recorded for statistical
purposes.
Delay Variation Offers the option of measuring variation

between latency of consecutive frames.
MEF Frame Delay Measurement method: First data bit in to

DUT; last data bit out of DUT.
Forwarding Delay Measurement method: Last data bit in to

DUT; last data bit out of DUT.
Advanced PG A set of features which allow packet group

Filter matching to ignore or mask:
• Group ID
• Signature
• Filter data
Round-trip flows Supports calculation of round-trip flows.
Data integrity Supports data integrity generation and

checking.
First time stamp Supports first time stamp operation.
Tx/Rx Time Stamp Allows the system to use the time stamp of
Mode the last bit of the packet; this is useful when
multiple rates are present in the network
topology.
Sequence Supports packet sequence generation and

checking verification.
Sequence When packet groups are used, allows

checking per sequence checking generation and
packet ID verification.
ISL encapsulation Receive side of port can accommodate ISL

encapsulation on receive side.
Small packets Supports the ability to capture packets

smaller than a legal packet; captured data
may be corrupted when this feature is used.
Wide packet This feature allows ports, which utilize packet

groups groups, to extend the number of bits in the
PGID to 17 bits (or more).


Category
PRBS Mode When the Receive Mode is set to PRBS

mode, both Wide Packet Groups and
Sequence Checking are automatically
enabled. In PRBS mode, all latency-related
statistics are removed and the following per
PGID statistics are added:
• PRBS Bits Received
• PRBS Errored Bits
• PRBS BER
Split PGIDs Allows for the creation of split PGID data.
Latency bins Latency data may be categorized by latency

values for each packet group.
Time bins Latency may be measured over time.
Echo Ports with this feature may echo all received

traffic as transmitted packets.
Preamble capture Frame’s preamble may be included in the

capture buffer.
Simulate cable A cable disconnect state may be simulated.

disconnect
Flexible Pattern Allows to set the Filter/Trigger pattern to a

Offset specific offset.
Multi Switched- Allows for the detection of loss/duplicate

Path packets.
Intrinsic Latency Reduces the measured latency by the

Adjustment amount of latency that is induced by the test
equipment itself (not the DUT). Retrieves
pre-determined latency value for a ‘known’
transceiver, or calculates and stores that
value for a ‘new’ transceiver.
Misdirected Mask Sets the signature mask used for identifying

misdirected packets.
Rate Monitoring Enables testing convergence times and

(convergence) service interruptions.
Auto-Detect On the receive side, automatically detects a

Instrumentation specified signature and Instrumentation
parameters for Data Integrity, Sequence
Checking, or Latency for streams generated
with Automatic Instrumentation Offsets using
Ixia software applications.
TSO/LRO Transmit Segmentation Offload/Large

Receive Offload (TSO/LRO) operation mode.


Category
Transmit Packet streams Supports the generation of packet streams.

Modes
Packet flows Supports the generation of packet flows.
Advanced Supports the operation of the advanced

scheduler scheduler, which allows inter-mixing of
multiple packet streams.
Forced collisions Supports the insertion of forced collisions.
Tx Data integrity Supports data integrity generation and

checking.
Odd preamble Supports the ability to send a preamble with

an odd number of bytes. This is not
applicable to boards with dual PHYs
(Ethernet/Fiber) when a port is in fiber mode.
Gap time units The inter-frame, -burst, and -stream gaps

can be programmed in discreet units of time
as opposed to indirectly through a
percentage of maximums frame rate.
Gap byte count Gaps may be expressed as a number of

bytes.
Modifiable The packet’s preamble content may be

preamble modified.
On 10GE load modules that support this
feature there are two options: modify the 7
rightmost bytes of the 8 byte preamble or
modify the inner 6 bytes of the 8 byte
preamble.
Forced minimum In advanced scheduler mode, a minimum

IPG gap may be enforced.
Increment frame Frame sizes may be incremented by an

size by N arbitrary value between transmitted frames.
Increment/ DA and SA values may be incremented or

Decrement DA/SA decremented by an arbitrary value between
by N transmitted frames.
Random data on When random data is generated within a

even offset only frame’s content, the random data may only
be placed at even byte boundaries.
Insert bad TCP Supports the generation of bad TCP

checksum checksums.
Checksum Overrides IPv4, IPv6 and TCP checksums.

Override


Category
Frequency offset The frequency for the card as a whole may

be modified a few percent from nominal.
Echo The port echoes all received packets.
Flexible Time The position of the time stamp in transmitted

Stamp packets may be repositioned.
Protocol Offset The beginning of the IP (or other) protocol

header may be repositioned so as to
accommodate leading headers, as in PPP.
Random IPG The IPG between packets may be set to a

random value.
Copper RJ45/Fiber The port has the ability to transmit and

SFP receive from either its copper RJ-45 Ethernet
or Fiber SFP optic interface.
Weighted Random The port has the ability to generate packets

Frame Size with random frame sizes. The frame sizes
are programmed through a set of frame sizes
and weightings.
Scheduled The duration of the transmit operation may

duration be scheduled for a number of seconds.
Simulate cable A cable disconnect state may be simulated.

disconnect
Repeatable Allows for repeating randomly generated

Random Streams stream data.
GRE An IP transport protocol available for

insertion into transmitted streams.
Stacked VLANs Allows for sending multiple VLAN IDs in a

single packet.
Tx Ignore Link Allows for transmission of packets with the

link down.
Protocol Pad Allows for a data pad to be added before the

protocol head field in a frame.
Dynamic Rate Allow rate change without stopping transmit.

Change
Dynamic Frame Allow frame size change without stopping

Size Change transmit.
New Incrementing Allow packets/burst setting in incrementing

Frame Size frame size mode


Category
Auto-Detect On the transmit side, automatically

Instrumentation configures a specified signature and
Instrumentation parameters for Data
Integrity, Sequence Checking, Latency, or
PRBS for streams generated for Ixia
software applications that use Automatic
Instrumentation Offsets.
Intrinsic Latency Reduce the measured latency by the amount

Adjustment of latency that is induced by the test
equipment itself (not the DUT). Retrieves
pre-determined latency value for a ‘known’
transceiver, or calculates and stores that
value for a ‘new’ transceiver.
PRBS When the port is in PRBS mode, all latency-

related statistics are removed and the
following per-PGID statistics are added:
• PRBS Bits Received
• PRBS Errored Bits
• PRBS BER
TSO/LRO Transmit Segmentation Offload/Large

Receive Offload (TSO/LRO) operation mode.
User Odd offset UDFs are allowed to start at an odd offset.

Defined
Fields
(UDF)
Overlap UDFs may overlap within a 4-octet boundary.

Otherwise UDFs must start at least 4 octets
apart.
Cascade UDFs may continue from previous stream

values.
Cascade from self UDFs may continue from previous values on

the same UDF.
Split UDFs may be split into multiple 8-bit and 16-

bit counters.
Bit mask UDFs output data may be masked with an

arbitrary bit mask. Otherwise limitations on
the number of changes of bits applies.
Incr By N Allows UDFs to increment by an arbitrary

value.
UDF5 The port has a fifth UDF.


Category
Advanced The port supports additional UDF features,

including:
Nested counters
Linked lists
Step size
Value list
Range list
IPv4 The port supports UDF - IPv4 type counting.
Range List The port supports UDF generated values

over a list of value ranges.
Value List The port supports UDF generated values

from a list of values.
Nested Counter The port supports UDF generated values

from two nested counters.
Table The port supports a UDF that derives values

from a table of offsets and values, by packet.
Chained UDFs The port supports the ability to chain from a

specified UDF.
Protocol Pad Allows for a data pad to be added before the

protocol head field in a frame.
POS/ POS Supports Packet over SONET operation.

BERT
BERT Supports Bit Error Rate Testing through the

generation and verifications of patterns.
Channelized Support channelized BERT testing.

BERT
BERT error Supports BERT error insertion.

insertion
DCC Supports additional DCC channel streams.
SRP Supports Serial Reuse Protocol—passive

receive.
SRP Full Supports Serial Reuse Protocol—active

send/receive.
RPR Supports Resilient Packet Ring operation.
FEC Support Forwarding Error Correction.
GFP Supports the Generic Framing Protocol.
SONET error Support the insertion of Sonet errors.

insertion list


Category
Multiple DLCIs Supports the use of more than one DLCI in

frame relay testing.
CJPAT/CRPAT Supports generated CJPAT and CRPAT

frame data patterns.
10 Gigabit OC192 Supports OC192 POS operation.

Ethernet
WAN Supports 10 GE WAN operation.
LAN Supports 10 GE LAN operation.
XAUI Supports 10GE XAUI interface.
XENPAK Supports 10GE XENPAK interface.
LASI Supports Link Alarm Status Interrupt.
XFP Supports an XFP interface.
SFP Supports an SFP (small form-factor

pluggable) transceiver interface.
UNIPHY Supports UNIPHY operation, which allows

the same port to operate in LAN, WAN, POS
and BERT modes.
Lane skew Supports the ability to skew multiple PCS

(Physical Coding Sublayer) lanes.
Set pause The destination for pause control packets

destination may be set.
address
Link Fault Supports the link fault signalling protocol.

Signalling
Gap Control Mode Allows for the selection of the gap control
algorithm, as defined by IEEE.
Pre-Emphasis Allows for boosting transmit signal.
MACSec Supports MACSec functionality.

Media Access Control Security (MACsec) is
a L2 protocol which authenticates the entire
L2 frame (except for the Ethernet CRC) and
provides confidentiality for all or some of the
MACsec data segment. This protocol is
defined in IEEE 802.1AE
Protocol Basic Routing Supports basic routing protocols, including

Server BGP, IS-IS and OSPF, but none of those in
the list for Advanced Routing.
DHCP Supports the DHCP protocol.


Category
DHCPv6 Supports the DHCPv6 protocol.
Advanced Routing Supports advanced routing protocols:

(note 1) • BGP-IPv6
• IGMP (new) with IPMPv3
• ISIS-IPv6
• OSPFv3
• PIM-SM
• Layer 2 VPN (LDP)
• Layer 3 VPN (BGP)
• LDP
• MLD
• RIPng
ARP Supports ARP generation and receipt

handling.
Gratuitous ARP Gratuitous ARP is sent by the host when its

IP to MAC mapping changes, so that
everybody else on the subnet updates their
ARP tables.
ARP rate control The rate at which multiple ARP packets are
transmitted may be controlled.
IGMP rate control The rate at which multiple IGMP packets are
transmitted may be controlled.
PING Supports PING generation and receipt.
FCoE/NPIV Supports Fibre Channel over Ethernet and

N_Port_ID Virtualization.
PTP Supports Precision Time Protocol.
RTP Supports Real-time Transport Protocol
Notes:
1. On older OC48c, OC192c and 10GE modules, these protocols require that the
ports have been upgraded to 128MB of CPU memory.

Card Properties
Card Properties
Details about the card characteristics described in Table 1-6 are presented in the
chapters about specific load modules.
Table 1-6. Card Specifications
Specification Usage
# ports The number of ports supported by the card(s).
-3/-M/L Card Available Whether a limited feature card is available.
L2/L3 Card Available Whether a Layer 2/3 only card is available.
Layer 7 Card Available Whether a Layer 7 only card is available.
Data Rate The choice of data rates offered by the card.
Connector/Frequency-Mode The connector type used on the card. For optical

connections, the light frequency used and
whether the fiber is used for singlemode or
multimode.
Capture buffer size The size of each port’s capture buffer.
Captured packet size The range of packet sizes that may be captured
on the card.
Streams per port The number of streams available on each port.
Flows per port The number of stream flows available on each

port. If available, this is always 15,872.
Advanced streams The number of advanced streams available on

each port.
Preamble size: min-max The range of sizes, in bytes, for generated

preambles.
Frame size: min-max The range of sizes, in bytes, for generated

frames.
Inter-frame gap: min-max The gap between frames, expressed as a range

of time.
Inter-burst gap: min-max The gap between bursts of frames, expressed as

a range of time.
Inter-stream gap: min-max The gap between streams, expressed as a range

of time. Sometimes expressed as a percentage
of the maximum rate.

1 Card Properties
Table 1-6. Card Specifications
Specification Usage
Latency The accuracy of latency operations.
Intrinsic Latency Adjustment Reduce the measured latency by the amount of

latency that is induced by the test equipment
itself (not the DUT). Retrieves pre-determined
latency value for a ‘known’ transceiver, or
calculates and stores that value for a ‘new’
transceiver.
Number of captured packets, an important characteristic, cannot be expressed as

a simple number. It is dependent on a number of factors as mentioned in the
following list:
• Size of the capture buffer
• Size of the captured packet
• Size of the capture slice, set by you
• Memory used by other functions
• Memory overhead per captured packet
The general equation is:

# of captured packets = (size of capture buffer) -
(memory used by other functions)
(min (captured packet, capture slice) + (per packet
overhead)
To get an idea of the memory available for packet capture, a set of simple
experiments can be run. For example, Table 1-7 indicates the measured number
of packets captured for different packet sizes. The type of card used is an
LM100TX, which has a 2MB capture buffer. The buffer slice is set to 8191.
Table 1-7. Measured Number of Packets for an LM100TX Card
Packet Size Number of Memory Used by

Packets Captured Captured Packets
64 bytes 18,668 1,194,752
1K bytes 1,698 1,738,752
4K bytes 436 1,785,856
8K bytes 219 1,794,048
The experiment indicates that there is approximately 1.8 MB available for data
capture.

Card Properties
Maximum number The maximum number of PGIDs for designated load module families is provided
of PGIDs in Table 1-8.
Table 1-8.Maximum PGID Summary
Load Module Family Receive Mode Maximum Number
PGIDs1(Decimal)
LM100TX
Packet Group 57344
First Timestamp
LM1000GBIC
Packet Group 57344
Sequence Checking N/A
First Timestamp
LM100TXS8
Packet Group 65536
Packet Group + Sequence Checking 128
Capture + Sequence Checking 128
Wide Packet Group 131072
LM1000STXS4 and
LSM1000XMS12-01,
LSM1000XMSP12-01
Packet Group 65536
Wide Packet Group (Reduced Feature) 65536
LSM1000XMV family
(4, 8, 12, and 16-port)
Wide Packet Group/Wide Bin Mode 1048576
(Full Feature)
ASM1000XMV Wide Packet Group/Wide Bin Mode 1048576
LSM10G
including MSM10G and
MSM2.5G
100GE LSM XMV, Wide Packet Group 1048576

40GE LSM XMV, and
40/100GE LSM XMV

1 Card Properties
Table 1-8.Maximum PGID Summary

Load Module Family Receive Mode Maximum Number
PGIDs1(Decimal)
LM10G and LM10GE

Packet Group 65536
Sequence Checking 8192
LMOC-12
Packet Group 57344
Sequence Checking N/A
LMOC-48
Packet Group 65536
LMOC-192
Packet Group 1024
LM622MR
Packet Group 65536
LavaAP40/100GE
Data Integrity
Wide Packet Groups 1048576
Latency/Jitter
1. The maximum number of PGIDs is the maximum hardware PGID that can be
supported by a particular load module in a particular mode. If time bin, latency, or
other parameters are enabled, the maximum PGID that can be supported is
reduced.
All modules have a maximum 2048 time bins. All modules that support latency
bins have quantity 16 latency bins.

New in Version 6.60 EA Patch1
New in Version 6.60 EA Patch1

The following features are new in this release:
• XGS12 Chassis
For more information, see Chapter 7, XGS12 Chassis
• PerfectStorm Load Modules
For more information, see Chapter 36, IXIA PerfectStorm Load Modules
• Subscription Licensing model for IxVM ports
For more information, see Licensing.

1 New in Version 6.60 EA Patch1

Chapter 2: Theory of Operation:
2 General
This chapter discusses the unifying concepts behind the Ixia system. Both the
software and hardware structures, and their usage, are discussed. The chapter is
divided into the following major sections:
• Ixia Hardware on page 2-1
• IxExplorer Software on page 2-78
Ixia Hardware
This section discusses the range and capabilities of the Ixia hardware, including
general discussions of several technologies used by Ixia hardware. This section is
divided into the following general areas:
• Chassis Chain (Hardware) on page 2-2
• Chassis on page 2-4
• Load Modules on page 2-8
• Port Hardware on page 2-9
• Types of Ports on page 2-9
• Port Transmit Capabilities on page 2-47
• Port Data Capture Capabilities on page 2-66
• Port Transmit/Receive Capabilities on page 2-75
• Port Statistics Capabilities on page 2-76

Theory of Operation: General
2 Ixia Hardware
Chassis Chain At the highest level, the Ixia hardware is structured as a chain of different types
(Hardware) of chassis, up to 256 units. The chassis list is mentioned in the following table:
Table 2-1. Currently Available Ixia Chassis
Chassis Number of Load

Modules Supported
XG12 12 high density modules
Optixia XM12 12 high density modules
Optixia XM2 Two high density modules
Optixia XL10 10 large modules
Optixia X16 16 standard load modules
Ixia 100 One standard load

modules
Ixia 250 Two standard load

modules, plus a single
built-in 10/100/1000
Ethernet port.
Ixia 400T Four standard load

modules
Ixia 1600T 16 standard load modules
All non-Optixia chassis support load modules that each may contain one to 8
ports. Up to 16 ports per load module are supported on Optixia XM2 and XM12
chassis, and up to 24 ports are supported on Optixia XL10 load modules, which
can result in a very large number of ports for the overall system.
Multiple Ixia chassis are chained together through special Sync-out/Sync-in

cables that allow for port-to-port synchronization across locally connected
chassis in accordance with the specification mentioned in the Chassis Chain
Timing Specification section.

Ixia Hardware
Note: There are several rules that must be observed when constructing chassis
chains. If a rule is violated, chassis timing may not meet the specification.
• Sync cable length between two chassis in a chain should be less than or
equal to 6 feet.
• In a physical chassis chain, the Optixia chassis must be grouped together,
and the non-Optixia chassis must be grouped together; that is, the two types
can be on the same chassis chain, but cannot be intermingled. In a virtual
chain that consists of several physical chains, each physical chain must obey
this rule.
• Sequence numbers must be unique in a chain. Within a chain, there cannot
be duplicate sequence numbers.The master chassis must have the smallest
sequence value in the physical chain. The order of sequence numbers must
match the order of chassis (up to 99999). The numbers do not have to be
sequentially contiguous (1, 2, 3, and so on.) but they must be sequentially
increasing in value (1, 5, 8, and so on.)
• Certain load modules must be used in only the first 3 chassis in a chain.
These include LM100TXS8, LM100TXS2, LM100TX8, LM100TX2,
LM100TX, LM100TX1, LM100TX2, and LM100TX3. If these boards are used
in the fourth or later chassis in a chain, the network ports may not operate
reliably.
The following figure is a representation of an independent Ixia chassis chain and

control network. Chassis are chained together through their sync cables. The first
chassis in a chain has a Sync-out connection (but no Sync-in unless it is the
AFD1 GPS receiver), and is called the master chassis. All other chassis in the
chain are termed subordinates.
Figure 2-1. Ixia Chassis Chain and Control Workstation
Multiple, geographically-separated, independent chassis may be synchronized

with a high degree of accuracy by using an Ixia chassis. Specific chassis include
an integral GPS or CDMA receiver which is used for worldwide chassis

2 Ixia Hardware
synchronization. See Chassis Synchronization on page 2-5 for a complete

discussion of chassis timing.
Note: Plugging-in or removing the sync cable while IxServer is starting or

running can cause the IxServer to detect the change in the sync-in connection
and shut down. If this occurs, restart IxServer, then restart all Ixia applications.
Ports from the chassis are connected to the Device Under Test (DUT) using
cables appropriate for the media. Ports from any chassis may be connected to the
similar ports on the DUT. It is even possible to connect multiple independent
DUTs to different ports on different chassis.
Each chassis is driven by an Intel Pentium-based computer running Windows XP

Professional and Ixia-supplied software. Each chassis may be directly connected
to a monitor, keyboard, and mouse to create a standalone system, but it is typical
to connect all chassis through an Ethernet network and run the IxExplorer client
software or Tcl client software on one or more external control PC workstations.
IxExplorer client software runs on any Windows 2000/XP based system or
Windows Server 2003 (console usage or simultaneous remote terminal access for
multiple users). Tcl client software runs on Windows 2000/XP based systems
and several Unix-based systems.
Chassis Chain Timing Specification

• Chassis timing skew between like chassis <= +/- 40ns.
• Chassis timing skew between unlike chassis <= +/- 80ns.
Based on the above numbers:

• Maximum latency error between like chassis due to the chassis <= +/- 40ns.
• Maximum latency error between unlike chassis due to the chassis <= +/-
80ns.
Chassis Each Ixia chassis can operate as a complete standalone system when connected to
a local monitor, keyboard, and mouse. The interior of an Ixia 1600T chassis is
shown in the following figure.

Ixia Hardware
Figure 2-2. Ixia 1600T Interior View (Top View)
The PC embedded in the chassis system is an Intel-compatible computer system

which includes the following components:
• A Pentium processor
• Main memory
• Keyboard interface
• Mouse interface
• Internal connection to the Ixia Backplane
• Video interface capable of 1024 x 768 or greater resolution
• 10/100/1000 Mbps Ethernet Network Interface Card (NIC)
The Ixia Backplane is connected to the PC Motherboard, through an Ixia custom

PCI interface card, and to the card slots where the Ixia load modules are installed.
Chassis Synchronization
Measurement of unidirectional latency and jitter in the transmission of data from
a transmit port to a receive port requires that the relationship between time
signatures at each of the ports is known. This can be accomplished by providing
the following signals between chassis:
• Clock (frequency standard): This allows chassis to phase-lock their frequency
standards so that a cycle counter on any chassis counts the same number of
cycles during the same time interval. Each Ixia port maintains such a counter
from a common chassis-wide frequency standard.
• Reset: A means must exist to either discover the fixed offset between their
counters, or to simultaneously set the counters to a known value. You may
think of this as the zero reset.

2 Ixia Hardware
The use of both Reset and Phase Lock allow the establishment and maintenance
of a fixed time reference between two or more chassis and the ports supported by
the chassis.
In test setups where chassis and ports are physically close together, a sync cable
is used to connect chassis in a ‘chassis chain’ for synchronization operation.
In widely distributed applications, such as monitoring traffic characteristics over

a WAN, clock reference and/or reset signals cannot be transmitted between
chassis over a physical connection because of unknown delay characteristics. An
alternative means is required to satisfy these requirements.
Ixia has facilities that allow for the synchronization of independent Ixia chassis
located anywhere in the world by replacing the existing inter-chassis sync cables
with a widely available frequency and time standard supplied from an external
source. This source provides a reference time used to obtain accurate latency and
other measurements in a live global network. When geographically dispersed
chassis are connected in this way, the combination is called a virtual chassis
chain.
Physical Chaining
Independent Ixia 400T, 1600T, Optixia XL10, Optixia XM12, Optixia XM2, or
Optixia X16 chassis may synchronize themselves with other chassis as shown in
the following figure. The timing choices are explained in Table 2-2.
Figure 2-3. Physical Chaining
Table 2-2. Physical Chaining Timing Choices
Choice Usage
Internal Sync If a chassis is used in a standalone manner or the master

(Synchronous) of a chassis chain, it may generate its own start signal. In
general, there is insufficient timing accuracy between
timing masters for measurements over any distance. This
is also known as the Synchronous Timing mode.
Sync-In (SI) If a chassis is a subordinate, either directly connected to

the master chassis or further down the chain, it derives its
timing from the previous chassis’ Sync-Out (SO) signal.

Ixia Hardware
Virtual Chaining
If two chassis are separated by any significant distance, a sync-out/sync-in cable

cannot be used to connect them. In this case, either an Ixia Auxiliary Function
Device (AFD1) or an Ixia 100 chassis with built-in Global Positioning Satellite
(GPS), or an Ixia 100 or Ixia 250 with Code Division Multiple Access (CDMA)
is used, one attached to each chassis through sync-out/sync-in cables, as shown in
the following figure. The Ixia 100 maintains an accuracy of less than 150
nanoseconds when attached to a GPS antenna, or 100 microseconds when
attached to a CDMA receiver, and provides chassis to chassis synchronization.
Figure 2-4. Virtual Chaining
To generate traffic for system latency testing, the Ixia 100 or Ixia 250 chassis can
be used alone or in conjunction with another Ixia chassis, or the Ixia AFD1 (GPS
receiver) can be used with any other Ixia chassis. The timing features available
with these chassis are shown in Table 2-3 on page 2-7. A GPS antenna requires
external mounting. Refer to Appendix C, GPS Antenna Installation
Requirements for more information.
Table 2-3. Virtual Chaining Timing Choices
Choice Usage
GPS The Ixia 100 or ixia AFD1 requires connection to an external

antenna to ‘capture’ multiple GPS satellites. It maintains an accuracy
of less than 150 nano-seconds.
CDMA The CDMA cellular network transmits an accurate time signal.

CDMA (Code Division Multiple Access) cellular base-stations
effectively act as GPS repeaters. The Ixia 100-CDMA or Ixia 250
receives the CDMA signals passively from an external antenna (you
do not need to subscribe to any service) and decodes the embedded
GMT time signal. Using this approach, the CDMA chassis can be
time-synched to GMT. A CDMA antenna does not require external
mounting.

2 Ixia Hardware
The Sync-Out from a GPS or CDMA chassis is used to master a chassis chain at
a specific geographic location. Since the Ixia 100 or Ixia 250 chassis has all other
functions provided by the other Ixia chassis, it may also use independent timing
when not used to synchronize with other chassis at other locations.
Note: CDMA reception depends on signal availability and may be impacted by

cell location and chassis installation within the selected site. Consult your Ixia
representative to determine the best solution for your installation.
For more information, including a formula for Calculating Latency Accuracy for
AFD1 (GPS), see Chapter 19, Ixia GPS Auxiliary Function Device (AFD1).
Ixia Chassis Connections
A number of LEDs are available on the front panel of the Ixia 100 or Ixia 250, as
described in Table 2-4 on page 2-8.
Table 2-4. IXIA 100 Front Panel LEDs
LED Usage
Set Lock Three LEDs indicate three separate status events:

• 1: Indicates that the chassis is armed for a GPS sync event.
• 2: Indicates that the antenna is correctly connected.
• 3: Indicates that the GPS is tracking satellites.
Time Stamp Three LEDs indicate the Stratum connection level. The Stratum
indicates the accuracy the time stamp. The following list
explains the significance of the number of LEDs lit:
• 0: Indicates Stratum 4, within 100 us of absolute GMT.
• 3: Indicates Stratum 1, within 100 ns of absolute GMT.
Shutdown The chassis is in the process of being shut down.
Power Power is applied to the chassis.
Similar information is available for the AFD1 GPS receiver in the Time Source
tab of the Chassis Properties form (viewable through IxExplorer user interface).
Load Modules Although each Ixia load module differs in particular capabilities, all modules
share a common set of functions. Ixia load modules are generally categorized by
network technology. The network technologies supported, along with names
used to reference these technologies and more detailed information on load
module differences, are available in the subsequent chapters of this manual.
Note: A load module can also be referred to as a card. The terms load module
and card are used interchangeably in this manual.
The Load Module name prefix is used as the prefix to all load modules for that
technology; for example, LM 100 in LM 100 TX. The IxExplorer name is used to
label card and port types.

Ixia Hardware
Some load modules are further labelled by the type of connector supported. Thus,
a load module’s name can be formed from a combination of its basic technology
and the connector type. For example, LM 100 TX is the name of the 10/100 load
module with RJ-45 connectors. An example for Packet Over SONET (POS) is
the LMOC48c POS module, where no connector type is specified.
In addition, less expensive versions of several load modules are available. These
are called Type-3 or Type-M modules, signified by an ending of ‘-3’ or ‘-M’ in
the load module name and with a ‘-3’or ‘-M’ suffix in the IxExplorer.
Newer boards also may have an ‘L’ before the last number in their part number,
signifying the same limited functionality (example: LSM10GL1-01).
Some load modules can be configured with less than standard amount of
memory. Modules configured with such memory have a notation as to the
memory upgrade following the module name. For example, LM622MR-512.
Port Hardware The ports on the Ixia load modules provide high-speed, transmit, capture, and
statistics operation. The discussion which follows is broken down into a number
of areas:
• Types of Ports on page 2-9: The different types of networking technology
supported by Ixia load modules
• Port Transmit Capabilities on page 2-47: Facilities for generating data traffic
• Streams and Flows: A set of packets, which may be grouped into bursts
• Bursts and the Inter-Burst Gap (IBG): A number of packets
• Packets and the Inter-Packet Gap (IPG): Individual frames/packets of data
• Frame Data on page 2-51: The construction of data within a frame/packet
• Port Data Capture Capabilities on page 2-66: Facilities for capturing data
received on a port
• Port Statistics Capabilities on page 2-76: Facilities for obtaining statistics on
each port
Types of Ports
The types of load module ports that Ixia offers are divided into these broad
categories:
• Ethernet
• Power over Ethernet
• 10GE
• 40GE and 100GE
• SONET/POS
• ATM
• BERT

2 Ixia Hardware
Only the currently available Ixia load modules are discussed in this chapter.
Subsequent chapters in this manual discuss all supported load modules and their
optional features.
Ethernet
Ethernet modules are provided with various feature combinations, as mentioned

in the following list:
• Speed combinations: 10 Mbps, 100 Mbps, and 1000 Mbps
• Auto negotiation
• Pause control
• With and without on-board processors, also called Port CPUs (PCPUs).
Load modules without processors only allow for very limited routing
protocol emulation
• Power over Ethernet (Described in Power over Ethernet on page 2-10)
• External connections including the following:
• RJ-45
• MII
• RMII - a custom Ixia connector
• MT-RJ Fibre singlemode and multimode
• SC multimode
• GBIC singlemode and multimode
Power over Ethernet
The Power over Ethernet (PoE) load modules (PLM1000T4-PD and

LSM1000POE4-02) are special purpose, 4-channel electronic loads. They are
intended to be used in conjunction with Ixia ethernet traffic generator/analyzer
load modules to test devices that conform to IEEE std 802.3af.
A PoE load module provides the hardware interface required to test the Power
Sourcing Equipment (PSE) of a 802.3af compliant device by simulating a
Powered Device (PD).
Power Sourcing Equipment (PSE)
A PSE is any equipment that provides the power to a single link Ethernet
Network section. The PSE’s main functions are to search the link section for a
powered device (PD), optionally classify the PD, supply power to the link section
(only if a PD is detected), monitor the power on the link section, and remove
power when it is no longer requested or required.
There are two power sourcing methods for PoE—Alternative A and Alternative
B.

Ixia Hardware
PSEs may be placed in two locations with respect to the link segment, either
coincident with the DTE/Repeater, or midspan. A PSE that is coincident with the
DTE/Repeater is an ‘Endpoint PSE.’ A PSE that is located within a link segment
that is distinctly separate from and between the Media Dependent Interfaces
(MDIs) is a ‘Midspan PSE.’
Endpoint PSEs may support either Alternative A, B, or both. Endpoint PSEs can
be compatible with 10BASE-T, 100BASE-X, and/or 1000BASE-T.
Midspan PSEs must use Alternative B. Midspan PSEs are limited to operation
with 10BASE-T and 100BASE-TX systems. Operation of Midspan PSEs on
1000BASE-T systems is beyond the scope of PoE.
Powered Devices (PD)
A powered device either draws power or requests power by participating in the

PD detection algorithm. A device that is capable of becoming a PD may or may
not have the ability to draw power from an alternate power source and, if doing
so, may or may not require power from the PSE.
One PoE Load Module emulates up to four PDs. The PoE Load Module (PLM)
has eight RJ-45 interfaces—four of them used as PD-emulated ports, with each
having its own corresponding interface that connects to a port on any Ixia 10/
100/1000 copper-based Ethernet load module (includes LM100TX, all copper-
based TXS, and Optixia load modules).
The following figure demonstrates how the PoE modules use an Ethernet card to
transmit and receive data streams.
Figure 2-5. Data Traffic over PoE Set Up

2 Ixia Hardware
The emulated PD device can ‘piggy-back’ a signal from a different load module
along the cable connected to the PSE from which it draws power. In this manner,
the emulated PD can mimic a device that generates traffic, such as an IP phone.
Discovery Process
The main purpose for discovery is to prevent damage to existing Ethernet

equipment. The Power Sourcing Equipment (PSE) examines the Ethernet cables
by applying a small current-limited voltage to the cable and checking for the
presence of a 25K ohm resistor in the remote Powered Device (PD). Only if the
resistor is present, the full 48V is applied (and this is still current-limited to
prevent damage to cables and equipment in fault conditions). The Powered
Device must continue to draw a minimum current or the PSE removes the power
and the discovery process begins again.
Figure 2-6. Discovery Process Voltage
There is also an optional extension to the discovery process where a PD may

indicate to the PSE its maximum power requirements, called classification. Once
there is power applied to the PD, normal transactions/data transfer occurs. During
this period, the PD sends back a maintain power signature (MPS) to signal the
PSE to continue to provide power.

Ixia Hardware
PoE Acquisition Tests
During the course of testing with the PoE module, it may be necessary to
measure the amplitude of the incoming current. The PoE module has the ability
to measure amplitude versus time in following two ways:
• Time test: The amount of time that elapses between a Start and Stop incoming
current measurement.
• Amplitude test: The amplitude of the current after a set amount of time from a
Start incoming current setting.
In both scenarios, a Start trigger is set, indicating when the test should commence
based on an incoming current value (in either DC Volts or DC Amps).
In a Time test, a Stop trigger is also set (in either DC Volts or DC Amps)
indicating when the test is over. Once the Stop trigger is reached, the amount of
time between the Start and Stop trigger is measured (in microseconds) and the
result is reported.
In an amplitude test, an Amplitude Delay time is set (in microseconds), which is

the amount of time to wait after the Start trigger is reached before ending the test.
The amplitude at the end of the Amplitude Delay time is measured and is
reported.
Both Start and Stop triggers must also have a defined Slope type, either positive
or negative. A positive slope is equivalent to rising current, while a negative
slope is equivalent to decreasing current. A current condition must agree with
both the amplitude setting and the Slope type to satisfy the trigger condition.
An example of a Time test is shown in the following figure, and an example of an

Amplitude test is shown in Figure 2-8.

2 Ixia Hardware
Figure 2-7. PoE Time Acquisition Example
Figure 2-8. PoE Amplitude Acquisition Example

Ixia Hardware
10GE
The 10 Gigabit Ethernet (10GE) family of load modules implements five of the
seven IEEE 8.2.3ae compliant interfaces that run at 10 Gbit/second. Several of
the load modules may also be software switched to OC192 operation.
The 10 GE load modules are provided with various feature combinations, as

mentioned in the following list:
• Interfaces types: LAN, WAN, XAUI, and XENPAK
• Interface connectors: SC singlemode (LAN and WAN), SC multimode
(LAN), LC singlemode/multimode, XFP, XAUI, and XENPAK
• Reach: Short, long, and extended
• Wavelengths: 850 nm, 1310 nm, 1550 nm
The relationship of the logical structures for the different 10 Gigabit types is
shown in the diagram (adapted from the 802.3ae standard) in the following
figure.
Figure 2-9. IEEE 802.3ae Draft—10 Gigabit Architecture
For 10GE XAUI and 10GE XENPAK modules, a Status message contains a 4-
byte ordered set with a Sequence control character plus three data characters (in
hex), distributed across the four lanes, as shown in the following figure. Four
Sequence ordered sets are defined in IEEE 802.3ae, but only two of these—Local

2 Ixia Hardware
Fault and Remote Fault—are currently in use; the other two are reserved for
future use.
Figure 2-10. 10GE XAUI/XENPAK Sequence Ordered Sets
XAUI Interfaces
The 10 Gigabit XAUI interface has been defined in the IEEE draft specification
P802.3ae by the 10 Gigabit Ethernet Task Force (10GEA). XAUI stands for ‘X’
(the Roman Numeral for 10, as in ‘10 Gigabit’), plus ‘AUI’ or Attachment Unit
Interface originally defined for Ethernet.
The original Ethernet standard was defined in IEEE 802.3, and included MAC
layer, frame size, and other ‘standard’ Ethernet characteristics. IEEE 802.3z
defined the Gigabit standard. IEEE 802.3ae has been created to create a
simplified version of SONET framing to carry native Ethernet-framed traffic
over high-speed fiber networks. This new standard allows a smooth transition
from 10 Gbps native Ethernet traffic to work with 9.6 Gbps for SONET at OC-
192c rate over WAN and MAN links. The 10GE XAUI has a XAUI interface for
connecting to another XAUI interface, such as on a DUT. A comparison of the
IEEE P802.3ae model for XAUI and the OSI model is shown in the following
figure.

Ixia Hardware
Figure 2-11. IEEE P802.3ae Architecture for 10GE XAUI
Lane Skew
The Lane Skew feature provides the ability to independently delay one or more
of the four XAUI lanes. The resolution of the skew is 3.2 nanoseconds (ns),
which consists of 10 Unit Intervals (UIs), each of which is 320 picoseconds (ps).
Each UI is equivalent to the amount of time required to transmit one XAUI bit at
3.125 Gbps.
Lane Skew allows a XAUI lane to be skewed by as much as 310 UI (99.2ns) with
respect to the other three lanes. To effectively use this feature, the four lanes
should be set to different skew values. Setting all four lanes to zero is equivalent
to setting all four lanes to +80 UI. In both cases, the lanes are synchronous and
there is no lane skew. When lane skewing is enabled, /A/, /K/, and /R/ codes are
inserted into the data stream BEFORE the lanes are skewed. The principle behind
lane skewing is shown in the diagrams in Figure 2-12 and Figure 2-13.

2 Ixia Hardware
Figure 2-12. XAUI Lane Skewing—Lane Skew Disabled
Figure 2-13. XAUI Lane Skewing—Lane Skew Enabled
Link Fault Signaling
Link Fault Signaling is defined in Section 46 of the IEEE 802.3ae specification

for 10 Gigabit Ethernet. When the feature is enabled, four statistics are added to
the list in Statistic View for the port. One is for monitoring the Link Fault State;
two for providing a count of the Local Faults and Remote Faults; and the last one
is for indicating the state of error insertion, whether or not it is ongoing.
Link Fault Signaling originates with the PHY sending an indication of a local
fault condition in the link being used as a path for MAC data. In the typical
scenario, the Reconciliation Sublayer (RS) which had been receiving the data
receives this Local Fault status, and then send a Remote Fault status to the RS
which was sending the data. Upon receipt of this Remote Fault status message,
the sending RS terminates transmission of MAC Data, sending only ‘Idle’
control characters until the link fault is resolved.
For the 10GE LAN and LAN-M serial modules, the Physical Coding Sublayer
(PCS) of the PHY handles the transition from 64 bits to 66 bit ‘Blocks.’ The 64
bits of data are scrambled, and then a 2-bit synchronization (sync) header is
attached before transmission. This process is reversed by the PHY at the
receiving end.
Link Fault Signaling for the 10GE XAUI/XENPAK is handled differently across
the four-lane XAUI optional XGMII extender layer, which uses 8B/10B
encoding.

Ixia Hardware
Figure 2-14. Examples of Link Fault Signaling Error Insertion
The examples in this figure are described in the following table:.

Table 2-5. Cases for Example
Case Conditions
Case 1 Contiguous Bad Blocks = 2 (the minimum).

Contiguous Good Blocks = 2 (the minimum).
Send Type A ordered sets.
Loop 1x.

Send Type A ordered sets.
Loop continuously.

Send alternate ordered set types.
Loop 1x.

Send alternate ordered set types.
Loop continuously.
Link Alarm Status Interrupt (LASI)
The link alarm status is an active low output from the XENPAK module that is
used to indicate a possible link problem as seen by the transceiver. Control
registers are provided so that LASI may be programmed to assert only for
specific fault conditions.

2 Ixia Hardware
Efficient use of XENPAK and its specific registers requires an end-user system
to recognize a connected transceiver as being of the XENPAK type. An
Organizationally Unique Identifier (OUI) is used as the means of identifying a
port as XENPAK, and also to communicate the device in which the XENPAK
specific registers are located.
Ixia’s XENPAK module allows for setting whether or not LASI monitoring is
enabled, what register configurations to use, and the OUI. The XENPAK module
can use the following registers:
• Rx Alarm Control (Register 0x9003): It can be programmed to assert only
when specific receive path fault condition(s) are present.
• Tx Alarm Control (Register 0x9001): It can be programmed to assert only
when specific transmit path fault condition(s) are present.
• LASI Control (Register 0x9002): A LASI control register that allows
global masking of the Rx Alarm and Tx Alarm.
You can control the registers by setting a series of sixteen bits for each register.
The register bits and their usage are described in the following tables.
Table 2-6. Rx Alarm Control
Bits Description Default
15 - 11 Reserved 0
10 Vendor Specific N/A (vendor Setting)
9 WIS Local Fault 1 (when implemented)

Enable
8-6 Vendor Specific N/A (vendor Setting)
5 Receive Optical 1 (when implemented)

Power Fault Enable
4 PMA/PMD Receiver 1 (when implemented)

Local Fault Enable
3 PCS Receive Local 1

Fault Enable
2-1 Vendor Specific N/A (vendor Setting)
0 PHY XS Receive 1
Local Fault Enable
Table 2-7. Tx Alarm Control
15 - 11 Reserved 0
10 Vendor Specific N/A (vendor setting)
9 Laser Bias Current 1 (when implemented)

Fault Enable

Ixia Hardware
Table 2-7. Tx Alarm Control
8 Laser Temperature 1 (when implemented)

Fault Enable
7 Laser Output Power 1 (when implemented)

Fault Enable
6 Transmitter Fault 1
Enable
5 Vendor Specific N/A (vendor setting)
4 PMA/PMD 1 (when implemented)

Transmitter Local
Fault Enable
3 PCS Transmit Local 1

Fault Enable
2-1 Vendor Specific N/A (vendor setting)
0 PHY XS Transmit 1
Local Fault Enable
Table 2-8. LASI Control

15 - 8 Reserved 0
7-3 Vendor Specific 0 (when implemented)
2 Rx Alarm Enable 0
1 Tx Alarm Enable 0
0 LS Alarm Enable 0
For more detailed information on LASI, see the online document XENPAK MSA
Rev. 3.
40GE and 100GE
For theoretical information, refer to 40 Gigabit Ethernet and 100 Gigabit

Ethernet Technology Overview White Paper, published by Ethernet Allliance,
November, 2008. This white paper may be obtained through the Internet.
http://www.ethernetalliance.org/images/40G_100G_Tech_overview.pdf
SONET/POS
SONET/POS modules are provided with various feature combinations:

• Different speeds: OC3, OC12, OC48, OC192, Fibre Channel, 2x Fibre
Channel, and Gigabit Ethernet.

2 Ixia Hardware
• Interfaces: SC singlemode and multimode (OC3, OC12, OC192), SC

singlemode (OC48), no optical transceiver, SFP LC singlemode
(Unframed BERT) and custom interface.
• Reach: long, intermediate and long.
• Wavelengths: 850nm, 1310nm and 1550nm.
• Local processor support. All SONET/POS load modules include a local
processor, but the power of the processor and amount of memory varies.
• Variable clocking—OC48 only, see Variable Rate Clocking on page 2-22.
• Concatenated or channelized SONET operation, see SONET Operation on
page 2-22.
• Error insertion, see Error Insertion on page 2-24.
• BERT: Bit Error Rate Testing both framed and unframed, see BERT on
page 2-45.
• DCC: Data Communication Channel, see DCC—Data Communications
Channel on page 2-25.
• RPR: Resilient Packet Ring, see RPR—Resilient Packet Ring on page 2-
26.
• GFP: Generic Framing Procedure, see GFP—Generic Framing Procedure
on page 2-29.
• PPP: Point to Point protocol, see PPP Protocol Negotiation on page 2-33.
• HDLC: High-Level Data Link Control, see HDLC on page 2-39.
• Frame Relay: see Frame Relay on page 2-39.
• DSCP: see DSCP—Differentiated Services Code Point on page 2-39.
Variable Rate Clocking
The OC48 VAR allows a variation of +/- 100 parts per million (ppm) from the
clock source’s nominal frequency, through a DC voltage input into the BNC jack
marked ‘DC IN’ on the front panel. The frequency may be monitored through the
BNC marked ‘Freq Monitor.’
SONET Operation
A Synchronous Optical NETwork/Synchronous Digital Hierarchy (SONET/

SDH) frame is based on the Synchronous Transport Signal-1 (STS-1) frame,
whose structure is shown in Figure 2-15 on page 2-23. Transmission of SONET
Frames of this size correspond to the Optical Carrier level 1 (OC-1).
An OC-3c, consists of three OC-1/STS-1 frames multiplexed together at the octet

level. OC-12c, OC-48c, and OC-192c, are formed from higher multiples of the
basic OC-1 format. The suffix ‘c’ indicates that the basic frames are concatenated
to form the larger frame.
Ixia supports both concatenated (with the ‘c’) and channelized (without the ‘c’)
interfaces. Concatenated interfaces send and receive data in a single streams of

Ixia Hardware
data. Channelized interfaces send and receive data in multiple independent

streams.
Figure 2-15. Generated Frame Contents—SONET STS-1 Frame
The contents of the SONET STS-1 frame are described in Table 2-9 on page 2-
23.
Table 2-9. SONET STS-1 Frame Contents
Section Description
Section Overhead Consists of 9 bytes which include information relating to

(SOH) performance monitoring of the STS-n signal, and
framing.
Line Overhead (LOH) Consists of 18 bytes which include information relating

to performance monitoring of the individual STS-1s,
protection switching information, and line alarm
indication signals.

2 Ixia Hardware
Table 2-9. SONET STS-1 Frame Contents
Section Description
Transport Overhead Consists of a combination of the Section Overhead and

(TOH) Line Overhead sections of the STS-1 frame.
Path Overhead Part of the Synchronous Payload Envelope (SPE),

(POH) contains information on the contents of the SPE, and
handles quality monitoring.
Synchronous Payload Contains the payload information, the packets which

Envelope (SPE) are being transmitted, and includes the Path Overhead
bytes.
Payload Capacity Part of the SPE, and contains the packets being
transmitted.
The SONET STS-1 frame is transmitted at a rate of 51.84 Mbps, with 49.5 Mbps
reserved for the frame payload. A SONET frame is transmitted in 125
microseconds, with the order of transmission of the starting with Row 1, Byte 1
at the upper left of the frame, and proceeding by row from top to bottom, and
from left to right.
The section, line, and path overhead elements are related to the manner in which
SONET frames are transmitted, as shown in Figure 2-16 on page 2-24.
Figure 2-16. Example Diagram of SONET Levels and Network Elements
Error Insertion
A variety of deliberate errors may be inserted in SONET frames in the section,

line or path areas of a frame. The errors which may be inserted vary by particular
load module. Errors may be inserted continuously or periodically as shown in
Figure 2-17 on page 2-25.

Ixia Hardware
Figure 2-17. SONET Error Insertion
An error may be inserted in one of two manners:

• Continuous: Each SONET frame receives the error.
• Periodic: A number of errors are inserted in consecutive frames and the
pattern is repeated based on a number of frames or a period of time.
Predefined periods are available, or you may create your own predefined
periods.
Each error may be individually inserted continuously or periodically. Errors may

be inserted on a one time basis over a number of frames as well.
DCC—Data Communications Channel
The data communication channel is a feature of SONET networks which uses the
DCC bytes in the transport overhead of each frame. This is used for control,
monitoring and provisioning of SONET connections. Ixia ports treat the DCC as
a data stream which ‘piggy-backs’ on the normal SONET stream. The DCC and
normal (referred to as the SPE - Synchronous Payload Envelope) streams can be
transmitted independently or at the same time.
A number of different techniques are available for transmitting DCC and SPE
data, utilizing Ixia streams and flows (see Streams and Flows on page 2-47) and
advanced stream scheduler (see Advanced Streams on page 2-48).
SRP—Spatial Reuse Protocol
The Spatial Reuse Protocol (SRP) was developed by Cisco for use with ring-
based media. It derives its name from the spatial reuse properties of the packet
handling procedure. This optical transport technology combines the bandwidth-
efficient and service-rich capabilities of IP routing with the bandwidth-rich, self-
healing capabilities of fiber rings to deliver fundamental cost and functionality
advantages over existing solutions. In SRP mode, the usual POS header (PPP,
and so forth) is replaced by the SRP header.
SRP networks use two counter-rotating rings. One Ixia port may be used to
participate in one of the rings; two may be used to simultaneously participate in
both rings. Ixia supports SRP on both OC48 and OC192 interfaces.

2 Ixia Hardware
In SRP-mode, SRP packets can be captured and analyzed. The IxExplorer

capture view displays packet analysis which understands SRP packets. The Ixia
hardware also collects specific SRP related statistics and performs filtering based
on SRP header contents.
Any of the following SRP packet types may be generated in a data stream, along
with normal IPv4 traffic:
• SRP Discovery
• SRP ARP
• SRP IPS (Intelligent Protection Switching)
RPR—Resilient Packet Ring
Ixia’s optional Resilient Packet Ring (RPR) implementation is available on the

OC-48c and OC-192c POS load modules. RPR is a proposed industry standard
for MAC Control on Metropolitan Area Networks (MANs), defined by IEEE
P802.17. This feature provides a cost-effective method to optimize the transport
of bursty traffic, such as IP, over existing ring topologies.
A diagram showing a simplified model of an RPR network is shown in Figure 2-

18 on page 2-26. It is made up of two, counter-rotating ‘ringlets,’ with nodes
called ‘stations’ supporting MAC Clients that exchange data and control
information with remote peers on the ring. Up to 255 nodes can be supported on
the ring structure.
Figure 2-18. RPR Ring Network Diagram
The RPR topology discovery is handled by a MAC sublayer, and a protection

function maintains network connectivity in the event of a station or span failure.
The structure of the RPR layers, compared to the OSI model, is illustrated in a
diagram based on IEEE 802.17, shown in Figure 2-19 on page 2-27.

Ixia Hardware
Figure 2-19. RPR Layers
A diagram of the layers associated with an RPR Station is shown in Figure 2-20
on page 2-27.
Figure 2-20. RPR Layer Diagram
The Ixia implementation allows for the configuration and transmission of the
following types of RPR frames:
• RPR Fairness Frames: The RPR Fairness Algorithm (FA) is used to manage
congestion on the ringlets in an RPR network. Fairness frames are sent
periodically to advertise bandwidth usage parameters to other nodes in the
network to maintain weighted fair share distributions of bandwidth. The

2 Ixia Hardware
messages are sent in the direction opposite to the data flow, and therefore, on
the other ringlet. A diagram of the RPR Fairness Frame, per IEEE 802.17/
D2.1, is shown in Figure 2-21 on page 2-28.
Figure 2-21. RPR Fairness Frame Format
A diagram of the baseRingControl byte, part of the Ring Control header for
all types of RPR frames, is shown in Figure 2-22 on page 2-28.
Figure 2-22. RPR baseRingControl Byte
• RPR Topology Discovery. Two types of messages are used:

• RPR Topology Discovery Message: for the discovery of the physical
topology.
• RPR Topology Extended Status Message: for the transmission of
additional information from a node concerning bandwidth and other
configuration options. This format uses TLV (Type-Length-Value)
options, including:
• Weight
• Total reserved bandwidth
• Neighbor address

Ixia Hardware
• Individual reserved bandwidth

• Station name
• Vendor specific data
• RPR Protection Switching Message: used to support automatic, rapid
switching of traffic in the presence of a ring failure.
• RPR Operations, Administration and Management (OAM). Three messages
are supported:
• Echo Request and Response messages
• Flush Frames
• Vendor specific message
GFP—Generic Framing Procedure
GFP provides a generic mechanism to adapt traffic from higher-layer client

signals over a transport network. Currently, two modes of client signal adaptation
are defined for GFP.
• A PDU-oriented adaptation mode, referred to as Frame-Mapped GFP (GFP-
F, for traffic such as IP/PPP or Ethernet MAC).
• A block-code oriented adaptation mode, referred to as Transparent GFP
(GFP-T, for traffic such as Fibre Channel or ESCON/SBCON).
In the Frame-Mapped adaptation mode, the Client/GFP adaptation function

operates at the data link (or higher) layer of the client signal. Client PDU
visibility is required, which is obtained when the client PDUs are received from
either the data layer network or a bridge, switch, or router function in a transport
network element.
For the Transparent adaptation mode, the Client/GFP adaptation function

operates on the coded character stream, rather than on the incoming client PDUs.
Processing of the incoming code word space for the client signal is required.
Two kinds of GFP frames are defined: GFP client frames and GFP control
frames. GFP also supports a flexible (payload) header extension mechanism to
facilitate the adaptation of GFP for use with diverse transport mechanisms.
GFP uses a modified version of the Header Error Check (HEC) algorithm to
provide GFP frame delineation. The frame delineation algorithm used in GFP
differs from HEC in two basic ways:
• The algorithm uses the PDU Length Indicator field of the GFP Core Header
to find the end of the GFP frame.
• HEC field calculation uses a 16-bit polynomial and, consequently, generates
a two-octet cHEC field.
A diagram of the format for a GFP frame is shown in Figure 2-23 on page 2-30.

2 Ixia Hardware
Figure 2-23. GFP Frame Elements
PTI PFI EXI

Payload Length
UPI
Core HEC
Payload Type
Core Header Type HEC
0 - 60 Bytes of
Extension Headers
CID
Payload Area
Payload Header Spare
Extension HEC
Extension HEC
Payload Information
N x [536, 520]
or
Variable Length Legend
Packets
HEC - Header Error Control
FCS - Frame Check Sequence
PTI - Payload Type Identifier
PFI - Payload FCS Identifier
Payload FCS EXI - Extension Header Identifier
UPI - User Payload Identifier
CID - Channel ID
The sections of the GFP frame are described in the following list:
• Payload Length Indicator (PLI): The two-octet PLI field contains a binary
number representing the number of octets in the GFP Payload Area. The
absolute minimum value of the PLI field in a GFP client frame is 4 octets.
PLI values 0-3 are reserved for GFP control frame usage.
• Core Header Error Control (cHEC): The two-octet Core Header Error Control
field contains a CRC-16 error control code that protects the integrity of the
contents of the Core Header by enabling both single-bit error correction and
multi-bit error detection.
• Type Header Error Control (tHEC): The two-octet Type Header Error
Control field contains a CRC-16 error control code that protects the integrity
of the contents of the Type field by enabling both single-bit error correction
and multi-bit error detection.
• Extension Header Error Control (eHEC): The two-octet Extension Header
Error Control field contains a CRC-16 error control code that protects the
integrity of the contents of the extension headers by enabling both single-bit
error correction (optional) and multi-bit error detection.
• Connection Identification (CID): The CID is an 8-bit binary number used to
indicate one of 256 communications channels at a GFP termination point.
• Payload: The GFP Payload Area, which consists of all octets in the GFP
frame after the GFP Core Header, is used to convey higher layer specific
protocol information. This variable length area may include from 4 to 65,535
octets. The GFP Payload Area consists of two common components:
• A Payload Header and a Payload Information field
• An optional Payload FCS (pFCS) field

Ixia Hardware
Practical GFP MTU sizes for the GFP Payload Area are application specific.
• Frame Check Sequence (FCS): The GFP Payload FCS is an optional, four-
octet long, frame check sequence. It contains a CRC-32 sequence that
protects the contents of the GFP Payload Information field. A value of 1 in
the PFI bit within the Type field identifies the presence of the payload FCS
field.
GFP frame delineation is performed based on the correlation between the first
two octets of the GFP frame and the embedded two-octet cHEC field. Figure 2-
24 on page 2-31 shows the state diagram for the GFP frame delineation method.
Figure 2-24. GFP State Transitions

Frame by Frame
(error correction disabled)
Virtual Framers
PRESYNC (up to M) PRESYNC
(cHEC1d) ... (cHECmd)
. .
. Incorrect cHEC . DELTA
consecutive
. . correct
cHEC
PRESYNC PRESYNC
(cHEC11) (cHECm1)
Correct cHEC Correct cHEC
HUNT SYNC
Octet by Octet Frame by Frame

(error correction disabled) (error correction enabled)
The state diagram works as follows:

1. In the HUNT state, the GFP process performs frame delineation by searching
octets for a correctly formatted Core Header over the last received sequence
of four octets. Once a correct cHEC match is detected in the candidate
Payload Length Indicator (PLI) and cHEC fields, a candidate GFP frame is
identified and the receive process enters the PRESYNC state.
2. In the PRESYNC state, the GFP process performs frame delineation by
checking frames for a correct cHEC match in the presumed Core Header of
the next candidate GFP frame. The PLI field in the Core Header of the
preceding GFP frame is used to find the beginning of the next candidate GFP
frame. The process repeats until a set number of consecutive correct cHECs
are confirmed, at which point the process enters the SYNC state. If an
incorrect cHEC is detected, the process returns to the HUNT state.

2 Ixia Hardware
3. In the SYNC state, the GFP process performs frame delineation by checking
for a correct cHEC match on the next candidate GFP frame. The PLI field in
the Core Header of the preceding GFP frame is used to find the beginning of
the next candidate GFP frame. Frame delineation is lost whenever multiple
bit errors are detected in the Core Header by the cHEC. In this case, a GFP
Loss of Frame Delineation event is declared, the framing process returns to
the HUNT state, and a client Server Signal Failure (SSF) is indicated to the
client adaptation process.
4. Idle GFP frames participate in the delineation process and are then discarded.
Robustness against false delineation in the resynchronization process depends on

the value of DELTA. A value of DELTA = 1 is suggested. Frame delineation
acquisition speed can be improved by the implementation of multiple ‘virtual
framers,’ whereby the GFP process remains in the HUNT state and a separate
PRESYNC substate is spawned for each candidate GFP frame detected in the
incoming octet stream.
Scrambling of the GFP Payload Area is required to provide security against

payload information replicating scrambling word (or its inverse) from a frame
synchronous scrambler (such as those used in the SDH RS layer or in an OTN
OPUk channel). Figure 2-25 on page 2-32 illustrates the scrambler and
descrambler processes.
Figure 2-25. GFP Scrambling
X43 + 1 Scrambler X43 + 1 De-scrambler
X(t) Y(t) Y(t) X(t)
Y(t - 43) Y(t - 43)

D43
D43
D2
D1
D1
D2
All octets in the GFP Payload Area are scrambled using a x43 + 1 self-
synchronous scrambler. Scrambling is done in network bit order.
At the source adaptation process, scrambling is enabled starting at the first

transmitted octet after the cHEC field, and is disabled after the last transmitted
octet of the GFP frame. When the scrambler or descrambler is disabled, its state
is retained. Hence, the scrambler or descrambler state at the beginning of a GFP
frame Payload Area is, thus, the last 43 Payload Area bits of the GFP frame
transmitted in that channel immediately before the current GFP frame.
The activation of the sink adaptation process descrambler also depends on the
present state of the cHEC check algorithm:
• In the HUNT and PRESYNC states, the descrambler is disabled.
• In the SYNC state, the descrambler is enabled only for the octets between
the cHEC field and the end of the candidate GFP frame.

Ixia Hardware
CDL— Converged Data Link
10GE LAN, 10GE XAUI, 10GE XENPAK, 10GE WAN, and 10GE WAN
UNIPHY modules all support the Cisco CDL preamble format.
The Converged Data Link (CDL) specification was developed to provide a

standard method of implementing operation, administration, maintenance, and
provisioning (OAM&P) in Ethernet packet-based optical networks without using
a SONET/SDH layer.
PPP Protocol Negotiation
The Point-to-Point Protocol (PPP) is widely used to establish, configure and

monitor peer-to-peer communication links. A PPP session is established in a
number of steps, with each step completing before the next one starts. The steps,
or layers, are:
1. Physical: a physical layer link is established.
2. Link Control Protocol (LCP): establishes the basic communications
parameters for the line, including the Maximum Receive Unit (MRU), type of
authentication to be used and type of compression to be used.
3. Link quality determination and authentication. These are optional processes.
Quality determination is the responsibility of PPP Link Quality Monitoring
(LQM) Protocol. Once initiated, this process may continue throughout the life
of the link. Authentication is performed at this stage only. There are multiple
protocols which may be employed in this process; the most common of these
are PAP and CHAP.
4. Network Control Protocol (NCP): establishes which network protocols (such
as IP, OSI, MPLS) are to be carried over the link and the parameters
associated with the protocols. The protocols which support this NCP
negotiation are called IPCP, OSINLCP, and MPLSCP, respectively.
5. Network traffic and sustaining PPP control. The link has been established and
traffic corresponding to previously negotiated network protocols may now
flow. Also, PPP control traffic may continue to flow, as may be required by
LQM, PPP keepalive operations, and so forth.
All implementations of PPP must support the Link Control Protocol (LCP),
which negotiates the fundamental characteristics of the data link and constitutes
the first exchange of information over an opening link. Physical link
characteristics (media type, transfer rate, and so forth) are not controlled by PPP.
The Ixia PPP implementation supports LCP, IPCP, MPLSCP, and OSINLCP.
When PPP is enabled on a given port, LCP and at least one of the NCPs must
complete successfully over that port before it is administratively ‘up’ and
therefore be ready for general traffic to flow.
Each Ixia POS port implements a subset of the LCP, LQM, and NCP protocols.
Each of the protocols is of the same basic format. For any connection, separate
negotiations are performed for each direction. Each party sends a Configure-

2 Ixia Hardware
Request message to the other, with options and parameters proposing some form
of configuration. The receiving party may respond with one of three messages:
• Configure-Reject: The receiving party does not recognize or prohibits one or
more of the suggested options. It returns the problematic options to the
sender.
• Configure-NAK: The receiving party understands all of the options, but finds
one or more of the associated parameters unacceptable. It returns the
problematic options, with alternative parameters, to the sender.
• Configure-ACK: The receiving party finds the options and parameters
acceptable.
For the Configure-Reject and Configure-NAK requests, the sending party is

expected to reply with an alternative Configure-Request.
The Ixia port may be configured to immediately start negotiating after the
physical link comes up, or passively wait for the peer to start the negotiation. Ixia
ports both sends and responds to PPP keepalive messages called echo requests.
LCP—Link Control Protocol Options
The following sections outline the parameters associated with the Link Control
Protocol. LCP includes a number of possible command types, which are assigned
option numbers in the pertinent RFCs. Note that PPP parameters are typically
independently negotiated for each direction on the link.
Numerous RFCs are associated with LCP, but the most important RFCs are RFC
1661 and RFC 1662. The HDLC/PPP header sequence for LCP is FF 03 C0 21.
During the LCP phase of negotiation, the Ixia port makes available the following
options:
• Maximum Receive Unit: This LCP parameter (actually the set of
Maximum Receive Unit (MRU) and Maximum Transmit Unit (MTU))
determines the maximum allowed size of any frame sent across the link
subsequent to LCP completion. To be fully standards-compliant, an
implementation must not send a frame of length greater than its MTU + 4
bytes + CRC length. For instance, if the negotiated MTU for a port is 2000
and 32 bit CRC is in use, no frame larger than 2008 bytes should ever be
sent out that port. Packets that are larger are expected to be fragmented
before transmitting or to be dropped. The Ixia port's MTU is the peer's
MRU following LCP negotiation. Strictly speaking, the receiving side can
assume that frames received is not greater than the MRU. In practice,
however, an implementation should be capable of accepting larger frames.
If a peer rejects this option altogether, the negotiated setting defaults to
1,500. Regardless of the negotiated MRU, all implementations must be
capable of accepting frames with an information field of at least 1,500
bytes.
For the transmit direction portion of the negotiation, the peer sends the
Ixia port its configuration request. The Ixia port accepts and acknowledges
the peer's requested MRU as long as it is less than or equal to the specified

Ixia Hardware
user's desired transmit value (but greater than 26). For the receive
direction portion of the negotiation, the Ixia port sends a configuration
request based on the user’s desired value. Generally, the Ixia port accepts
what the peer desires (if it acknowledges the request, then the user value is
used, or if the peer sends a Configure-Nak with another value the Ixia port
uses that value as long as it is valid). This approach is used to maximize
the probability of successful negotiation.
• Asynchronous Control Character Map: ACCM is only really pertinent to
asynchronous links. On asynchronous lines, certain characters sent over
the wire can have special meaning to one or more receiving entities. For
instance, common implementations of the widely used XON/XOFF flow
control protocol assign the ASCII DC3 character (0x13) to XOFF. On such
a link, an embedded data byte that happens to have the value 0x13 would
be misinterpreted by a receiver as an XOFF command, and cause
suspension of reception. To avoid this problem, the 0x13 character
embedded in the data could be sent through an ‘escape sequence’ which
consists of preceding the data character with a dedicated tag character and
modifying the data character itself.
The Asynchronous Control Character Map (ACCM) LCP parameter
allows independent designation of each character in the range 0x00 thru
0x1F as a control character. A control character is sent/received with a
preceding ‘control-escape’ character (0x7D). When the 0x7D is seen in
the received data stream, the 0x7D is dropped and the next character is
exclusive-or’d with 0x20 to get the original transmitted character. ACCM
negotiation consists of exchanging masks between peers to reach an
agreement as to which characters are treated as special control characters
on transmission and reception. For example, sending a mask of
0xFFFFFFFF means all characters in the range 0x00 thru 0x1F are sent
with escape sequences; a mask of 0 means no special handling, so all
characters are arbitrary data.
Packet over SONET is an octet-synchronous medium. If the link is direct
between POS peers, neither side should be generating control-escapes.
(Exceptions to this are bytes 0x7D and 0x7E: the former is the special
control escape character itself; the latter is the start/end frame marker.
Escaping of these two characters is generally handled directly by physical
layer hardware). On links in which there is some kind of intermediate
asynchronous media, it is required that whatever device performs the
asynchronous to synchronous conversion must also take care of any
special character handling, isolating this from any POS port. See RFC
1662, sections 4.1 and 6.
If ACCM negotiation is enabled, the Ixia port advertises an ACCM mask
of 0 to its peer in its LCP configuration request. The Ixia port accept
whatever the peer puts forth, but does not act on the results. Regardless of
the final negotiated settings for receive and transmit ACCM, the Ixia port
does not send escape control sequences nor does it expect to receive them.
This is the nature of a synchronous PPP medium, such as POS.

2 Ixia Hardware
• Magic Number: A magic number is a 32-bit value, ideally numerically

random, which is placed in certain PPP control packets. Magic numbers
aid in detection of looped links. If a received PPP packet that includes a
magic number matches a previously transmitted packet, including magic
number, the link is probably looped.
IxExplorer and the Tcl APIs allow global enable/disable of magic number
negotiation. If the ‘Use Magic Number’ feature is enabled, the Ixia port
does not request magic number of its peer and rejects the option if the peer
requests it. If the check box is selected, the port attempts to negotiate
magic number. The result of the bi-directional negotiation process is
displayed in the fields for transmit and receive: an indication of whether
magic number is enabled is written in the field for the corresponding
direction.
NCP—Network Control Protocols

• IPCP: Internet Protocol Control Protocol Options for IPV4. IPCP includes
three command types, which are assigned option numbers in the pertinent
RFCs. Note that PPP parameters are typically independently negotiated for
each direction on the link.
The sender of this Configure-Request may either include its own IP
address, to provide this information to its remote peer, or may send all
0.0.0.0 as an IP address, which requests that the remote peer assign an IP
address for the local node. The receiver may refuse the requested IP
address and attempt to specify one for the peer to use by using a
Configure-NAK response to the request with a specification of a different
address.
The Ixia implementation provides minimal configuration of this
parameter. You must specify the local IP address of the unit and the peer
must provide its own IP address. The Ixia port accepts any IP address the
peer wishes to use as long as it is a valid address (for example, not all 0's).
The Ixia port expects the peer to accept its address. If, however, the peer
specifies a different address for use, the port acknowledges that address
but not actually notify you that this has happened. The Ixia port accepts a
situation in which local and peer addresses are the same following
negotiation.
• IPv6CP: Internet Protocol Control Protocol Options for IPv6. IPv6CP
includes three command types, which are assigned option numbers in the
pertinent RFCs. Note that PPP parameters are typically independently
negotiated for each direction on the link.
A PPP peer may determine its IPv6 interface address by one or three
methods:
• Generate its own address.
• Suggest its own address to its peer, but allow the peer to override
that value.
• Require that the peer designate an address.

Ixia Hardware
In any of these cases, the Configure-Request must contain a tentative

interface-identifier to send to the peer that is both unique to the link and if
possible consistently reproducible.
The Ixia PPP implementation of IPv6CP is such that the negotiation mode
of the local endpoint may be configured in one of three modes:
• Local may: the local peer may suggest an Interface Identifier (IID),
but most allow a Configure-NAK with an alternate address to
override its setting.
• Local must: the local peer must set the IID, which the peer must
accept.
• Peer must: the peer must supply the IID. This is accomplished by
sending an all zero tentative IID.
The peer endpoint may be configured in one of three modes:
• Peer may: the remote peer may suggest an IID, but most allow a
Configure-NAK with an alternate address to override its setting.
• Peer must: the remote peer must set the IID, which the local peer
accepts.
• Local must: the local peer must supply the IID.
One IID can be sent in each Configuration-Request. A zero value may be
sent, in which case, the peer may send an IID in its response. Either node
on the link can provide the valid, non-zero IID values for itself and its
peer.
The tentative, or assigned IID in the Peer - Local Must case, may be
assigned from one of four sources:
• Last Negotiated: the last negotiated interface-identifier.
• MAC Based: an address derived from the port’s MAC address.
• IPv6: an IPv6 format address.
• Random: a randomly generated value.
See IPv6 Interface Identifiers as follows for more information.
• OSI Network Layer Control Protocol (OSINLCP): A single option is
provided for this NCP protocol. If a non-zero value for alignment has been
negotiated, subsequent ISO traffic (for example, IS-IS) arrives with or be
sent with 1 to 3 zero pads inserted after the protocol header as per RFC
1377.
• MPLS Network Control Protocol (MPLSCP): No options are currently
available for this protocol setup.

2 Ixia Hardware
IPv6 Interface Identifiers (IIDs)
IIDs comprise part of an IPv6 address, as shown in Figure 2-26 on page 2-38 for
a link-local IPv6 address.
Note: The IPv6 Interface Identifier is equivalent to EUI-64 Id in the Protocol

Interfaces window.
Figure 2-26. IPv6 Address Format—Link-Local Address
The IPv6 Interface Identifier is derived from the 48-bit IEEE 802 MAC address
or the 64-bit IEEE EUI-64 identifier. The EUI-64 is the extended unique
identifier formed from the 24-bit company ID assigned by the IEEE Registration
Authority, plus a 40-bit company-assigned extension identifier, as shown in
Figure 2-27 on page 2-38
Figure 2-27. IEEE EUI-64 Format
To create the Modified EUI-64 Interface Identifier, the value of the universal/
local bit is inverted from ‘0’ (which indicates global scope in the company ID) to
‘1’ (which indicates global scope in the IPv6 Identifier). For Ethernet, the 48-bit
MAC address may be encapsulated to form the IPv6 Identifier. In this case, two
bytes ‘FF FE’ are inserted between the company ID and the vendor-supplied ID,
and the universal/local bit is set to ‘1’ to indicate global scope. An example of an
Interface Identifier based on a MAC address is shown in Figure 2-28 on page 2-
39.

Ixia Hardware
Figure 2-28. Example—Encapsulated MAC in IPv6 Interface Identifier
Retry Parameters
During the process of negotiation, the port uses three Retry parameters. RFC
1661 specifies the interpretation for all of the parameters.
HDLC
Both standard and Cisco proprietary forms of HDLC (High-level Data Link
Control) are supported.
Frame Relay
Packets may be wrapped in frame relay headers. The DLCI (Data Link
Connection Identifier) may be set to a fixed value or varied algorithmically.
DSCP—Differentiated Services Code Point
Differentiated Services (DiffServ) is a model in which traffic is treated by

intermediate systems with relative priorities based on the type of services (ToS)
field. Defined in RFC 2474 and RFC 2475, the DiffServ standard supersedes the
original specification for defining packet priority described in RFC 791. DiffServ
increases the number of definable priority levels by reallocating bits of an IP
packet for priority marking.
The DiffServ architecture defines the DiffServ (DS) field, which supersedes the
ToS field in IPv4 to make Per-Hop Behavior (PHB) decisions about packet
classification and traffic conditioning functions, such as metering, marking,
shaping, and policing.
Based on DSCP or IP precedence, traffic can be put into a particular service

class. Packets within a service class are treated the same way.
The six most significant bits of the DiffServ field are called the Differential
Services Code Point (DSCP).
The DiffServ fields in the packet are organized as shown in Figure 2-29 on page
2-40. These fields replace the TOS fields in the IP packet header.

2 Ixia Hardware
Figure 2-29. DiffServ Fields
The DiffServ standard utilizes the same precedence bits (the most significant bits
are DS5, DS4, and DS3) as TOS for priority setting, but further clarifies the
definitions, offering finer granularity through the use of the next three bits in the
DSCP. DiffServ reorganizes and renames the precedence levels (still defined by
the three most significant bits of the DSCP) into these categories (the levels are
explained in greater detail in this document). Figure 2-10 on page 2-40 shows the
eight categories.
Table 2-10. DSCP Categories
Precedence Level Description
7 Stays the same (link layer and routing protocol keep

alive)
6 Stays the same (used for IP routing protocols)
5 Express Forwarding (EF)
4 Class 4
3 Class 3
2 Class 2
1 Class 1
0 Best Effort
With this system, a device prioritizes traffic by class first. Then it differentiates
and prioritizes same-class traffic, taking the drop probability into account.
The DiffServ standard does not specify a precise definition of ‘low,’ ‘medium,’
and ‘high’ drop probability. Not all devices recognize the DiffServ (DS2 and
DS1) settings; and even when these settings are recognized, they do not
necessarily trigger the same PHB forwarding action at each network node. Each
node implements its own response based on how it is configured.
Assured Forwarding (AF) PHB group is a means for a provider DS domain to

offer different levels of forwarding assurances for IP packets received from a
customer DS domain. Four AF classes are defined, where each AF class is in
each DS node allocated a certain amount of forwarding resources (buffer space
and bandwidth).
Classes 1 to 4 are referred to as AF classes. The following table illustrates the

DSCP coding for specifying the AF class with the probability. Bits DS5, DS4,

Ixia Hardware
and DS3 define the class, while bits DS2 and DS1 specify the drop probability.
Bit DS0 is always zero.
Table 2-11. Drop Precedence for Classes
Drop Class 1 Class 2 Class 3 Class 4
Low 001010 010010 011010 100010

AF11 AF21 AF31 AF41
DSCP 10 DSCP 18 DSCP 26 DSCP 34
Medium 001100 010100 011100 100100

AF12 AF 22 AF32 AF42
High 001110 010110 011110 100110

AF13 AF23 AF33 AF43
ATM
The ATM load module enables high performance testing of routers and
broadband aggregation devices such as DSLAMs and PPPoE termination
systems.
The ATM module is provided with various feature combinations:

• Interfaces: pluggable PHYs:
• 1310nm multimode optics with dual -SC connectors
• SFP socket
• Speeds: OC3 and OC12
• Encapsulations:
• LLC/SNAP
• LLC/NLPID
• LLC Bridged Ethernet
• LLC Bridged Ethernet without FCS
• VC Mux Routed
• VC Mux Bridged Ethernet
• VC Mux Bridged Ethernet without FCS
• Multiple independent data streams
ATM is a point-to-point, connection-oriented protocol that carries traffic over

‘virtual connections/circuits’ (VCs), in contrast to Ethernet connectionless LAN
traffic. ATM traffic is segmented into 53-byte cells (with a 48-byte payload), and
allows traffic from different Virtual Circuits to be interleaved (multiplexed).
Ixia’s ATM module allows up to 4096 transmit streams per port, shared across up
to 15 interleaved VCs.

2 Ixia Hardware
To allow the use of a larger, more convenient payload size, such as that for
Ethernet frames, ATM Adaptation Layer 5 (AAL5) was developed. It is defined
in ITU-T Recommendation I.363.5, and applies to the Broadband Integrated
Services Digital Network (B-ISDN). It maps the ATM layer to higher layers. The
Common Part Convergence Sublayer-Service Data Unit (CPSU-SDU) described
in this document can be considered an IP or Ethernet packet. The entire CPSU-
PDU (CPCS-SDU plus PAD and trailer) is segmented into sections which are
sent as the payload of ATM cells, as shown in Figure 2-30 on page 2-42, based
on ITU-T I.363.5.
Figure 2-30. Segmentation into ATM Cells
The Interface Type can be set to UNI (User-to-Network Interface) format or NNI
(Network-to-Node Interface aka Network-to-Network Interface) format. The 5-

Ixia Hardware
byte ATM cell header is different for each of the two interfaces, as shown in
Figure 2-31. ATM Cell Header for UNI and NNI
ATM OAM Cells
OAM cells are used for operation, administration, and maintenance of ATM
networks. They operate on ATM's physical layer and are not recognized by
higher layers. Operation, Administration, and Maintenance (OAM) performs
standard loopback (end-to-end or segment) and fault detection and notification
Alarm Indication Signal (AIS) and Remote Defect Identification (RDI) for each
connection. It also maintains a group of timers for the OAM functions. When
there is an OAM state change such as loopback failure, OAM software notifies
the connection management software.
The ITU-T considers an ATM network to consist of five flow levels. These levels
are illustrated in Figure 2-32 on page 2-44.

2 Ixia Hardware
Figure 2-32. Maintenance Levels
The lower three flow levels are specific to the nature of the physical connection.
The ITU-T recommendation briefly describes the relationship between the
physical layer OAM capabilities and the ATM layer OAM.
From an ATM viewpoint, the most important flows are known as the F4 and F5
flows. The F4 flow is at the virtual path (VP) level. The F5 flow is at the virtual
channel (VC) level. When OAM is enabled on an F4 or F5 flow, special OAM
cells are inserted into the user traffic.
Four types of OAM cells are defined to support the management of VP/VC
connections:
• Fault Management OAM cells. These OAM cells are used to indicate
failure conditions. They can be used to indicate a discontinuity in VP/VC
connection or may be used to perform checks on connections to isolate
problems.
• Performance Management OAM cells. These cells are used to monitor
performance (QoS) parameters such as cell block ratio, cell loss ratio and
incorrectly inserted cells on VP/VC connections.

Ixia Hardware
• Activation-deactivation OAM cells. These OAM cells are used to activate

and deactivate the generation and processing of OAM cells, specifically
continuity check (CC) and performance management (PM) cells.
• System management OAM cells. These OAM cells can be used to
maintain and control various functions between end-user equipment.Their
content is not specified by I.610, and they are limited to end-to-end flows.
The general format of an OAM cell is shown in Figure 2-33 on page 2-45.
Figure 2-33. OAM Cell Format
The header indicates which VCC or VPC an OAM cell belongs to. The cell
payload is divided into five fields. The OAM-type and Function-type fields are
used to distinguish the type of OAM cell. The Function Specific field contains
information pertinent to that cell type. A 10 bit Cyclic Redundancy Check (CRC)
is at the end of all OAM cells. This error detection code is used to ensure that
management systems do not make erroneous decisions based on corrupted OAM
cell information.
Ixia ATM modules allows to configure Fault Management and

Activation/Deactivation OAM Cells.
BERT
Bit Error Rate Test (BERT) load modules are packaged as both an option to
OC48, POS, and 10GE load modules and as BERT-only load modules. As
opposed to all other types of testing performed by Ixia hardware and software,
BERT tests operate at the physical layer, also referred to as OSI Layer 1. POS
frames are constructed using specific pseudo-random patterns, with or without
inserted errors. The receive circuitry locks on to the received pattern and checks
for errors in those patterns.
Both unframed and framed BERT testing is available. Framed testing can be
performed in both concatenated and channelized modes with some load modules.
The patterns inserted within the POS frames are based on the ITU-T O.151
specification. They consist of repeatable, pseudo-random data patterns of
different bit-lengths which are designed to test error and jitter conditions. Other
constant and user-defined patterns may also be applied. Furthermore, you may
control the addition of deliberate errors to the data pattern. The inserted errors are
limited to 32-bits in length and may be interspersed with non-errored patterns
and repeated for a count. This is illustrated in Figure 2-34 on page 2-46. In the
figure, an error pattern of n bits occurs every m bits for a count of 4. This error is
inserted at the beginning of each POS data block within a frame.

2 Ixia Hardware
Figure 2-34. BERT Inserted Error Pattern
Errors in received BERT traffic are visible through the measured statistics, which
are based on readings at one-second intervals. The statistics related to BERT are
described in the Available Statistics appendix associated with the Ixia Hardware
Guide and some other manuals.
Available/Unavailable Seconds
Reception of POS signals can be divided into two types of periods, depending on
the current state—‘Available’ or ‘Unavailable,’—as shown in Figure 2-35 on
page 2-46. The seconds occurring during an unavailable period are termed
Unavailable Seconds (UAS); those occurring during an available period are
termed Available Seconds (AS).
Figure 2-35. BERT—Unavailable/Available Periods
These periods are defined by the error condition of the data stream. When 10
consecutive SESs (A in the figure) are received, the receiving interface triggers
an Unavailable Period. The period remains in the Unavailable state (B in the
figure), until a string of 10 consecutive non-SESs is received (D in the figure),
and the beginning of the Available state is triggered. The string of consecutive
non-SESs in C in the figure was less than 10 seconds, which was insufficient to
trigger a change to the Available state.

Ixia Hardware
Port Transmit The Ixia module ports format data to be transmitted in a hierarchy of structures:
Capabilities • Streams and Flows—A set of related packet bursts
• Bursts and the Inter-Burst Gap (IBG)—A repetition of packets
• Packets and the Inter-Packet Gap (IPG)—Individual packets/
frames
Timing of transmitted data is performed by the use of inter-stream, -burst, and -

packet gaps. Ethernet modules use all three types of gaps, programmed to the
resolution of their internal clocks. POS modules gaps are implemented by use of
empty frames and the resolution of the gap is limited to a multiple of such
frames. ATM modules do not use inter-stream or inter-packet gaps, and instead
control the transmission rate through empty frames. The three types of gaps are
discussed in:
• Streams and the Inter-Stream Gap (ISG) on page 2-50
• Bursts and the Inter-Burst Gap (IBG) on page 2-50
• Packets and the Inter-Packet Gap (IPG) on page 2-51
The percentage of line rate usage for ports is determined using the following
formula:
(packet size + 12 byte IPG + requested preamble)/
(packet size + requested IPG + requested preamble) * 100
Streams and Flows
The Ixia system uses sophisticated models for the programming of data to be
transmitted. There are two general modes of scheduling data packets for
transmission:
• Sequential: The first configured stream in a set of streams is transmitted
completely before the next one is sent, and so on, until all of the configured
streams have been transmitted. Two types are available:
• Packet Streams
• Packet Flows (available on certain modules)
• Interleaved: The individual packets in the streams are multiplexed into a
single stream, such that the total packet rate is the sum of the packet rates
for each of the streams. One type is available:
• Advanced Streams (Advanced Stream Scheduler feature)
ATM modules support up to 15 independent stream queues, each of which may

contain multiple streams. Up to 4096 total streams may be defined. See Stream
Queues on page 2-49.
Packet Streams
This sequential transmission model is supported by the Ixia load modules, where
dedicated hardware can be used to generate up to 255 Packet Streams ‘on-the-

2 Ixia Hardware
fly,’ with each stream consisting of up to 16 million bursts of up to 16 million

packets each. Transmission of the entire set of packet streams may be repeated
continuously for an indefinite period, or repeated only for a user-specified count.
The variability of the data within the packets is necessarily generated
algorithmically by the hardware transmit engine.
Note: Streams consisting of only one packet are not transmited at wire speed.
Also, streams set to random frame size generation does not have accurate IP
checksum information. See the IxExplorer Users Guide, Chapter 4, Stream and
Flow Control, for more information on creating streams.
Packet Flows
A second sequential data transmission model is supported by software for any

Ixia port which supports Packet Flows. An individual packet flow can consist of
from 1 to 15,872 packets. For packet flows consisting of only one unique packet
each, a maximum of 15,872 individual flows can be transmitted. Because the
packets in each of the packet flows is created by the software, including User
Defined Fields (UDF) and checksums, and then stored in memory in advance of
data transmission, there can be more unique types of packets than is possible with
streams. Continuous transmission cannot be selected for flows, but by using a
return loop, the flows can be retransmitted for a user-defined count.
Packet streams, which can contain larger amounts of data, are based on only one
packet configuration per stream. In contrast, many packet flows can be
configured for a single data transmission, where each flow consists of packets
with a configuration unique to that flow. Some load modules permit saving/
loading of packet flows.
Advanced Streams
A third type of stream configuration is called Advanced Streams, which involves

interleaving of all defined streams for a port into a single, multiplexed stream.
Each stream is assigned a percentage of the maximum rate. The frames of the
streams are multiplexed so that each stream’s long-term percentage of the total
transmitted data rate is as assigned. When the sum of all of the streams is less
than 100% of the data rate, idle bytes are automatically inserted into the
multiplexed stream, as appropriate.

Ixia Hardware
Figure 2-36. Example of Advanced Stream Generation
Stream Queues
Stream queues allow standard packet streams to be grouped together. Up to 15

stream queues may be defined, each containing any number of streams so long as
the total number of streams in all queues for a port does not exceed 4,096. Each
queue is assigned a percentage of the total and traffic is mixed as in advanced
streams. Each queue may represent any number of VPI/VCI pairs; the VPI/VCI
pairs may also be generated algorithmically.
Basic Stream Operation
When multiple transmit modes are available, the transmit mode for each port
must be set by you to indicate whether it uses streams, flows, or advanced stream
scheduling. The programming of sequential streams or flows is according to the
same programming model, with a few exceptions related to continuous bursts of
packets. Since the model is identical in both cases, we refer to both streams and
flows as ‘streams’ while discussing programming.
There are three basic types of sequential streams:

• Continuous Packet: A continuous stream of packets. The packets are not
necessarily identical; their contents may vary significantly. (Not available for
packet flows.)
• Continuous Burst: A set of counted packets within a burst; the burst is
repeated continuously. (Not available for packet flows.)
• Counted Burst (non-continuous): A user-specified number of bursts per
stream, where each burst contains a counted number of packets.
Each non-continuous stream is related to the next stream by one of four modes:
• Stop after this stream: Data transmission stops after the completion of the
current stream. (For example, after transmission of a stream consisting of
10 bursts of 100 packets each.)

2 Ixia Hardware
• Advance to Next: Data transmission continues on to the next stream after

the completion of the current stream.
• Return to ID: After the completion of the current stream, a previous stream
(designated by its Stream ID) is retransmitted once, and then transmission
stops.
• Return to ID for Count: After the completion of the current stream, a
previous stream (designated by its Stream ID) is retransmitted for the user-
specified number of times (count), and then transmission stops.
If a Continuous Packet or Continuous Burst stream is used, it becomes the last

stream to be applied and data transmission continues until a Stop Transmit
operation is performed.
Streams and the Inter-Stream Gap (ISG)
A programmable Inter-Stream Gap (ISG) can be applied after each stream, as

pictured in Figure 2-37 on page 2-50.
Figure 2-37. Inter-Stream Gap (ISG)
The size and resolution of the Inter-Stream Gaps depends on the particular Ixia
module in use. For all modules except 10 Gigabit Ethernet modules, the stream
uses the parameters set in the following stream. In 10 Gigabit Ethernet modules,
it uses the parameters set in the preceding stream. There are no ISGs before
Advanced Scheduler Streams. For non-Ethernet modules, the ISG is
implemented by use of empty frames and the resolution of the ISG is limited to a
multiple of such frames.
Bursts and the Inter-Burst Gap (IBG)
Bursts are sets of a specified number of packets, separated by programmed gaps

between the sets. For Ethernet modules, Inter-Burst Gaps (IBG) are inserted
between the sets. For POS modules, bursts of packets are separated by Burst
Gaps. ATM modules do not insert IBGs. The size and resolution of these gaps
depends on the type of Ixia load module in use. The placement of Inter-Burst
Gaps is shown in Figure 2-38 on page 2-51.

Ixia Hardware
Figure 2-38. Inter-Burst Gap (IBG)/Burst Gap
Packets and the Inter-Packet Gap (IPG)
Streams may contain a counted number of frames, or a continuous set of frames

when Continuous Packet mode is used. Frames are separated by programmable
Inter-Packet Gaps (IPGs), sometimes referred to as Inter-Frame Gaps (IFGs).
The size and resolution of the Inter-Packet Gaps depends on the particular Ixia
module in use. For non-Ethernet modules, the ISG is implemented by use of
empty frames and the resolution of the IPG is limited to a multiple of such
frames. ATM modules do not insert IBGs.The placement of Inter-Packet Gaps is
shown in Figure 2-39 on page 2-51.
Figure 2-39. Inter-Packet Gap (IPG)
Frame Data
The contents of every frame and packet are programmable in terms of structure
and data content. The programmable fields are:
• Preamble or Header contents
• Ethernet modules: Preamble Size: The size and resolution depends on the
particular Ixia load module used.
• POS modules: Minimum Flag and Header contents: The minimum number
of flag fields to precede the packet within the POS frame and the type of
encapsulation/signalling.
• ATM modules: Header contents.
• Frame size: The size and resolution depends on the particular Ixia load
module used.
• Destination and Source MAC Addresses (Ethernet only): Allows the MAC
addresses to be set to constants, vary randomly, or increment/decrement using
a mask.

2 Ixia Hardware
• Data generators: Five different data generators are available. These

generators are listed as follows, in order of increasing priority (from top to
bottom). The values from generators located lower in this list override data
from those higher in the list.
• Protocol-related data: Formatted to correspond to particular data link,
transport, and protocol conventions.
• Data link layer controls for Ethernet allow for Ethernet II/SNAP,
802.3 Raw and 802.3 IPX formatting, with support for VLANs,
MPLS, and Cisco-proprietary ISL. VLANs are described in Virtual
LANs on page 2-52
• Protocol-specific data for formatting IPv4, IPv6, and IPX packets
(such as Source and Destination IP addresses), as well as Layer 4
transport protocol headers (TCP/IP, IGMP, and so on) are also
supported. IPv4/IPv6 and IPv6/IPv4 tunneling is also supported.
• IP Source and Destination addresses may be incremented or
decremented using a network mask.
• Data Patterns: Can be one of three types: predefined patterns up to 8K
bytes in length, randomly generated data, algorithmically generated data,
industry standard (such as CJPAT and CRPAT) or user-specified.
• User Defined Fields (UDFs): A number of 32-bit counters. For some
modules the counters can each be flexibly configured as multiple 8, 16, 24,
and 32-bit counters. Each counter may independently increment or
decrement using a mask. These are further described in User Defined
Fields (UDF) on page 2-55.
• Frame Identity Record (FIR): An identity record stored at the end of the
packet. The information is very useful for determining the source of
transmitted data found in capture buffers.
• Frame Check Sequence (FCS): The checksum for a packet may be omitted,
formatted correctly, or have deliberate errors inserted. Deliberate errors
include incorrect checksum, dribble errors, and alignment errors.
Virtual LANs
Virtual LANs (VLANs) are defined in IEEE 802.1Q, and can be used to create
subdomains without the use of IP subnets. The IEEE 802.1Q specification uses
the explicit VLAN tagging method and port-based VLAN membership. Explicit
tagging involves the insertion of a tag header in the frame by the first switch that
the frame encounters. This tag header indicates which VLAN the packet belongs
to. A frame can belong to only one VLAN.
VLAN tag headers are inserted into the frames, following the source MAC
address. A maximum of 4094 VLANs can be supported, based on the length of
the 12-bit VLAN ID. The VID value is used to map the frame into a specific
VLAN. VLAN IDs 0 and FFF are reserved. VID = 0 indicates the null VLAN ID,
which means that the tag header contains only user priority information.
An example of Layer 2 broadcast domain without VLANs is shown in Figure 2-

40 on page 2-53.

Ixia Hardware
Figure 2-40. Example of Broadcast Domain Without VLANs
In the example above, a company has four departments (Sales, and so forth)
which are in one switched broadcast domain. Broadcasts are flooded to all of the
devices in the domain. A router sends/receives Internet traffic. In Figure 2-41 on
page 2-54, the departments have been grouped into two separate VLANs, cutting
down on the amount of broadcast traffic. For example, VLAN 20 contains Ports
1, 2, 3, and 6 on Switch 1, and Ports 1, 2, 3, and 6 on Switch 2. VLAN 21
contains Ports 4, 5, and 6 on Switch 1, and Ports 1, 4, 5, and 6 on Switch 2.

2 Ixia Hardware
Figure 2-41. Example of VLANs
With the new network design, switch ports and attached nodes are assigned to
VLANs. Frames are tagged with their VLAN ID as they leave the switch, en
route to the second switch. The VLAN ID indicates to the second switch which
ports to send the frame to. The VLAN tag is removed as the frame exits a port
belonging to that VLAN, on its way to the attached node. With VLANs,
bandwidth is conserved, and security is improved. Communication between the
VLANs is handled by the existing Layer 3 router.
Stacked VLANs (Q in Q)
VLAN Stacking refers to a mechanism where one VLAN (Virtual Local Area
Network) may be encapsulated within another VLAN. This allows a carrier to
partition the network among several networks, while allowing each network to
still utilize VLANs to their full extent. Without VLAN stacking, if one network
provisioned an end user into ‘VLAN 1,’ and another network provisioned one of
their end users into ‘VLAN 1,’ the two end users would be able to see each other
on the network.
VLAN stacking solves this problem by embedding each instance of the 802.1Q
VLAN protocol into a second tier of VLANs. The first network is assigned a
‘Backbone VLAN,’ and within that Backbone VLAN a unique instance of
802.1Q VLAN tags may be used to provide that network with up to 4096 VLAN
identifiers. The second network is assigned a different Backbone VLAN, within
which another unique instance of 802.1Q VLAN tags is available.
Figure 2-42 on page 2-55 demonstrates an example packet of a stacked VLAN.

Ixia Hardware
Figure 2-42. Stacked VLAN Header Information
User Defined Fields (UDF)
Seven different types of UDFs are available, depending on the load module type.
The types of UDFs that are supported by particular port types is detailed in
Chapter 1, Platform and Reference Overview. Not all features supported by a port
type are available on all UDFs; whether a particular UDF type is supported on a
particular UDF can be ascertained by looking at the UDF with IxExplorer or
programatically using the Tcl API. These types are:
• Counter Mode UDF
• Random Mode UDF
• Value List Mode UDF
• Range List Mode UDF
• Nested Counter Mode UDF
• IPv4 Mode UDF
• Table Mode UDF
Some features are common across all UDFs:

• Counter Type: The size of the counter is available in two modes:
• A single counter with a length of 8, 16, 24 or 32 bits, or
• A 32-bit value that may be divided into one to four 8 to 32 bit
counters in any order. For example, 8x8x8x8 (four 8-bit counters),
8x16 (an 8-bit counter followed by a 16 bit counter), or 24x8 (a 24-
bit counter followed by an 8-bit counter). In this case, each of the
up to four counters may be independently controlled as described in
Counter Mode UDF.
• Offset: The offset from the beginning of the packet to the start of the
counter.
• Init val: The initial value given to the counter.
• Cascade: Sets the initial value for the counter, in one of two ways:
• From the last value for this stream: The counter continues from the
last value generated by this UDF for this stream. The first value for

2 Ixia Hardware
the counter is set from the Init val setting. This type of cascade is
sometimes referred to as Cascade From Self.
• From the last value on the previous cascade stream: The counter
continues from the last value generated by the last executed stream
using this UDF that is also in this cascade mode. The first value for
the first UDF is set from the Init val setting. This type of cascade is
sometimes referred to as Cascade From Previous Stream.
• Masking: The bit masking operation allows certain bits to maintain
constant values, while varying other values. In the IxExplorer GUI, a bit
mask is represented as a string of characters, one character per counter bit.
For example, a possible Bit Mask setting for an 8-bit counter might be:
0110XXXX
The ‘0’s and ‘1’s represent fixed values after the mask value, while the
‘X’s are bits which vary as a result of the increment, decrement or random
value option.
In the TCL/C++ APIs, the Bit Mask value is split into two variables:
• maskSelect: Indicates which bits of the counter are fixed in value,
and
• maskval: Indicates the fixed value for any of the bits set in
maskSelect.
In all of the UDF figures, the generated counter value is shaded. The parameters
are shown in ovals (blue in the online version).
Counter Mode UDF
The counter mode UDF features the ability of a counter (up to four on some load
modules) to count up or down or to use random values. Certain bits of the counter
may be held at fixed values using a mask. The parameters that affect the
counter’s operation are shown in Table 2-12 on page 2-56.
Table 2-12. Counter Mode UDF Parameters
IxExplorer Label Tcl API Variables
Counter Type countertype
Offset offset
Init Value initval
Set from Init Value cascadeType

Continue from last value for this stream enableCascade
Cascade continue
Random* random
Continuously Counting continuousCount
Step step
Repeat Count repeat

Ixia Hardware
Table 2-12. Counter Mode UDF Parameters
Mode updown
Bit Mask maskval

maskselect
* some card types include random mode as part of the counter mode and others
use them as a separate mode.
In the TCL APIs the value of the counterMode variable in the udf command
should be set to udfCounterMode (0). The operation of counter mode is described
in the flowchart shown in Figure 2-43 on page 2-57.
Figure 2-43. UDF Counter Mode Operation
Random Mode UDF
The random mode UDF features a counter whose values are randomly generated,
but may be masked. Cascading modes do not apply to random mode UDFs. The
parameters that affect the counter’s operation are shown in Table 2-13 on page 2-
57.
Table 2-13. Random Mode UDF Parameters
Offset offset
Bit Mask maskval

maskselect

2 Ixia Hardware
should be set to udfRandomMode (1). The operation of random mode is
described in the flowchart shown in Figure 2-44 on page 2-58.
Figure 2-44. UDF Random Mode Operation
Value List Mode UDF
The value list mode UDF features a counter whose values successively retrieved
from a table of values. Cascading modes do not apply to value list mode UDFs.
The parameters that affect the counter’s operation are shown in Table 2-14 on
page 2-58.
Table 2-14. Value List Mode UDF Parameters
Offset offset
Data valueList

should be set to udfValueListMode (2). The operation of value list mode is

Ixia Hardware
Figure 2-45. UDF Value List Mode Operation
Range List Mode UDF
The range list mode UDF features a counter whose values are generated from a
list of value ranges. Each range has an initial value, repeat count, and step value.
Cascading modes do not apply to range list mode UDFs. The parameters that
affect the counter’s operation are shown in Table 2-15 on page 2-59.
Table 2-15. Range List Mode UDF Parameters
Offset offset
Init Value initval
Repeat Count repeat
Step step

should be set to udfRangeListMode (4). The initval, repeat, and step values are
added into the udf command by the addRange sub-command. The operation of
range list mode is described in the flowchart shown in Figure 2-46 on page 2-60.

2 Ixia Hardware
Figure 2-46. UDF Range List Mode Operation
Nested Counter Mode UDF
The nested counter mode UDF features a counter whose values are generated
from three nested loops:
1. A given value may be repeated a number of times.
2. That value is incremented and step 1 is repeated for a count. This is called the
inner loop.
3. That value is incremented and steps 1 and 2 repeated continuously for a
count. This is called the outer loop.
The parameters that affect the nested counter’s operation are shown in Table 2-16
on page 2-60.
Table 2-16. Nested Counter Mode UDF Parameters
Offset offset
Init Value initval
Inner Loop: Repeat value innerRepeat
Inner Loop: increment value innerStep
Inner Loop: loop innerLoop
Outer Loop:increment value step

Ixia Hardware
Table 2-16. Nested Counter Mode UDF Parameters
Outer Loop: loop continuously continuousCount
Outer Loop: repeat outer loop repeat

should be set to udfNestedCouterMode (3). The operation of range list mode is
Figure 2-47. UDF Nested Counter Mode Operation

2 Ixia Hardware
IPv4 Mode UDF
The IPv4 counter mode UDF features a counter designed to be used with IPv4
addresses. The process is:
1. A given value may be repeated a number of times. Values with all ‘1’s and
‘0’s in a particular part of the value may be skipped so as to avoid broadcast
addresses. The number of low order bits to check for ‘0’s and ‘1’s can be set.
2. That value is incremented and step 1 is repeated continuously or for a count.
page 2-62.
Table 2-17. IPv4 Mode UDF parameters
Offset offset
Init Value initval
Loop: Repeat value innerRepeat
Loop: increment by innerStep
Repeat Loop: Continuously continuousCount
Repeat Loop: times repeat
Skip all zeros and ones enableSkipZerosAndOnes
masked with skipMaskBits

The operation of IPv4 mode is described in the flowchart shown in Figure 2-46
on page 2-60.

Ixia Hardware
Figure 2-48. UDF IPv4 Mode Operation
Table Mode UDF
Table UDFs allows to specify a number of lists of values to be placed at

designated offsets within a stream. Each list consists of an Offset, a Size, and a
list of values.

2 Ixia Hardware
Figure 2-49 on page 2-64 illustrates the basic operation of the Table UDFs using
a GRE encapsulated packet as an example. Four of the fields in the packets need
to be modified on a packet by packet basis—the key and sequence GRE fields
and the source and destination IP addresses in the IP header. The Table UDF
provides a means by which lists are developed for each of these fields and the list
is associated with an offset and size within the packet. During stream generation,
all lists are applied at the same time in lock step.
Figure 2-49. Table UDF Mode
A Table UDF is applied before, and can be combined with, the standard UDF
fields already available on ports. By combining these two features you can model
multiple flows using the powerful combination of a value list group for flow
identity fields and UDFs for protocol related timestamp/sequence fields.
Table Mode UDF has a limitation compared to the other UDFs. Specifically,
Table Mode behaves differently when Random Data payload is enabled for the
frame.
Most UDFs are attached to the frame after the Random Data is placed in the
frame; the UDFs ‘overlay’on top of the random data. The Table Mode UDF data,
however, is put in the frame before the random data. As a result, the payload is
random only after the Table UDF.
For example, if a frame has a Table UDF that is 1 byte wide starting at offset 100,
random data cannot appear in the payload until byte 101. Thus, the first 100 of
these frames would have the same ‘random’ data appear within the first 99 bytes
of the payload—for all 100 frames. The data would truly appear random starting
at byte 101, after the Table UDF insertion.
This is the same limitation currently for random data packets that have PGID or
Data Integrity enabled.

Ixia Hardware
page 2-65.
Table 2-18. Table Mode UDF Parameters
Offset offset
Init Value initval
Add Column addColumn
Add Row addRow
Clear All Columns clearColumns
Get First Column getFirstColumn
Get Next Column getNextColumn
Clear All Rows clearRows
Get First Row getFirstRow
Get Next Row getNextRow
Export to File export
Import from File import
Transmit Operations
The transmit operations may be performed across any set of chassis, cards, and
ports specified by you. These operations are described in Table 2-19 on page 2-
65.
Table 2-19. Transmit Operations
Operation Usage
Start Transmit Starts the transmission operation on all ports included in

the present set of ports. If no transmit operation has been
performed yet, or if the last operation was Stop Transmit,
then transmission begins with the first stream configured
for each port. If a Pause Transmit operation was last
performed, then transmission begins at the next packet in
the queue for all ports.
Staggered Start The same operation is performed as in Start Transmit,

Transmit except that the start operation is artificially staggered
across ports. The time interval between the start of
transmission on consecutive ports is in the range of 25-
30ms.
Stop Transmit Stops the transmission operation on all ports included in

the present set of ports. A subsequent Start Transmission
or Step Stream operation commences from the first stream
of each port.

2 Ixia Hardware
Table 2-19. Transmit Operations
Operation Usage
Pause Transmit Stops the transmission operation on all ports in the present
set of ports at the end of transmission of the current
packet. A subsequent Start Transmission or Step Stream
commences at the beginning of the next packet in the
queue on each port.
Step Stream Causes one packet to be transmitted from each of the

ports in the present set of ports.
Repeat Last Random Pattern
The 10 GE LSM module transmit engine has the ability to provide repeatable
random values in all its random number generators. This feature allows to run
tests with random parameters such as frame size, frame data, and UDF values to
rerun the tests with the same set of random data if a problem is found. A check
box on the Port Properties transmit tab is used to enable/disable, repeating the
last seed used on the port. In addition to the check box, there is a read-only
window showing the last 32 bit master seed value used in generating seeds for all
random number generators on the port.
Port Data Capture Capabilities
Most ports have an extensive buffer which may be used either to capture the
packet data ‘raw’ as it is received, or to categorize it into groups known as Port
Groups. Each port must be designated to have a Receive mode which is either
Capture or Packet Groups. Packet groups are used in measuring latency.
The start of capture buffering may be triggered by a set of matching conditions

applied to the incoming data, or all data may be captured. Packets can be filtered,
as well. During capture mode operation, the amount of data saved in the capture
buffer can be limited to a user-defined ‘capture slice’ portion of each incoming
packet, rather than the entire packet.
Each port’s Capture trigger and filter conditions are based on:
• For Ethernet Modules:
• Data link encapsulation type
• Destination and source MAC addresses
• Protocol layer type: such as IP, IPv6, and ARP
• IPv4 and IPv6 source and destination addresses
• TCP and UDP port numbers
• VLAN IDs
• For POS Modules:
• Use of PPP

Ixia Hardware

• For ATM Modules:
• VPI and VCI combinations
• ATM OAM cells
• Data pattern match for the packet, and matching errors such as: Bad CRC,
Bad Packet, Alignment Error, and Dribble Error
• Packet sizes within a user-specified range
Continuous Versus Trigger Capture
For some load modules, there are more advanced options provided for setting up
data capture operations on a port. These options are set in the receive mode
dialog for the port. The available options are described in the following list:
• Continuous Capture. Options are as follows:
• All packets are captured.
• All packets which match a user-defined Capture Filter condition are
captured.
• Trigger Capture:
• Capture operation starts before a packet matching the user-defined Trigger
condition is received. Options are:
• No packets are captured.
• All packets which match a user-defined Capture Filter condition are
captured.
• Capture operation starts after a packet matching the user-defined Trigger
condition is met. Options are:
• All packets that match a user-defined Capture Filter condition are
captured.
• All packets that match the user-defined Trigger Capture condition
are captured.
• Trigger Position: The slider bar is used to set the position (% transmitted)
in the data stream where the Capture Trigger is first applied to incoming
packets.

2 Ixia Hardware
Port Capture Operations
The data capture operations may be performed across any set of chassis, cards,
and ports defined by you. These operations are described in Table 2-20 on page
2-68.
Table 2-20. Capture Operations
Operation Usage
Start Capture Enables data capture on all ports in the set of ports whose
receive mode is set to Capture. Packets are not actually
captured until the user-specified capture trigger condition
is satisfied.
Stop Capture Stops data capture on all ports in the set of ports.
Start Latency Initiates latency measurements for all ports in the set of
ports whose receive mode is set to Packet Group
operation.
Stop Latency Stops latency measurements on all ports in the set of

ports.
Start Collision Enables generation of forced collisions on received data,

for all ports in the set of ports—if this option is selected for
the port and enabled. Applies to half-duplex 10/100
Ethernet connections only.
Stop Collision Stops generation of forced collisions for all ports in the set
of ports.
Forced Collision Operation
In addition to normal capture operation, forced collisions can be generated on the

receive side of some 10/100/1000 load module ports, but only when the port is in
half-duplex mode.
Forced collisions operate by generating ‘collision’ data as information is being

received on the incoming port. The ‘collision’ takes the form of a number of
nibbles inserted at a user-specified offset within a packet as it is received. A
period with a number of consecutive ‘collisions’ is followed by a period with no
collisions. This combination of collisions and non-colliding periods can be
repeated indefinitely, or repeated for a user-specified number of times. These
parameters are shown in Figure 2-50 on page 2-69.

Ixia Hardware
Figure 2-50. Forced Collisions
Non-Colliding
Colliding Packets Packets Colliding Packets
Collision
Duration
(Individual Packet)
Preamble
Packet Collision
Offset
Packet Group Operation
Packet groups are sets of packets which have matching tags, called Packet Group
IDs. Real-time latency measurements within packet groups depend on
coordination between port transmission and port reception. Each transmitted
packet must include an inserted 4-byte packet ‘group signature’ field, which
triggers the receiving port to look for the packet group ID. This allows the
received data to be recognized and categorized into packet groups for latency
analysis.
Packet group IDs should be used to group similar packets. For example, packet
groups can be used to tag packets connected to individual router ports.
Alternatively, packet groups may be used to tag frame sizes. Such groupings
allow to measure the latency with respect to different characteristics (for
example, router port number or frame size as in the above scenario).
After packet group operation is triggered on the receiving port, the packet group
ID—a 2-byte field which immediately follows the signature—is used as an index
by the port’s receive buffer to store information related to the latency of the
packet. When packet group signatures and packet group IDs are included in
transmitted data, an additional time stamp is automatically inserted into the
packet. Figure 2-51 on page 2-69 shows the fields within packets which are
important for packet grouping and latency analysis.
Figure 2-51. Packet Format for Packet Groups/Latency
A special version of packet groups, known as wide packet groups, uses a 4-byte
packet group ID, of which only the low order 17 bits are active. A mask may be
applied to the matching of the packet group ID. Latency, sequence checking, and

2 Ixia Hardware
first/last timestamps are supported at the same time. Latency over time and data
integrity checking are not supported in this mode. Frames must be greater than or
equal to 64 bytes.
Split Packet Group Operation
Split PGID allows the 32-bit PGID field used to identify and group packets to be
generated from a concatenation of three separate PGID fields. Note that the
method for detecting and determining if a packet has a valid signature is no
different from standard PGID operation. A valid signature is still required before
the concatenated PGID is considered to be valid.
Instead of having one PGID offset value with one mask, you are allowed to enter
up to three separate PGID offsets and masks. The split PGID method works with
both the standard instrumentation method or the floating instrumentation method,
and does not interfere with other features such as time bins and bin by latency.
In addition to having three 16 bit offset values and three 32 bit mask values, the
following possibilities are available for the PGID offset:
• Offset from Start of Frame (Original starting point for PGIDs)
• Offset from End of Floating Instrumentation Pattern Match
• Offset from Start of IP
• Offset from Start of Protocol
The definition of the mask is also different when in split PGID mode. In the
standard PGID mode, the mask is only used to zero out PGID values and not to
change the width of the final PGID. In split PGID mode, the mask is used to
reduce the overall width of the PGID value for that region. A value of 1 in mask
field indicates the bit is discarded (masked out).
The final 32 bit PGID value used is a concatenation of the values extracted based
on the offset/mask combinations provided for the three PGID regions. The final
32 bit PGID is generated by concatenating the three regions as follows: PGID3,
PGID2, and PGID1. If the concatenation of the three regions is not sufficient to
fill the 32 bit value, a padding of 0 is used on the remaining leftmost bits.
Figure 2-52 on page 2-71 demonstrates the three options when employing split
PGIDs.

Ixia Hardware
Figure 2-52. Split PGID Scenarios
Latency/Jitter Measurements
Latency and Jitter can be measured when packet groups are enabled on a
transmitting port and received on a port enabled to receive packet groups. The
difference between the received time and the transmitted time held in the
packet’s time stamp is the measured latency or jitter. The latency is included in a
memory cell indexed by the packet group ID. The count of packets received,
minimum, maximum, average, and mean latencies are maintained. There are two
modes for latency measurement:
• Instantaneous: Latency measured for all received data (continuous). The
number of PGID groups available depends on the features being employed
on the receive side. The PGID is used as an index into an area of cells and
the count/min/max/avg/mean is maintained for each PGID.
• Latency over time: Latency measured for a number of time intervals of
equal length, called ‘time buckets.’ The range of cells is divided up over a
period of time—for example, for one second intervals over a 30 second
period. Each time period (one second in this example) is called a time
bucket. Within each time bucket, the data for all PGIDs must be stored into
a limited number of cells. This is accomplished by grouping a number of

2 Ixia Hardware
PGIDs together. The grouping is called the ‘# of PGIDs/Time Bucket’.

Figure 2-53 on page 2-72 demonstrates the relationship between the time
buckets and PGIDs in an example. The minimum size time bucket varies
by port type, but the size set should be reasonable for the transmission
speed of the port—certainly no shorter than 1 microsecond.
Figure 2-53. Multiple Latency Time Measurements—Example
The timeline is equally divided into a # of Time Buckets, each of which is one
Time Bucket Duration in length. A time bucket duration can range anywhere
from nanoseconds to hours, depending on the user configuration.
The maximum number of time buckets that can be handled is determined by the
number of PGIDs in each bucket.
Four types of timing measurements are available, corresponding to the type of

device under test:
• Cut-Through: For use with switches and other devices that operate using
packet header information. The time interval between the first data bit out of
the Ixia transmit port and the first data bit received by the Ixia receive port is
measured. The first data bit received on Ethernet links (10/100 and Gigabit
modules) is the start of the MAC DA field. For Packet over SONET links, the
first bit received is the start of the IP header.
• Store and Forward: For use with routers and other devices that operate on the
contents of the entire packet. The time interval between the last data bit out of
the Ixia transmit port and the first data bit received by the Ixia receive port is
measured. The last data bit out is usually the end of the FCS or CRC, and the
first data bit received is as described above for Cut Through.
NOTE: Store and Forward latency mode is intended to test Store and Forward
switching devices, which receive the entire packet before transmitting it to its
destination. If Store and Forward latency is used in loopback, back-to-back
or without a Store and Forward switch, then either a zero latency or very high
latency is reported.
• Store and Forward Preamble (only available on some load modules): As with
store and forward, but measured with respect to the preamble to the Ethernet
frame. In this case, the time interval between the last data bit out of the Ixia
transmit port and the first preamble data bit received by the Ixia receive port
is measured. For this measurement, the size of the preamble (in bytes) is
considered.
• Inter-Arrival Time (IAT): Compares the time between PGID packet arrivals.
In this case, when a packet with a PGID is received, the PGID is examined. If

Ixia Hardware
a packet has already been received with the same PGID, then the timestamp
of the previous packet is subtracted from the current timestamp. The interval
between the timestamps is the jitter, and it is recorded for statistical purposes.
Sequence Checking Operation
A number of ports have the additional ability to insert a sequence number at a

user-specified position in each transmitted packet. This sequence number is
different and distinct from any IP sequence number within an IP header. On the
receiving port, this special sequence number is retrieved and checked, and any
out-of-sequence ordering is counted as a sequence error.
As in packet groups (see Packet Group Operation on page 2-69), for sequence
checking a signature value is inserted into the packet on the transmit side to
signal the receive side to check the packet. In fact, this particular signature value
is shared by both the packet group and the sequence checking operations. Both
the signature value and sequence number are 4-byte quantities and must start on
4-byte boundaries. These fields are shown in Figure 2-54 on page 2-73.
Figure 2-54. Packet Format for Sequence Checking
Sequence numbers are integers which start at ‘0’ for each port when transmission
is started, and increment by ‘1’ continuously until a Reset Sequence Index
operation is performed. Note that multiple sequence errors results when a packet
is received out of sequence. For example, if five packets are transmitted in the
order 1-2-3-4-5 and received in the order 1-3-2-4-5, three sequence errors are
counted:
1. At 1-3, when packet 2 is missed
2. At 1-3-2, when 2 is received after 3
3. At 1-3-2-4, when 4 is received after 2
Switched-Path Duplicate/Gap Checking Mode
This is a mode in sequence checking that allows for detecting duplicate packets,
or sequence gaps. IxExplorer stores the largest sequence number received. Any
packet that arrives with a lower or equal sequence number is regarded as a
duplicated packet. For a flow with no packet reordering, the ‘reversal errors’
matches the number of duplicates received. For a flow with packet reordering,
the ‘reversal errors’ gives a count that may be higher than the number of
duplicates received.

2 Ixia Hardware
Data Integrity Checking Operation
A number of ports also possess the ability to check the integrity of data contained
in a received packet, by computing an additional 16-bit CRC checksum.
As with packet groups (see Packet Group Operation on page 2-69) and sequence
checking (see Sequence Checking Operation on page 2-73), a signature value is
inserted into the packet on the transmitting interface, to serve as a trigger for the
receiving port to notice and process the additional checksum. The data integrity
operation uses a different signature value from the one shared by packet groups
and sequence checking.
The data integrity signature value marks the beginning of the range of packet
data over which the 16-bit data integrity checksum is calculated, as shown in
Figure 2-55 on page 2-74. This packet data ends just before the timestamp and
normal CRC/FCS. The CRC-16 checksum value must end on a 4-byte boundary.
There may be 1, 2, or 3 bytes of zeroes (padding) inserted after the CRC-16, but
before the Time Stamp, to enforce all boundary conditions.
Figure 2-55. Packet Format for Data Integrity Checking
When the Receive Mode for a port is configured to check for data integrity,
received packets are matched for the data integrity signature value, and the
additional CRC-16 is checked for accuracy. Any mismatches are recorded as data
integrity errors.
Automatic Instrumentation Signature
The Automatic Instrumentation Signature feature allows the receive port to look
for a signature at a variable offset from the start of frames. The feature supports
Sequence Checking, Latency, Data Integrity functionality, with signature and
Packet Group ID (when Automatic Instrumentation is enabled, these receive port
options are enabled as well).
In normal stream operation, signatures for Data Integrity, Latency, and Sequence
Checking are forced to a single, uniform offset location in each frame of the
stream. Many of the Ixia software application (that is, IxVPN, IxChariot, and so
forth) can generate streams that place a signature at random places within the
frames of a single stream. To accurately detect these signatures on the receive
side of the chassis, Automatic Instrumentation Signature is used.
Automatic Instrumentation Signature allows the chassis to look for a floating

pattern in the frame. Two data blocks are placed in the frame (by some stream
generating application). The first is positioned at a variable offset from the start
of the frame. The second is positioned at a fixed 12 byte offset from the end of
the frame.

Ixia Hardware
Figure 2-56 shows the composition of the blocks.
Figure 2-56. Automatic Instrumentation Signature Block
The receive port recognizes an instrumented frame by detecting the Signature in

the first block. Once a signature match has occurred, the Packet Group ID
(PGID) and Sequence Number are extracted from the frame. Data Integrity also
starts immediately following the signature.
The Checksum Adjust field is reserved for load modules that cannot correctly do
checksums on large frames.
Port Transmit/Receive Capabilities
Round Trip TCP Flows
For most 10/100 load modules, a special capability exists in the Ixia hardware to
enable the measurement of round trip times for IP packets sent through a switch
or other network device. The normal setup for this measurement is shown in
Figure 2-57. RoundTrip TCP Flows Setup
In this scenario, Ports A and X are configured on one IP subnet, and Ports B and
Y are configured on a different IP subnet. IP packets sent from A have a source

2 Ixia Hardware
address of A and destination address of B. The DUT is configured to route or

forward to Y any packets that it receives on X for an address on B-Y’s subnet.
After being received on Port B, the packet is reconstructed in a modified form as
described in the following list, and sent back in the opposite direction along the
path to Port A.
When enabled on the Ixia receiving port (in this case, Port B), the Round Trip
TCP Flows feature performs several operations on the received IP packet:
• The Source and Destination IP addresses are reversed, and a packet destined
for Port A is created using the reversed addresses.
• The frame size, source and destination MAC addresses, and background data
pattern are set as specified by you.
• The timestamp is copied to the new packet unmodified.
• The new packet is transmitted to Port Y on the DUT, and should be routed
back to Port A by the DUT.
This re-assembly/retransmit process makes it possible to measure the round-trip

time for the packet’s trip from Port A through the DUT to Port B, and back
through the DUT to Port A again. Note that the Packet Groups feature may be
used, in addition, for latency measurements on this round trip. For latency
testing, the background data set by the Round Trip TCP Flows feature overwrites
the Packet Group Signature Value contained in the packet. It is important that
proper programming of the background data pattern be used to insert the
appropriate signature value back into the packet.
Port Statistics Capabilities
Each port automatically collects statistics. A wide range of statistics are

preprogrammed and available for many types of load modules. Other statistics
may be selected or programmed and include:
• User-Defined Statistics: Four counters which can be programmed to
increment based on the same conditions as those involved in defining capture
triggers and capture filters.
• Quality of Service Types: Separate counts for each of eight Quality of Service
values used in IP headers.
• IP/UDP/TCP Checksum Verification Statistics: For hardware checksum
verification.
• Data Integrity Statistics: For errors relating to Data Integrity Operation. Refer
to Data Integrity Checking Operation on page 2-74.
• Packet Group Statistics: For statistics relating to Latency operations. Refer to
Latency/Jitter Measurements on page 2-71.
• Protocol Server Statistics: Protocol-based statistics for a wide range of
routing protocols.
• SONET Extended Statistics: Statistics associated with SONET Line, Section
and Path characteristics.
• VSR Statistics: Statistics associated with OC192 VSR modules.
• ATM Statistics: Statistics associated with ATM modules.

Ixia Hardware
• BERT Statistics: Statistics associated with BERT error generation and

detection.
• Temperature Sensors Statistics: For verifying that temperatures on high-
performance 10 Gigabit and OC-192c POS cards are within operational
limits.

2 IxExplorer Software
IxExplorer Software
The IxExplorer software utilizes concepts that match the Ixia hardware
hierarchy. The software hierarchy is:
• Chassis Chain (Software): A set of Ixia chassis joined through sync-in/sync-
out cables.
• Chassis: A single Ixia chassis capable of holding different Ixia module
cards.
• Card: An Ixia module card, all of whose ports have the same
features.
• Port: An individual transmit/capture port on a card.
• Capture View: A view of the capture buffer for the port.
• Filters, Statistics and Receive Mode: A means of programming
capture triggers, filters, and statistics.
• Packet Streams: A means of programming sets of streams and
flows.
• Statistics: A view of the statistics gathered by the port.
• Global Views:
• Port Groups: Hold groups of related ports that may be operated on at the
same time.
• Stream Groups: Hold groups of related ports that may be operated on at the
same time.
• Packet Group Statistic Views: Allows the latency data (including Inter-
Arrival Time) to be collected from one or more ports that are configured to
receive packet groups.
• Statistic Views: Holds groups of related ports, all of whose statistics can be
viewed at one time.
• Stream Statistic Views: Holds groups of related streams, all of whose
statistics can be viewed at one time.
• MII Templates: A means of creating and editing MII templates.
• Layouts: A means of saving open GUI features.
• IxRouter Window: A means of designating interface addresses associated
with ports and programming routing protocol simulations on each port. Note
that IxRouter must be installed for full use of this window. Without IxRouter,
only limited use of ARP and PING are allowed. See IxRouter User Guide for
more information.
Chassis Chain The IxExplorer chassis chain corresponds to the hardware chain. The chain starts
(Software) with a master, whose sync-out line is connected to the sync-in line of the next
chassis, and so on. Multiple chassis chains may be defined in the IxExplorer and
operated independently or at the same time. Various forms of time

IxExplorer Software
synchronization may be used to coordinate multiple chassis chains dispersed

world-wide into a single ‘virtual chassis chain’; see Chassis Synchronization on
page 2-5. The Ixia 100 chassis includes a built-in GPS receiver to provide very
accurate timing.
Chassis The IxExplorer chassis corresponds to an Ixia 1600T, 400T, 250, 100, Optixia
XL10, Optixia XM12, Optixia XM2, Optixia X16 or other chassis capable of
holding Ixia module cards. The name or IP address of each chassis must be input;
the type of the chassis is automatically discovered by the software. A chassis may
hold any mix of module cards.
Card The IxExplorer card corresponds to an Ixia load module card. The types of cards
loaded in a chassis are automatically discovered and the appropriate number of
ports are inserted into the hierarchy. Each port on a card has the same
capabilities.
Port The IxExplorer port corresponds to an individual port on an Ixia module card.
Each port is independently programmed in terms of its transmit, capture and
statistics capabilities. The IxExplorer software shows four separate views for
programming and viewing operations:
• Filters, Statistics and Receive Mode: Sets the trigger and capture conditions
for the capture buffer, conditions for the four user-defined statistics, and the
receive mode for the port.
• Packet Streams/Flows: Defines the streams within stream regions and the
contents of packets.
• Capture View: Shows the data gathered during capture operations. Data is
displayed in raw form and interpreted for some protocols.
• Statistics : Shows the live statistics gathered during transmit and capture
operation.
Port Properties
A Port Properties dialog allows other port related properties to be programmed:

• Auto-Negotiation: Low level physical controls, such as 10 versus 100 Mbps
operation and full duplex versus half duplex.
• Advanced MII controls: Additional low level MII register controls.
• Flow control: Related to pause control operation.
• Collision Backoff Algorithm: Handling of collision situations.
• Forced Collisions: The generation of collision packets on receive ports.
• Transmit mode: The choice of streams or flows for the port.
• SONET Header: For use with Packet Over SONET frames.
• SONET Overhead: For generation of APS (K1/K2), J0/J1 bytes, and Error
Insertion.

• PPP: For use with SONET. Includes dialogs for Negotiation, Link Control
Protocols, and Network Control Protocols.
Port Groups Port groups are an IxExplorer convenience. They allow to perform operations,
such as start/stop transmit, start/stop capture and clear timestamps, for a wide
range of ports all at the same time.
Stream Groups Stream groups are an IxExplorer convenience. They allow to perform operations,
such as start/stop transmit, start/stop capture and clear timestamps, for a group of
streams all at the same time.
Packet Group The Packet Group Statistics View allows the latency data (including Inter-Arrival
Statistic Views Time) to be collected from one or more ports that are configured to receive
packet groups. Packets representing different types of traffic profiles can be
associated with packet group identifiers (PGIDs). The receiving port measures
the minimum, maximum, and average latency in real time for each packet
belonging to different groups. Measurable latencies include Instantaneous
Latency, where each packet is associated with one group ID only, and Latency
Over Time, where multiple PGIDs can be placed in ‘time buckets’ with fixed
durations.
Statistic Views Statistic Views are similar to port groups, in that they let you consider a set of
ports all at once. When a Statistic View group is selected, all of the statistics for
all of the ports are simultaneously viewed. The particular statistics viewed may
be independently selected for each Statistic View. Statistic logging and alerts are
also provided; see Statistics Logging and Alerts on page 2-82
Stream Statistic Stream Statistic Views are like Statistic Views, but on a per stream basis rather
Views than per port basis.
MII Templates Allows for the creation and/or editing of MII template files. Register templates
are applied to physical ports through Port Properties dialogs.
Layouts Allows for the creation of templates for the layout of the IxExplorer GUI. A
layout consists of the combined open features in the GUI.
IxRouter Window The IxRouter window provides the means by which routing protocols are
emulated by the Ixia hardware and software. This window includes the interface
by which multiple IPv4 and IPv6 interfaces are associated with each port. A
growing number of protocols are supported in this window, including ARP,
BGP, OSPF, ISIS, RSVP-TE, LDP, RIP, RIPng, and IGMP.
Note that full use of this window requires that IxRouter be installed. For more
information on protocols and protocol testing, see IxRouter User Guide.

IxExplorer Software
IxExplorer IxExplorer saves all settings and programming in ‘saved’ named files, which
Operation may be retrieved on each invocation. Captured data is lost when the IxExplorer is
exited.
All IxExplorer test operations perform on an arbitrary set of ports, as single port
or multiple ports may be selected. Any level of the hierarchy may be selected to
include all ports below that level. For example, selecting a card includes all ports
on that card, or selecting a chassis chain includes all ports on all cards in all
chassis in the chassis chain. In addition, port groups may contain ports from any
card; the port group may then be used in any testing operations.
The operations that can be performed on any group of ports:

• Start/Stop Capture: When capture is enabled, data for each port that is
configured for capture (versus latency) is collected when the trigger is
satisfied and to the extent that the filter is satisfied as well.
• Start/Stop Transmit: When transmit is enabled, data is transmitted as
programmed to the extent designated by the synchronous stream region.
• Start/Stop Collision: Forced collisions are enabled/disabled for receive ports.
• Start/stop Latency: When latency measurement is enabled, data for each port
configured for latency (versus capture) is collected when the trigger is
satisfied and to the extent that the filter is satisfied as well.
• Pause/Single-Step Transmit: Transmittal of information may be paused and
then single-stepped on a stream-by-stream basis or continued through a start
transmit command.
• Interactive streams: This is a special function that allows for interactive
variation of frame size and inter-packet gaps. Interactive streams may not be
operated across ports that are configured for flows.
Multi-User Operation
IxExplorer provides an optional means of coordinating the sharing of chassis

ports among multiple users. If a single user is operating a chassis, multi-user
commands are not required at all. As an user, you may perform any operation on
any port. Two or more people may also share ports on a chassis without use of
IxExplorer multi-user facilities, through some verbal agreement (for example,
‘You take cards 1-8 and I’ll take cards 9-16’). IxExplorer provides no assistance
in this instance.
Where more accurate control over port sharing is required, multi-user facilities
should be used. IxExplorer’s multi-user model is a very simple, advisory model.
Each user logs in with an arbitrary name. Each and every user may take
ownership of any and all ports. A port owner has the ability to read data and
program the port; all other users have read-only access to the port. A port owner
may clear ownership of ports, making them available for other users. You may
take ownership of a port owned by someone else, with an optional warning
message. Any user may clear all ownerships.

IxExplorer provides a further distinction of roles between users. Administrators

are privileged users who may take ownership of ports, configure their
characteristics, and initiate tests using those ports. Operators are unprivileged
users who may only look at chassis, card, and port characteristics and measured
data.
Note: We NEVER support multiple clients simultaneously changing data on one

port. The rule is: one port-one owner for each system test.
The ownership model should not be used to have one script take ownership of a
port and another script take ownership of that same port with the same
username because one client may be working with a copy of the port
configuration that has been made invalid by another owner.
The two basic modes of multi-user operation are referred to as:

• Voluntary: All users are considered administrators and voluntarily login and
take or clear ownership of ports. All chassis are initially configured in this
mode.
• Secure: Users are characterized as Administrators or Operators. All users
must login. Administrators operate in the same manner as all Voluntary mode
users. Operators are restricted to viewing data.
Statistics Logging and Alerts
IxExplorer has the ability to centrally log statistics from any port and to signal
alert conditions when a particular statistic goes out of a specified, valid range.
Figure 2-58 on page 2-82 shows the basic operation of logging and alerts.
Figure 2-58. Statistics Logging and Alerts
The clients (Client 1 and Client 2) run IxExplorer and are connected to all of the
chassis (Chassis 1, Chassis 2 and Chassis 3) in the chassis chain. The clients set
up conditions under which statistics data is logged and alerts generated. These

IxExplorer Software
conditions are transmitted to all of the chassis. Each chassis interprets these
conditions and logs statistics data and alert conditions to their local disks.
When a chassis detects an alert condition, it sends signals to all of the clients
connected to the chassis at the moment. Each client receives alerts from all of the
chassis, regardless of whether they set up the particular alert condition
themselves.
It can take considerable effort to set up one port’s statistics logging and alert
conditions. It is not necessary to repeat this process for multiple ports that have
identical logging and alert behavior. IxExplorer’s Port Copy feature may be used
to copy these specifications.
It should be noted that logging and alerts continue even after a client has exited
IxExplorer.
Statistics Logging
Each client selects particular statistics on particular ports to be logged. The data
is logged at the chassis hosting the port. All clients connected to a chassis
contribute their desired port-statistics to be logged. All statistics from all clients
are logged to the same single file on a chassis.
The log file is ASCII in format and contains a line of text for each port on which
statistics have been gathered. Each line contains all of the selected statistics for
the port, separated by commas. The contents of the file are easiest to understand
and interpret if the same statistics are gathered for all ports.
The statistic values that are logged are the ‘rolling average’ for the value logged.
That is, a value at time slot n depends on the previous average and the current
measured value, as per the following equation:
Averagen = (Averagen-1 * (n-1)/n) + (Measurementn * 1/n)
The client specifies several parameters that affect the logging of statistics:
• Enable/Disable: Enable or disable all statistics logging specified from this
client.
• Log at interval: Specify an interval between logged entries.
• Log during alerts: Log statistics while alert conditions exist.
• File naming: The format and location of logging files on the chassis.
Multiple clients should agree on the log interval and file naming conventions; the
chassis uses the settings received from any client that applies changes.
Alerts
Each client sets up anticipated valid ranges for particular statistics on specific
ports. All clients connected to a chassis distribute their specific valid ranges to all
chassis. Each chassis watches for out of range values on the specified port-
statistics and generates alerts for the conditions. All alert conditions are sent to

all connected clients. Alert condition changes may be optionally logged on files
at the chassis.
The client indicates how it wants to receive alerts for a particular statistic and
port. There are three options:
• Visual: each statistic subject to alerting is displayed as green (in range), red
(out of range) or yellow (was previously out of range) in any Statistic View
containing the port-statistic.
• Audible: while any out of range condition exists, the client’s computer issues
a repeating beep-beep. A client may mute all audible alarms at once.
• Both visual and audible.
In addition, the existence of an alert condition for a particular port-statistic may

be used to initiate statistics logging for that port, as described in Statistics
Logging on page 2-83.
The client specifies several parameters that affect the setup of alert conditions:
• Enable/Disable alerts: Enable or disable all visual and/or audible alerts
specified from this client.
• Enable/Disable Alert Logging: Enable or disable the logging of alert change
conditions on the chassis.
• File Naming: The format and location of alert files on the chassis.
Multiple clients should agree on the valid range of port-statistics values and file
naming conventions; the chassis uses the settings received from any client that
applies changes.

Tcl Software Structure

The Tcl software is structured as a number of client-server pieces so that it may
operate simultaneously in three different environments:
• On the Ixia chassis: The Tcl scripts are executed on the same computer that
runs the Ixia hardware.
• On a Windows client: The Tcl scripts are executed on a Windows 2000/XP
client.
• On a Unix client: The Tcl scripts are executed on a Unix client.
The following sections describe the components used in each of these scenarios.
Operation on the When the Tcl client software is installed on the Ixia chassis itself three distinct
Ixia Chassis software components are used, as shown in Figure 2-59 on page 2-85.
Figure 2-59. Software Modules Used on an Ixia Chassis

2 Tcl Software Structure
In this scenario, three components are used as described in Table 2-21.

Table 2-21. Software Modules Used on an Ixia Chassis
Module Usage
Tcl scripts Ixia supplied and user developed Tcl. The Tcl extensions that
program the Ixia hardware use the TclHAL layer.
TclHAL A layer of software, supplied as a DLL (Dynamic Linked

Library), that is responsible for interpreting the Tcl commands
into C++ functions to be sent to the IxServer software.
IxServer An independent Windows executable that is responsible for

directly controlling the Ixia hardware.
Operation on a When the Tcl client software runs on a Windows client, the same three
Windows Client components are used but in a different configuration, as shown in Figure 2-60 on
page 2-86.
Figure 2-60. Software Modules Used on a Windows Client
In this scenario, three components are used as described in Table 2-22.

Table 2-22. Software Modules Used on a Windows Client
Module Usage
Tcl scripts Ixia supplied and user developed tests run on the Windows client
using the Tcl software. The Tcl extensions that program the Ixia
hardware use the TclHAL layer.
TclHAL A layer of software, supplied as a DLL (Dynamic Linked Library),

that is responsible for interpreting the Tcl commands into C++
functions to be sent to the IxServer over the local network.
IxServer An independent Windows executable running on the Ixia Chassis

that is responsible for directly controlling the Ixia hardware. Its
commands are received from clients over the LAN.

Operation on a Unix When the Tcl client software runs on a Unix client, five components are used as
Client shown in Figure 2-61 on page 2-87.
Figure 2-61. Software Modules Used on a Unix Client
In this scenario, five components are used as described in Figure 2-23 on page 2-
87.
Table 2-23. Software Modules Used on a Unix Client
Module Usage
Tcl scripts Ixia supplied and user developed tests run on the
Windows client using the Tcl software. The Tcl extensions
that program the Ixia hardware use the Tcl-DP client
software.
Network Interface This is a layer of software within the TCL system that
translates hardware commands into ascii commands,
which are sent to the TCL Server on the connected Ixia
chassis.
TclServer This layer receives commands from the Tcl-DP client on

Unix client platforms. Commands are translated into calls
to the TclHAL layer.
TclHAL A layer of software, supplied as a DLL (Dynamic Linked

Library), that is responsible for interpreting the Tcl
commands into C++ functions to be sent to IxServer on
the chassis over the network.
IxServer An independent Windows executable running on the Ixia

Chassis that is responsible for directly controlling the Ixia
hardware. Its commands are received from clients over the
LAN.
Multiple Client A single Ixia chassis may be used by multiple clients simultaneously. Clients
Environment may run from the Ixia chassis, Windows clients, and Unix clients simultaneously,
as shown in Figure 2-62 on page 2-88.

2 Tcl Software Structure
Figure 2-62. Multi-Client Environment
TCL Version Note the following limitation with respect to Tcl versions and the use of Wish
Limitations and Tclsh shells:
1. Tcl 8.0 is no longer supported.
2. Tclsh does not run on any version of Windows, with Ixia software. Under
Linux or Solaris, Tclsh runs on any version of Tcl greater than or equal to 8.2.
The use of the Wish shell with Ixia software has been tested for Tcl 8.3 under
Windows, Linux, and Solaris. It has not been tested, but should run with any Tcl
version greater than or equal to 8.2.
Beginning with the Ixia TCL libraries supplied with IxOS version 3.80, these
libraries are compatible with TCL version 8.3 and above. That is, it is not
necessary to obtain a new version of the Ixia libraries when TCL 8.4 (or above) is
installed on a computer.

Chapter 3: Theory of Operation:
3 Protocols
Protocol Server
Most ports in an Ixia chassis operate a Protocol Server. The Protocol Server
includes a complete TCP/IP stack, allowing different forms of high-level DUT
testing. The Protocol Server can be configured to test a set of provided Level 2
and Level 3 protocols, which include MAC and IP addressing and IP routing.
The Protocol Server for Packet over SONET cards omits all MAC configuration
items, since POS does not use a MAC layer. The information gathered by the
Protocol Server is used within generated frame data, as well.
The Protocol Server can be accessed through the IxRouter Window. Each
protocol must be individually enabled for a selected port in the IxRouter
Window.
The protocols supported by the Ixia Protocol Server are described in the
following sections in this chapter:
Table 3-1. Protocols Supported by Ixia Protocol Server
Address Resolution Protocol (non-POS only) See ARP on page 3-2

(includes IP to MAC addressing)
Internet Gateway Management Protocol See IGMP on page 3-3
Open Shortest Path First Protocol See OSPF on page 3-4
Open Shortest Path First Protocol Version 3 (for See OSPFv3 on page
IPv6) 3-7
Border Gateway Protocol See BGP4/BGP+ on

page 3-8
Routing Information Protocol See RIP on page 3-14
Routing Information Protocol: Next Generation See RIPng on page 3-

(for IPV6) 16
Intermediate System to Intermediate System (Dual See ISISv4/v6 on page

Mode) 3-17

Theory of Operation: Protocols
3 ARP
Table 3-1. Protocols Supported by Ixia Protocol Server
Resource ReSerVation Protocol: with Traffic See RSVP-TE on page

Engineering Extensions 3-20
Label Distribution Protocol See LDP on page 3-27
Multicast Listener Discovery See MLD on page 3-28
Protocol Independent Multicast: Sparse Mode See PIM-SM/SSM-v4/

v6 on page 3-29
Multi-Protocol Label Switching See MPLS on page 3-

34
Bi-Directional Forwarding See BFD on page 3-36
Connectivity Fault Management See CFM on page 3-37
Fibre Channel over Ethernet (FCoE), FCoE See FCoE and NPIV on
Initialization Protocol (FIP) and NPIV page 3-39
Precision Time Protocol (PTP) See Precision Time

Protocol (PTP) IEEE
1588v2 on page 3-41
There are additional sections on the following topics:

• ATM Interfaces on page 3-46
• Generic Routing Encapsulation (GRE) on page 3-53
• DHCP Protocol on page 3-57
• Ethernet OAM on page 3-59
ARP
The Address Resolution Protocol (ARP) facility controls the manner in which
ARP requests are sent. This option is only available on Ethernet load modules.
The resulting responses from ARP requests are held in the ARP Table, which is
used to set MAC addresses for transmitted data. ARP’ing the Device Under Test
(DUT) allows tests and generated frames to be configured with a specific IP
address, which at run time is associated with the MAC address of that particular
DUT.
IP
The IP table within the ARP window specifies a per-port correspondence
between IP addresses, MAC addresses (for Ethernet ports only), and the Default

IGMP
Gateway. IP addresses may be expressed as individual addresses or as a range of

addresses.
All ARP requests (for Ethernet) are sent to the Default Gateway address. In most
cases, the Default Gateway Address is the address of the DUT. When a gateway
separates the Ixia port from the DUT, use the IP address of that gateway as the
Default.
IGMP
The Internet Group Management Protocol (IGMP) is used with IPv4 to control
the handling of group membership in the Internet. Version 3, specified in RFC
3376, is supported and is interoperable with Versions 1 and 2. Version 1 of the
protocol is specified in RFC 1112, and Version 2 is specified in RFC 2236.
IGMP normally works in an environment in which there are a number of IGMP-

capable hosts connected to one or more IGMP routers. The routers forward
membership information and packets to other IGMP routers and receive group
membership information and packets from other IGMP routers.
The Ixia hardware simulates one or more hosts, while the DUTs are assumed to
be IGMP routers. The simulation calls for groups of simulated hosts to respond to
IGMP router-generated queries and to automatically generate reports at regular
intervals. A number of IGMP groups are randomly shared across a group of
hosts.
Version 3 adds the concept of filtering, based on the IP source address, to cut
down on the reception of unwanted multicast traffic. This filtering consists of
limiting the receipt of packets to only those from specific sources (INCLUDE) or
to those from all but specific sources (EXCLUDE). Refer to MLD on page 3-28
for information about similar functions for multicast traffic in IPv6
environments.
Compatibility with earlier versions of IGMP is an important part of IGMPv3.

The Group Compatibility Modes for an IGMPv3 router are summarized as
follows:
• IGMPv3 Compatibility Mode (default): An IGMPv2 and/or IGMPv1 Host
is present, but NOT running.
• IGMPv2 Compatibility Mode: An IGMPv2 Host may be present and
running. An IGMPv1 Host is present, but NOT running.
• IGMPv1 Compatibility Mode: An IGMPv1 Host is present and running.

3 OSPF
OSPF
Note: See also OSPFv3 on page 3-7.
Open Shortest Path First (OSPF) is a set of messaging protocols that are used by
routers located within a single Autonomous System (AS). The Ixia hardware
simulates one or more OSPF routers for the purpose of testing one or more DUT
routers configured for OSPF. The OSPF version 2 specification (RFC 2328)
details the message exchanges by OSPF routers, as well as the meanings and
usage.
OSPF has the following three principal stages:

• The HELLO Protocol
• Database transfer
• HELLO Keepalive
When an OSPF router initializes, it sends out HELLO packets and learns of its
neighboring routers by receiving their HELLO packets. If the router is on a
Point-to-Point link, or on an Ethernet (transit network) link, these packets are
addressed to the AllSPFRouters multicast address (224.0.0.5). In these types of
networks, there is no need to manually configure any neighbor information for
the routers.
Each router that is traversed on the path between neighbors is added to a list
contained in the HELLO packet. In this way, each router discovers the shared set
of neighbors and creates individual state machines corresponding to each of its
neighbors.
If the network type is broadcast, then the process for selecting a Designated
Router (DR) and Backup Designated Router (BDR) begins. A Designated Router
is used to reduce the number of adjacencies required in a broadcast network. That
is, if no Designated Router is used, then each router must pair (form an
adjacency) with each of the other routers. In this case, the number of required
adjacencies is equal to the square of the number of routers (N^2). If a DR and
BDR are used, the number of required adjacencies drops to 2 times the number of
routers (2N). Currently, the Ixia ports are unable to simulate a DR or BDR.
Once the routers have initialized their adjacency databases, they synchronize
their databases. This process involves one router becoming the master and the
other becoming the subordinate. On Ethernet networks, the DR is always the
master; on point-to-point networks, the router with the highest Router ID is the
master.
Link State Advertisements (LSAs) are OSPF messages that describe an OSPF
router’s local environment. The simplest LSA Type is the router-LSA
(RouterLinks LSA). Each router is required to generate exactly one of these
LSAs to describe its own attached interfaces. If a network that consists of a single
OSPF area is being simulated with only point-to-point links and there are no

OSPF
Autonomous System Border Routers (ASBR), then this is the only type of LSA
that is sent.
The subordinate asks the master for its LSA (Link State Advertisement) headers,
which enables the subordinate to determine the following information:
1. The subset of LSAs that the master holds, but that the subordinate does not
have, and
2. The subset of LSAs that the master and subordinate both have, but which are
more recent on the master.
The subordinate router then proceeds to explicitly query the master to send it
each LSA from Steps (1) and (2). The subordinate sends an ACK to the master
upon receipt of each LSA. The global Link State Database (LSDB) is constructed
by each router, based on LSAs from all the other routers in the network.
Once this exchange process is complete, the routers are considered to have
reached Full Adjacency, and each runs the link state algorithm to update its IP
forwarding tables. The routers continue to exchange periodic HELLO packets, as
keepalive messages, until a change occurs (for example, a link goes down or an
LSA expires). OSPF routers continue to periodically exchange their LSAs every
30 minutes to ensure that they all hold identical LSDBs.
This section describes the programming of the Ixia hardware related to OSPF
testing, as well as the theory of operation and protocol message formats. The Ixia
hardware simulates multiple OSPF routers on multiple networks. For example, in
Figure 3-1 on page 3-5 there are three networks and three routers.
Figure 3-1. Sample OSPF Network
The Protocol Server calls for the specification of router-network connections to

be specified in a network-centric fashion. One specifies the network in terms of
an Area ID and network mask. One specifies the routers in terms of the interface
IP address on that network and Router ID, usually the lowest IP address for the
router. For the sample OSPF network, in which Router 3 is the DUT, the three

3 OSPF
networks are specified by their significant characteristics as shown in Table 3-2

on page 3-6.
Table 3-2. Sample OSPF Network Assignments
Network Area ID Network Mask Router ID Router

Interface
IP Address
1 192.168.36.0 255.255.255.0 192.168.36.10 10.0.0.40
2 172.16.0.0 255.255.255.0 172.16.0.20 10.0.0.41
3 10.0.0.0 255.255.0.0 10.0.0.40 10.0.0.40

10.0.0.41 10.0.0.41
10.0.0.90 10.0.0.90
Within this framework, Link State Advertisements (LSAs) may be issued from
the perspective of any interface on any router. Any OSPF messages from the
DUT Routers may be captured and analyzed in the normal manner.

OSPFv3
OSPFv3
Open Shortest Path First Protocol Version 3 supports Internet Protocol version 6
(IPv6), as defined in RFC 2740. The 128-bit IPv6 addressing scheme has been
accommodated in OSPF through the use of new LSA types.
Some of the differences between OSPFv2 (for IPv4) and OSPFv3 (for IPv6) are
listed as follows:
• Changes to adapt to the IPv6 128-bit address size. No addresses are carried in
OSPF packets or basic LSAs, but addresses are carried in certain LSAs.
• OSPFv3 operation is per Link, with the IPv6 concept of ‘link’ replacing the
‘IP subnet’ and ‘network’ terminology of OSPFv2.
• OSPVv3 supports multiple instances of the protocol per link, through
‘Instance IDs.’
• LSA flooding scope is explicitly defined in the LS Type field of each LSA.
• Authentication is handled by the IPv6 protocol itself, rather than by the OSPF
protocol. For this reason, Authentication information has been removed from
the packet headers in OSPFv3.
Note: In OSPFv2, IPv4 addresses were used in many contexts besides IP

source and destination addresses. For example, they were assigned as name
identifiers for routers (RIDs). This naming convention for RIDs has been
retained in OSPFv3.

3 BGP4/BGP+
BGP4/BGP+
Border Gateway Protocol Version 4 (BGP-4) is the principal protocol used in the
Internet backbone and in networks for large organizations. The BGP4
specification (RFC 1771) details the messages exchanged by BGP routers, as
well as their meaning and usage. BGP4 - Inter-Domain Routing in the Internet,
by John W. Stewart III is a descriptive reference on this protocol.
Internal Versus The BGP4 protocol is used according to two sets of rules, depending on whether
External BGP or not the two communicating BGP routers are within the same Autonomous
System (AS). An AS is a collection of routers that implement the same routing
policy and are typically administered by a single group of administrators. ASs
connected to the Internet are assigned Autonomous System Numbers (ASNs) that
are key to inter-domain routing. When BGP is used between two ASs, the
protocol is referred to as EBGP (External BGP); when BGP is used within an AS
it is referred to as IBGP (Internal BGP). Figure 3-2 on page 3-8 depicts the
differences in topology between EBGP versus IBGP.
Figure 3-2. External BGP Versus Internal BGP
In the figure above, AS1, AS2, and AS3 are distinct Autonomous Systems. The
Rns are routers in the various ASs. Routers on the links between ASs ‘speak’
EBGP, while the routers within AS3 ‘speak’ IBGP.
IBGP Extensions
In the original BGP4 specification (RFC 1771), all IBGP routers within an AS
are required to establish a full mesh with each other. This leads to a lack of
scalability which is solved by the introduction of two additional concepts: route
Reflection and Confederations.
In route reflection, some routers in an AS are assigned the task of re-distributing

internal routes to other internal AS routers. To prevent looping within an AS that
uses route reflection, two concepts are important: the originator-id and cluster-
list attributes.The originator-id is the identification of the router that originated a
particular route. Routers within an AS propagate this information and refuse to
send a route back to its originator. Even the use of route reflectors and originator-

BGP4/BGP+
ids can lead to scalability problems in an AS. The cluster-list concept helps this
problem. A cluster consists of a reflecting router and its clients. A Cluster ID is
the IP address of the reflecting router if there is one, or a configured number
otherwise. A cluster-list is a constructed list, consisting of the cluster IDs of all of
the clusters that a route has passed through. Each router refuses to send a route
back to a cluster that has seen the route already.
In a confederation, an AS is divided into multiple sub-confederation subsets.

Each sub-confederation is defined in terms of its own ASN and a list of routers.
Routers within a sub-confederation are expected to fully mesh using IGP. Sub-
confederations within a confederation speak a variant of EGP, called EIGP.
Additional path attributes are used with a confederation to indicate paths that
should not be propagated outside the confederation.
Communities In deployment of BGP4 into a growing Internet environment, it became

necessary to deal with certain routes in different manners not related to the strict
routing of packets. The community attribute was invented to allow a route to be
‘tagged’ with multiple numbers, called communities. This is also referred to
sometimes as route coloring.
BGP Router Test The Ixia Protocol server implements an environment in which the Ixia hardware
Configuration simulates multiple routers which speak IBGP and/or EBGP with one or more
DUT routers. For example, in Figure 3-2 on page 3-8, the Ixia hardware emulates
R1, R3, and R5 while the DUTs are R2 and R4. The following figure depicts the
same setup based on the location of the simulated or actual router:
Figure 3-3. BGP Interconnection Environment

3 BGP4/BGP+
All of the routers are logically connected through appropriate networking

hardware. The Ixia hardware is used to simulate three of the routers in two
different ASs communicating with two routers being tested.
A single router emulated by the Ixia hardware is specified by a single IP address,

and a number of emulated routers may be specified by a range of IP addresses.
Each DUT router is identified by its IP address.
Messages may be sent between the emulated routers and the DUT routers when a
connection is made and one of the two endpoints sends an OPEN message.
Where the emulated routers and the DUT routers send their OPEN messages
simultaneously, standard collision handling is applied. Thereafter, the emulated
routers send a number of UPDATE messages to the DUT routers. The UPDATE
messages contain a number of network address ranges (route ranges), also known
as ranges of prefixes. The ranges of generated network addresses is illustrated in
Figure 3-4. Generation of Network Addresses in BGP UPDATE Messages
A designated number of network addresses are generated with network Mask

Width with the From through To values. Table 3-3 on page 3-11 shows some
examples of generated addresses. Network Addresses are generated by starting
with the First Route and From mask width up to, but not including 224.0.0.0.
(127.*.*.* is also skipped). If the requested number of network addresses has not
been generated before 224.0.0.0 is reached, then the next mask length is used
with the First Route to generate network addresses.

BGP4/BGP+
Table 3-3. Examples of Generated BGP Routes (Network Addresses)
First Route Mask Mask Iterator Number of Generated BGP

Width Width Step Routes Routes
From To (Network
Addresses)
192.168.36.0 24 26 1 (14,378,756 192.168.36.0/24

Max.) 192.168.37.0/24
192.168.38.0/24
...
223.255.255.0/24
(224.0.0.0+ skipped)
192.168.36.0/25
192.168.36.128/25
192.168.37.0/25
...
223.255.255.128/25
(224.0.0.0+ skipped)
192.168.36.0/26
192.168.36.64/26
192.168.36.128/26
...
223.255.255.192/26
204.197.56.0 24 24 10 4 204.197.56.0/24
204.197.66.0/24
204.197.76.0/24
204.197.86.0/24
All of the generated network addresses are associated with a set of attributes that
describes routing to these generated network addresses and associated features.
Only one route can be added per UPDATE message, but a variable number of
withdrawn routes may be packed into each UPDATE message. The packing is
randomly chosen across a range of a number of routes. The time interval between
UPDATE messages is configurable, in units of milliseconds.
A BGP4 network condition called ‘flapping’ can be emulated by the protocol

server on an Ixia port. In the Link flapping emulation, a peer BGP router appears
to be going offline and online repeatedly, which is accomplished on the Ixia port
by alternate disconnects and reconnects of the TCP/IP stack. In the Route
flapping emulation, BGP routes are repeatedly withdrawn, and then re-
advertised, in UPDATE messages.

3 BGP4/BGP+
BGP L3 VPNs L3 Virtual Private Networks (VPNs) over an IP backbone (at Layer 3 of the OSI
model), may be provided to the customers of a Service Provider (SP), providing
connectivity between two or more sites owned by the customer. L3 VPNs are
independent of the Layer 2 protocol. While MPLS handles the packet forwarding
in the backbone/core, the BGP protocol provides a means of advertising external
routes/network addresses across that backbone between sites. IETF Internet Draft
‘draft-ietf-ppvpn-rfc2547bis-01.txt,’ the proposed successor to RFC 2547, covers
the VPN architecture designed for use by private service providers. A simplified
example of a BGP L3 VPN topology is shown in Figure 3-5 on page 3-12.
Figure 3-5. Simplified BGP L3 VPN Diagram
The term site refers to a customer/client site, which consists of a group of inter-
connected IP devices, usually in one geographic location. A Customer Edge (CE)
device, typically a router, connects the site, through a data link connection, to a
Provider Edge (PE) router—an entry point to the service provider’s backbone.
The PE-to-CE routing protocols may be static routing, or a dynamic protocol
such as eBGP or RIPv2.
Provider (P) network core routers, ‘transparently’ carry the IP traffic across the
internal core between CE routers. CEs and Ps are not ‘VPN-aware’ devices. CE
devices are considered as belonging to a only one site, but that site may belong to
multiple VPNs. A VPN Routing and Forwarding table (VRF) on a PE consists of
an IP routing table, a forwarding table, and other information on the set of
interfaces in the VPN. The VRF generally describes a VPN site’s routing
information, and a PE may maintain multiple VRFs, one for each connected
customer site. See L3 VPN VRFs on page 3-14 for additional information on
VRFs.
Layer 3 VPN sites are identified by a Route Target (RT). A route target is based
on the mechanism proposed in the IETF draft for the ‘BGP Extended

BGP4/BGP+
Communities Attribute.’ An 8-byte route target is common to all route ranges

that belong to a single L3 site. Route targets are defined for individual VPN route
ranges. The formats for Route Targets (RTs) are shown in Figure 3-6 on page 3-
13.
Figure 3-6. Route Target Formats (BGP Extended Community Types)
BGP VPN-IPv4 Address Formats
Globally unique 12-byte VPN-IPv4 prefixes are created by a PE router. This

includes configuration of the 8-byte VPN Route Distinguishers (RDs). It should
be noted that BGP IPv4 routes and VPN -IPv4 routes are considered
noncomparable; VPN-IPV4 addresses can be used only within the VPN service
provider network.The route distinguishers are used by PE routers to associate
routes with the path to a particular CE site router in a VPN. Each route can only
have one RD. The formats of the RDs are shown in Figure 3-7 on page 3-13.
Figure 3-7. VPN-IPv4 Address Formats (with Route Distinguishers)

3 RIP
L3 VPN VRFs
For Layer 3 Virtual Private Network (L3 VPN) configurations, the Provider Edge
(PE) routers maintain routing tables for each VPN that they participate in, termed
VPN Routing and Forwarding tables (VRFs). The VRFs are populated with
routes received from both the directly attached and remote Customer Edge (CE)
routers. Each entry in the VRF is called a VPN Forwarding Instance (VPI). VRFs
and CEs are not required to be configured on a one-to-one basis, although this is
the typical situation. An example of the possible relationships between VRFs and
CEs is shown in Figure 3-8 on page 3-14.
Figure 3-8. L3 VPN VRF Example
RIP
The Routing Information Protocol (RIP) is an interior routing protocol. It is the
oldest and most frequently used of the LAN routing protocol. RIP routers
broadcast or multicast to each other on a regular basis and in response to
REQUEST packets. RIP routers incorporate routing information received from
their neighbors into their own routing table and forward them on to other
neighbors. Two distinct versions of RIP exist: version 1 and version 2. Both IPv4
and IPv6 are supported.
As implemented by the Protocol Server, each Ixia port is capable of simulating

one or more routers at distinct addresses. Routing tables for the simulated routers
are configured by you and sent out at regular intervals, with a configurable
randomizing factor. Either version 1 or version 2 packet formats may be sent
through multicast or broadcast (for compatibility with version 1 routers).
Received packets may be filtered for version 1 and/or 2 compatibility.

RIP
The current implementation of the Protocol Server uses Split Horizon with Space
Saver as its update mode, which receives, but not process RIP broadcasts heard
from DUT routers. That is, it does not incorporate received information into its
own table, but rather always broadcast the same routing table. Future versions
will offer Split Horizon, Split Horizon with Poison Reverse, and Silent modes of
update.
The Protocol Server, however, responds to REQUEST packets that it receives.

Two types of requests are processed:
• Request for all routes: The Protocol Server sends the same routing table that it
sends at regular intervals back to the requestor.
• Request for specific routes: The Protocol Server fills in the requested
information in the received packet and send it back to the requestor.
RIP Overview The Routing Information Protocol (RIP) is an interior gateway routing protocol
(IGP) and uses a Distance Vector Algorithm. It is the oldest and most frequently
used of the LAN routing protocols. RIP routers broadcast or multicast to each
other on a regular basis and in response to REQUEST packets. RIP routers
optionally incorporate routing information received from their neighbors into
their own routing table and forward it on to other neighbors.
Note: For information on RIPng (RIP-Next Generation), based on IPv6, see

RIPng on page 3-16.
As implemented by the Protocol Server, each Ixia port is capable of simulating

one or more routers with separate addresses. Routing tables for the simulated
routers are configured by you and sent out at regular intervals, with a
configurable randomizing factor. Either Version 1 or Version 2 packet formats
may be sent through multicast or broadcast (for compatibility with Version 1
routers). Received packets may be filtered for Version 1 or Version 2
compatibility.
The current implementation of the Protocol Server uses Split Horizon with Space
Saver as its update mode, which receives, but not process, RIP broadcasts heard
from DUT routers. That is, it does not incorporate received information into its
own table, but rather always broadcast the same routing table. Future versions
will offer Split Horizon, Split Horizon with Poison Reverse, and Silent modes of
update.
The Protocol Server, however, responds to REQUEST packets that it receives.

Two types of requests are processed:
• Request for all routes: The Protocol Server sends the same routing table that it
sends at regular intervals back to the requestor.
• Request for specific routes: The Protocol Server fills in the requested
information in the received packet and send it back to the requestor.

3 RIPng
RIPng
Routing Information Protocol - Next Generation (RIPng) is specified for use with
IPv6 in RFC 2080. Like the IPv4 version of RIP, this routing protocol is based on
a Distance Vector algorithm. RIPng routers compare information for various
routes through an IPv6 network, especially the information related to the RIPng
metric. Due to the limited number of allowed hops, this protocol is used in small-
to moderate-sized networks. The valid metric range is from 1 to 15 (hops). The
metric values of 16 and above are defined as ‘infinity’ and are considered
unreachable.
An RIPng router is assumed to have interfaces to one or more directly-connected

networks. Each router maintains a routing table, with one entry for every
reachable destination in the RIPng network. Each routing table entry contains a
minimum of:
• IPv6 destination prefix(es)
• total metric cost for the path to the destination(s)
• IPv6 address of the next hop router
• a ‘route change flag’
• timers
As a UDP-based protocol, the RIPng routing process functions on UDP well-

known port number 521 (the ‘RIPng port’), on which datagrams are sent and
received. The RIPng port supports the following:
• Receives all communications received from another router’s RIPng
process.
• Sends all RIPng routing update messages.
• Unsolicited routing update messages specify this port as the source and
destination.
• Responses to request messages are sent to the originating UDP port.
• Specific requests need not come from the RIPng port, but the destination
on the targeted device must be the RIPng port.

ISISv4/v6
ISISv4/v6
The Intermediate System to Intermediate System (ISIS) routing protocol was
originally designed for use with the OSI Connectionless Network Protocol
(CLNP) and was defined in ISO DP 10589. It was later extended to include IP
routing in IETF RFC 1195. When routing for OSI and IP packets (defined in
ISO/IEC 10589:1992(E)) is combined in this way, the protocol is referred to as
Integrated ISIS or Dual ISIS. In addition, RFC 2966 extends the distribution of
routing prefixes among ISIS routers, and IETF DRAFT draft-ietf-isis-ipv6-05
adds IPv6 routing capability to the protocol.
ISIS Topology ISIS areas are administrative domains which contain ISIS routers, have one or
more private networks, and may share networks with other areas. The example
shown in Figure 3-9 on page 3-17 consists of a theoretical ISIS topology. Note
that, as shown in this diagram, all ISIS routers are considered to reside entirely
within an area, unlike some other protocols such as OSPF, where routers can
reside at the edges of areas and domains.
Figure 3-9. ISIS Topology
One or more Area IDs are associated with an area. Most areas only require one
ID during steady state operation, but up to three IDs may be needed during the
process of migrating a router from one area to another. In most cases, the
maximum number of area IDs is set to three.
ISIS routers can be divided into three categories, as follows:

• Level 1 (L1): These routers can connect only to L1 or L1/L2 routers within
their own area (intra-area). They have no direct connection to any other ISIS
area.
• Level 2 (L2): These routers can connect only to other L2 routers outside their
area, or to L1/L2 routers within their own area. They are used as backbone
routers in the routing domain, to connect ISIS areas.

3 ISISv4/v6
• Level 1/2 (L1/L2): These routers have separate interfaces which can connect
to both L1 routers within their own area and L2 routers in other areas.
Entirely separate routing tables are maintained for Level 1 and Level 2 ISIS
information, even within L1/L2 routers. All L1s within an area maintain identical
databases. All L2s within a domain maintain identical databases.
ISIS Processing Many OSI concepts are necessary for describing ISIS. The following terms are
important to the following discussion:
• IS - Intermediate System. An ISIS router is an IS.
• ES - End System. A host is an ES. (Note: The Ixia hardware does not
currently simulate End Systems.)
• PDU - Protocol Data Unit. PDUs contain messages used for the ISIS
protocol. The following PDUs are used in IS-IS communications:
• IIH - IS-to-IS Hello PDU. This message is multicast over broadcast
networks, or unicast on point-to-point links, between ISs to discover
neighbors and maintain ISIS state.
• LSP - Link State PDU. This message holds the significant part of the
routing table sent between ISIS routers.
• SNP - Sequence Number PDU. This message is used to request LSPs and
acknowledge receipt of LSPs. Two types are used depending on the
network type:
• CSNP - Complete SNP. In broadcast networks, these are sent by the
Designated Router in an area. On point-to-point connections,
CSNPs are used for initialization. A CSNP contains a complete
description of the LSPs in the sender’s database.
• PSNP - Partial SNP. On broadcast networks, PSNPs are used to
request LSPs. On point-to-point connections, PSNPs are used to
acknowledge receipt of LSPs. On both types of networks, PSNPs
are used to advertise newly learned LSPs or purge LSPs. A PSNP
contains a subset of the received records.
ISIS routers maintain knowledge of each other by exchanging Hello PDUs at

regular, configured Hello intervals. A router is considered down if it does not
respond within a separately configured Dead interval.
ISIS routers update each other using Link State PDUs (LSPs) at a regular interval
of 30 minutes. The LSP header contains the Remaining Lifetime for the LSP, a
Sequence Number, and a checksum. Each LSP contains information about a
router’s connection to local networks, plus a metric related to each network. ISO
DP 10589 defines four types of metrics: default, delay, expense, and error.
In a Broadcast/LAN network, the Designated Router sends a Complete Sequence

Number PDU (CSNP). In a Point-to-Point network, the receiving router sends a
Partial Sequence Number PDU (PSNP).
In the ISIS protocol, for each of the levels (L1 or L2), one of the routers is elected
as the Designated IS, based on priority values assigned to each interface as part

ISISv4/v6
of Hello PDU processing. The Ixia Protocol Server does not support the role of
DR, so to ensure that it is not elected by its ISIS peers each Ixia-simulated ISIS
router has a default priority of ‘0,’ indicating its unwillingness to be the
Designated IS.
ISIS Addresses Due to the OSI derivation of the ISIS protocol, each ISIS router has an OSI NET
address of 8 to 20 octets in length. The NET address consists of two parts: an
Area ID and a System ID. The Area ID has a number of different formats defined
in OSI specifications. The System ID may be from 1 to 8 octets in length. The
default System ID length defaults to 6 octets and must be the same length for
every router in the domain. The System ID is unique within its ISIS area for
Level 1, or unique within the ISIS routing domain for Level 2 or Level 1/2. Two
types of network connections are supported: broadcast and point-to-point. In a
broadcast network, each interface on an ISIS dual-mode router must have an IP
address and mask.

3 RSVP-TE
RSVP-TE
The Ixia protocol server implements a part of the Resource Reservation Protocol
(RSVP) used for Traffic Engineering (TE). This subset of the RSVP protocol,
referred to as RSVP-TE, is used in the process of constructing a path through a
sequence of MPLS-enabled label switched routers (LSRs), while reserving
necessary bandwidth resources. The use of an internal gateway routing protocol
(IGP), such as OSPF, is also required to automatically determine the ‘next hop’
router.
Multi-Protocol Label Switching (MPLS) allows rapid forwarding of packets

across a sequence of routers, without time-consuming examination of the packet
contents at each hop. Label switching has been used extensively for ATM traffic,
where overhead bytes for each ‘cell,’ or packet, of data constitute a large
percentage of the overall data transmitted. The addition of a ‘label’ value to the
header information in each cell or packet supplies the only forwarding
information required to transit the MPLS domain. Based on information in its
forwarding table, each LSR replaces (swaps) the incoming label with a new one
which directs the packet to the next hop.
The most important output from an RSVP-TE setup session is the set of MPLS
labels, which are used by the MPLS-enabled routers along the path to efficiently
forward network traffic. The operation of RSVP-TE is shown in Figure 3-10 on
page 3-20.
Figure 3-10. RSVP-TE Overview
Through the use of RSVP-TE message exchanges, the router at the entry to the
MPLS domain, also known as an Ingress LSR, initiates the creation of a dynamic
‘tunneled’ pathway to the Egress LSR, the router at the exit side of the MPLS
domain. Packets which pass through this ‘tunnel’ are essentially ‘protected’ from
the extensive packet processing normally imposed by each router it traverses.
Once this special pathway or Label Switched Path (LSP) is established, the router
can forward, rather than route, packets across the domain, saving considerable

RSVP-TE
processing time at each intermediate LSR (Transit LSR). The resulting tunneled
pathway is known as an LSP Tunnel. The traffic flows through an LSP Tunnel
are unidirectional. To establish bidirectional traffic through the MPLS domain, a
second LSP Tunnel must be created in the opposite direction.
An LSP Tunnel is defined by a Destination Address (the IP address of the Egress

LSR), and a Tunnel ID. At a finer level of granularity are LSP IDs. Essentially,
these LSP IDs can serve to provide a set of aliases for alternate hop-by-hop paths
between a single pair of Ingress and Egress LSRs, and therefore exist within the
same LSP Tunnel.
Note: Ingress LSRs and Egress LSRs are also known as Label Edge Routers
(LERs).
Two principal RSVP-TE message types are used to establish LSP Tunnels:
• PATH message. A PATH message is generated by the ingress router and sent
toward the egress router. This is termed the downstream direction. This
PATH message is a request by the sending LSR for the establishment of an
LSP to the egress router. Each LSR in the path to the destination router
digests the PATH message and does one of three things:
• If the LSR cannot accommodate the request, it rejects the request by
sending a PATH_ERR message back to the source indicating the nature of
the rejection.
• If the LSR is not the egress router, it sends a PATH message to the next
LSR toward the destination router.
• If the LSR is the egress router, it should respond with a RESV message
back to its most recent neighbor.
• RESV message. A RESV message is generated by the egress router and sent
over the reverse path that the PATH messages took. This is termed the
upstream direction.
An additional HELLO message is used between neighbor LSRs to ensure that

LSRs are alive. This allows for quick tunnel replacement in the case of link or
router failure.
A set of labels is passed in the RESV messages sent upstream from the egress to
the ingress router. A label is sent from one LSR to its upstream neighbor telling
the upstream router which label to use when later sending downstream traffic.
Three scenarios are currently supported to test MPLS/RSVP-TE on a DUT using

Ixia equipment:
1. The DUT acts as the Ingress LSR, and the Egress LSR is simulated by an Ixia
port.
2. The DUT acts as the Egress LSR, and the Ingress LSR is simulated by an Ixia
port.
3. The DUT acts as a Transit/Intermediate LSR, and the Ingress and Egress
LSRs are simulated by Ixia ports.

3 RSVP-TE
PATH Messages PATH messages contain a number of objects which define the tunnel to be
established. These are shown in Table 3-4 on page 3-22.
Table 3-4. RSVP-TE PATH Message Objects
Object Contents Usage
SESSION Describes the destination router

and associates a tunnel ID with
the session.
tunnel endpoint The destination router’s IP

address.
tunnel ID A unique LSP tunnel ID.
SENDER_TEMPLATE The description of the sender.
tunnel sender The sender router’s IP address.

address
LSP ID A unique LSP ID.
LABEL_REQUEST Asks all the LSRs to send back

label values through RESV
messages.
SENDER_TSPEC and Both of these objects deal with

ADSPEC bandwidth and other QoS
requirements for the path.
TIME_VALUES Timing values related to the

refresh of tunnel information.
refresh interval The interval between messages.
EXPLICIT_ROUTE Allows the sender to request that

the LSP tunnel follow a specific
path from ingress to egress router.
See Explicit_Route on page 3-22
for more details.
SESSION_ATTRIBUTE Other attributes associated with

the session: tunnel establishment
priorities, session name, and
optionally resource affinity.
RSVP_HOP Describes the immediate

upstream router’s address to the
downstream router.
Explicit_Route An explicit route is a particular path in the network topology. Typically, the
explicit route is determined by a node with the intent of directing traffic along
that path. An explicit route is described as a list of groups of nodes along the
explicit route. In addition to the ability to identify specific nodes along the path,
an explicit route can identify a group of nodes that must be traversed along the
path. Each group of nodes is called an abstract node. Thus, an explicit route is a
specification of a set of abstract nodes to be traversed.

RSVP-TE
There are three types of objects in an explicit route:

• IPv4 prefix
• IPv6 prefix
• Autonomous system number
Each node has a loose bit associated with it. If the bit is not set, the node is
considered strict. The path between a strict node and its preceding node may only
include network nodes from the strict node and its preceding abstract node. The
path between a loose node and its preceding node may include other network
nodes that are not part of the strict node or its preceding abstract node.
RESV Message The RESV message contains object that indicate the success of the PATH request
and the details of the assigned tunnel. These are shown in Table 3-5 on page 3-
23.
Table 3-5. RSVP-TE RESV Message Objects
Object Usage
SESSION Indicates which session is being responded to.
TIME_VALUES As in the PATH message but from the downstream LSR to

the upstream LSR.
STYLE The type of reservation assigned by the egress router.

This relates to whether individual tunnels are requested for
each sender-destination connection or whether some
connections may use the same tunnel.
FILTER_SPEC The sender router’s IP address and the LSP ID.
LABEL The label value assigned by the downstream router for use
by the upstream router.
RECORD_ROUTE If requested, the complete route from the destination back

to the source. The contents of this object include the IP
addresses in either v4 or v6 format of all the LSRs
encountered in the formation of the LSP, and optionally the
labels used at each step. Each LSR on the upstream path
perpends its own address information.
RESV_CONF If present, it indicates that the ingress router should send a

RESV_CONF message in response to the destination to
indicate that the tunnel has been completely established.

3 RSVP-TE
Other Messages Several additional messages are used in RSVP-TE, as explained in Table 3-6 on
page 3-24.
Table 3-6. Additional RSVP-TE Messages
Message Usage
PATH_ERR Any LSR may determine that it cannot accommodate the

tunnel requested in a PATH message. In this case it sends a
PATH_ERR message back to the sender.
PATH_TEAR When a sender router determines that it wants to tear down a

tunnel, it sends a PATH_TEAR message to the destination
router.
RESV_ERR If a router cannot handle a reservation, it sends a RESV_ERR

back to the destination router.
RESV_TEAR When a destination router determines that it wants to tear down

a tunnel, it sends a RESV_TEAR message upstream to the
source router.
RESV_CONF When requested, a sender router responds to the destination

router with a RESV_CONF message to indicate that a
complete tunnel has been successfully established.

RSVP-TE
RSVP-TE Fast RSVP-TE Fast Reroute allows to configure backup LSP tunnels to provide local
Reroute repair/protection ONLY for explicitly-routed LSPs/LSP tunnels, termed
protected LSPs as described in IETF DRAFT draft-ietf-mpls-rsvp-lsp-
fastreroute-03.
An example diagram of a backup scenario for rerouting around a downed link,

using an LSP Detour, is shown in Figure 3-11 on page 3-25. Figure 3-12 on page
3-25 shows an example diagram for a backup scenario to reroute around a
downed node, using an LSP Detour.
Figure 3-11. RSVP-TE Fast Reroute Backup Link (Detour) Example
Figure 3-12. RSVP-TE Fast Reroute Backup Node (Detour) Example

3 RSVP-TE
The one-to-one backup method is based on including a DETOUR object in the

Path message. The head-end router, the Point of Local Repair (PLR), sets up a
separate detour LSP for each LSP it protects. For the Facility backup method, the
PLR sets up a tunnel to protect multiple LSPs simultaneously, by using the
MPLS label stack.
Ixia Test Model The Ixia test process is designed so as to fully exercise RSVP functionality in
MPLS routers. An Ixia port can simulate any number of LSR routers at the same
time. Each router operates in an ingress or egress mode. In the following
discussion, LSRs I and II refer to Figure 3-10 on page 3-20:
• Ingress mode: LSRs I and II are termed a neighbor pair, where LSR I is the
upstream router being simulated and LSR II is its immediate downstream
neighbor. The Ixia port generates the PATH and HELLO messages that LSR
I would send. LSR II is the Device Under Test (DUT) and may be an egress
router or be connected to other LSRs, as shown in the figure.
• Egress mode: the Ixia port simulates LSR II while LSR I is the DUT. The Ixia
port interprets PATH messages that it receives to determine if they are
directed for any of the defined destination routers. If that is the case, it
responds with appropriate RESV messages.
If requested, HELLO messages are generated and responded to in either mode.
When the Ixia port operates in Ingress mode, it attempts to set up LSP tunnels for
each combination of sender router and destination router, using any number of
LSP tunnels and any number of LSP IDs for each LSP tunnel. Thus the number
of PATH messages that the Ixia port attempts to generate for each refresh interval
is:
# of sender routers
x # of destination routers
x # of LSPs
x # of LSP tunnels
The protocol server records all labels and other information that it receives on
behalf of its simulated routers and displays those in a convenient format.

LDP
LDP
The Label Distribution Protocol (LDP) version 1, defined in RFC 3036, works in
conjunction with Multi-Protocol Label Switching (MPLS), to efficiently ‘tunnel’
IP traffic across backbone topologies between Label Switching Routers (LSRs).
MPLS forwards packets based on added labels, so IP routing table lookups are
not required along the length of the tunnel. RFC 3031 defines Forwarding
Equivalence Classes (FECs) for use with MPLS, for purposes such as Quality of
Service (QoS). LDP utilizes this option, assigning an FEC to every Label
Switched Path (LSP) it sets up.
The LDP protocol creates peer sessions through a bidirectional exchange of

messages, which include label requests and labels. While the initial Hello
messages are based on UDP and sent to well-known port ‘646,’ all other
messages are based on TCP.
The following global timers can be configured: Hello Hold timer, Hello Interval
timer, KeepAlive Hold timer, and KeepAlive Interval timer. The values for these
timers can be entered by you, but the final values are negotiated during the
Discovery and Session setup processes. When the LDP remote peer has a timeout
value which is lower than the one configured for the local LDP router, the lower
value is used by both peers.
Virtual Circuit (VC) Ranges of MAC Addresses can be created to simulate

Virtual Private LAN Services (VPLS), where L2 PDUs can be carried over VC
LSPs, which, in turn, are carried over MPLS. This creates a ‘bridged,’ Ethernet
Layer Two Virtual Private Network (Ethernet L2VPN). Refer to IETF DRAFT
draft-lasserre-vkompella-ppvpn-vpls-03, which defines the VC Type - Ethernet
VPLS, and also discusses the use of MPLS transport tunnels by pseudowires
(PWs).
A pseudowire is a logical link through the tunnel, made up of two parallel VC

LSPs using the same VC Identifier (VCID), as shown in Figure 3-13 on page 3-
27, and in more detail in Figure 3-14 on page 3-28.
Figure 3-13. LDP VPLS Example

3 MLD
Figure 3-14. LDP VPLS Pseudowire Diagram
MLD
The Multicast Listener Discovery (MLD) protocol is integral to the operation of
Internet Protocol Version 6 (IPv6). MLDv1 is defined by RFC 2710, while
MLDv2 is defined by RFC 3810. The MLD operations are based on operations
similar to the Internet Group Management Protocol (IGMP) that supports IPv4.
MLDv2 corresponds to IGMPv3. Both versions are supported by the protocol
server.
An IPv6 router uses MLD to: (1) discover multicast listeners (nodes) on the
directly attached links, and (2) find out which multicast addresses those nodes
have interest in. In MLDv2, nodes can indicate interest in listening to packets
that are sent to a specific multicast address from a filtered group of source IP
addresses. This filtering can be based on ‘all but’ (Excluding) or ‘only’
(Including) certain source addresses. Host nodes can only be multicast ‘listeners,’
while the multicast routers can act as routers or listeners.

PIM-SM/SSM-v4/v6
PIM-SM/SSM-v4/v6
Protocol Independent Multicast - Sparse Mode (PIM-SM) Version 2 protocol is
designed for multicast routing, and is defined in RFC 2362. IETF DRAFT draft-
ietf-pim-sm-v2-new-06.txt is being designed to obsolete RFC 2362.
There is one Rendezvous Point (RP) per multicast group, and this router serves as
the root of a unidirectional shared distribution tree whose ‘leaves’ consist of
multicast receivers. In addition, PIM-SM can create an optional shortest-path tree
for an individual source (where the source is the root). The term upstream is used
to indicate the direction toward the root of the tree; downstream indicates the
direction away from the root of the tree. The address of the RP can be configured
statically by an administrator, or configured through a Bootstrap router (BSR)
mechanism.
PIM-SM can use two sources of topology information to populate its routing
table, the Multicast Routing Information Base (MRIB): unicast or multicast-
capable. In a LAN where there are multiple PIM-SM routers and directly-
connected hosts, one of the routers is elected as Designated Router (DR) to act on
the behalf of the hosts.
The diagram in Figure 3-15 on page 3-29 shows a simplified PIM-SM test setup
using Ixia ports.
Figure 3-15. PIM-SM Diagram

3 PIM-SM/SSM-v4/v6
PIM-SM Source- PIM-SM Source-Group mapping involves the pairing of Sources and Groups.
Group Mapping The default method is a fully-meshed mapping of sources to groups, where every
source is paired with every group. For a situation where there are ‘X’ number of
sources and ‘Y’ number of groups, there will be ‘X x Y’ number of mappings,
resulting in a great deal of memory usage for processing. When full-mesh
mapping is not desired, the optional ‘One-To-One’ Source-Group Mapping can
be used to save memory. In comparison, if a one-to-one type mapping behavior
was preferred and only a full-mesh setup was available, you would have to create
‘N’ fully-meshed source-group mapping ranges of size ‘1’ to emulate the one-to-
one behavior. An example showing the differences between the two types of
mapping is shown in Figure 3-16 on page 3-30.
Figure 3-16. PIM-SM Source-Group Mapping Example

PIM-SM/SSM-v4/v6
PIM-SSM Protocol Independent Multicast - Source-Specific Multicast (PIM-SSM) uses a

subset of the PIM-SM protocol, described in draft-ietf-ssm-arch-06, Source-
Specific Multicast for IP, and in Section 4.8 of draft-ietf-pim-sm-v2-new-11,
Protocol Independent Multicast - Sparse Mode (PIM-SM): Protocol Specification
(Revised).
PIM-SSM is useful for broadcast-type applications, where one source sends

packets to many host groups. There is no shared distribution tree topology, but
there is a shortest-path tree (SPT) established, where the source is the root of the
tree. In the case of SSM, the usual PIM-SM multicast terminology is modified,
and the term Channel is used instead of Group and Subscription replaces Join. A
multicast group (G) router that wants to receive packets from a specific Source
(S) for its hosts/listeners, will ‘Subscribe’ to ‘Channel (S,G).’ An example of an
PIM-SSM topology is shown in Figure 3-17 on page 3-31.
Figure 3-17. PIM-SSM Topology Example
An existing PIM-SM network can be modified to run SSM by enabling PIM-

SSM on the source and destination/group routers. The typical PIM-SM signaling
is not used for PIM-SSM, since the role of Rendezvous Point (RP) router is
eliminated. The Subscribe (Join) message travels directly from the Destination
router to the Source router, and data packets are transmitted in the opposite
direction.
PIM-SSM Addressing
The PIM-SSM protocol uses a restricted addressing scheme, with reserved values
for IPv4 SSM addresses defined by the IANA as 232.0.0.0 through
232.255.255.255 (232/8). IPv6 SSM addresses are defined in IETF DRAFT
draft-ietf-ssm-arch- 06 and draft-ietf-pim-sm-v2-new-11 as FF3x: : /32. The
range of FF3x: : /96 is proposed by RFC 3307, ‘Allocation Guidelines for IPv6
Multicast Addresses.’

3 PIM-SM/SSM-v4/v6
Differences Between PIM-SM and PIM-SSM
Some of the principal differences between PIM-SM and PIM-SSM routers, per
draft-ietf-ssm-arch-06, are mentioned in the following list:
• PIM-SSM-only routers must not send (*,G) Join/Prune messages.
• PIM-SSM-only routers must not send (S,G,rpt) Join/Prune messages.
• PIM-SSM-only routers must not send Register messages for packets with
SSM destination addresses.
• PIM-SSM-only routers must act in accordance with (*,G) or (S,G,rpt) state
by forwarding packets with SSM destination addresses.
• PIM-SSM-only routers acting as RPs must not forward Register messages
for packets with SSM destination addresses.
Protocol Elements for PIM-SSM
Protocol elements required for PIM-SSM-only routers are mentioned in the

following list:
• (S,G) Downstream and Upstream state machines.
• Hello messages, neighbor discovery, and DR election.
• Packet forwarding rules.
• [(S,G) Assert state machine]
Some of the Protocol elements not required for PIM-SSM-only routers are
mentioned in the following list:
• Register state machine
• (*,G), (S,G,rpt), and (*,*,RP) Downstream and Upstream state machines.
• Keepalive Timer (treated as always running)
• SptBit (treated as always set for an SSM address)

PIM-SM/SSM-v4/v6
Multicast VPNs Multicast VPNs (MVPNs) can be created through the use of MP-BGP combined
with PIM-SM. Multicast VPNs can be set up by a Service Provider to support
scalable, IPv4 multicast traffic solutions, based on IETF draft-rosen-vpn-mcast-
07, ‘Multicast in MPLS/BGP IP VPNs.’
Multicast VRFs (MVRFs) on each PE router contain multicast routing tables.

Within a Service Provider’s domain, each MVRF is assigned to a Multicast
Domain (MD), which is a set of MVRFs that can send multicast traffic to one
another. Multicast packets from CE routers are sent over a (GRE) multicast
tunnel to other PE routers in the multicast domain. A simplified example of a
Multicast VPN topology, with one MVPN, is shown in Figure 3-18 on page 3-33.
Figure 3-18. Multicast VPN Topology Example
Each CE and its connected PE set up a PIM-SM adjacency. However, CEs do not
set up PIM-SM adjacencies with each other. Separate CE-associated instances of
PIM are run by each PE router, and these are called ‘PIM C-instances.’ Each C-
instance is MVRF-specific. As each PE can be affiliated with many MVPNs/
MVRFs, the router can run many PIM C-instances simultaneously, up to a
maximum of one C-instance per MVRF.
PIM Provider-wide instances (‘PIM P-instances’) are run by each PE router,

creating a global PIM adjacency with all of its IGP PIM-SM-enabled neighbors
(P routers). P routers cannot set up PIM-SM C-instances.
At startup for the multicast domain’s Provider Edge (PE) routers, the default
Multicast Distribution Tree (MDT) is set up automatically. Each Multicast
Domain is identified by a globally unique Service Provider (P) Group address
and a Route Distinguisher. The MD group address is created by using BGP (L3
Site window). It is a valid 4-byte IPv4 multicast address prefix (for example,
239.1.1.1/32). The 12-byte Route Distinguisher is also created through BGP (L3
Site window). This Ixia implementation uses an RD value = 2. One C-Multicast
Group Range (MGR) can be configured for each MVRF.

3 MPLS
MPLS
Multi-Protocol Label Switching (MPLS) is based on the concept of label
switching: and independent and unique ‘label’ is added to each data packet and
this label is used to switch and route the packet through the network. The label is
simple, essentially a shorthand version of the packet’s header information, so
network equipment can be optimized around processing the label and forwarding
traffic. This concept has been around the data communications industry for years.
X.25, Frame Relay, and ATM are examples of label switching technologies.
It is important to understand the differences in the way MPLS and IP routing

forward data across a network. Traditional IP packet forwarding uses the IP
destination address in the packet’s header to make an independent forwarding
decision at each router in the network. These hop-by-hop decisions are based on
network layer routing protocols, such as Open Shortest Path First (OPSF) or
Border Gateway Protocol (BGP). These routing protocols are designed to find
the shortest path through the network, and do not consider other factors, such as
latency or traffic congestion.
MPLS creates a connection-based model overlaid onto the traditionally

connectionless framework of IP routed networks. This connection-oriented
architecture opens the door to a wealth of new possibilities for managing traffic
on an IP network. MPLS builds on IP, combining the intelligence of routing,
which is fundamental to the operation of the Internet and today’s IP networks,
with the high performance of switching. Beyond its applicability to IP
networking, MPLS is being expanded for more general applications in the form
of Generalized MPLS (GMPLS), with applications in optical and Time-Division
Multiplexing (TDM) networks.
One of the primary original goals of MPLS, boosting the performance of

software-based IP routers, has been superseded as advances in silicon technology
have enabled line-rate routing performance implemented in router hardware. In
the meantime, additional benefits of MPLS have been realized, notably Virtual
Private Network (VPN) services and traffic engineering (TE).
Advantages of Some of the advantages of using MPLS are:

MPLS • MPLS enables traffic engineering. Explicit traffic routing and engineering
help squeeze more data into available bandwidth.
• MPLS supports the delivery of services with Quality of Service (QoS)
guarantees. Packets can be marked for high quality, enabling providers to
maintain a specified low end-to-end latency for voice and video.
• MPLS reduces router processing requirements, since routers simply forward
packets based on fixed labels.

MPLS
How Does MPLS MPLS is a technology used for optimizing forwarding through a network.
Work? Though MPLS can be applied in many different network environments, this
discussion focuses primarily on MPLS in IP packet networks, by far the most
common application of MPLS today.
MPLS assigns labels to packets for transport across a network. The labels are
contained in an MPLS header inserted into the data packet.
These short, fixed-length labels carry the information that tells each switching
node (router) how to process and forward the packets, from source to destination.
They have significance only on a local node-to-node connection. As each node
forwards the packet, it swaps the current label for the appropriate label to route
the packet to the next node. This mechanism enables very-high-speed switching
of the packets through the core MPLS network.
MPLS combines the best of both Layer 3 IP routing and Layer 2 switching. In
fact, it is sometimes called a ‘Layer 2-1/2’ protocol. While routers require
network-level intelligence to determine where to send traffic, switches only send
data to the next hop, and so are inherently simpler, faster, and less costly. MPLS
relies on traditional IP routing protocols to advertise and establish the network
topology. MPLS is then overlaid on top of this topology. MPLS predetermines
the path data takes across a network and encodes that information into a label that
the network’s routers can understand. This is the connection-oriented approach
previously discussed. Since route planning occurs ahead of time and at the edge
of the network (where the customer and service provider network meet), MPLS-
labeled data requires less router horsepower to traverse the core of the service
provider’s network.
MPLS Routing
MPLS networks establish Label-Switched Paths (LSPs) for data crossing the
network. An LSP is defined by a sequence of labels assigned to nodes on the
packet’s path from source to destination. LSPs direct packets in one of two ways:
hop-by-hop routing or explicit routing.
Hop-by-Hop Routing
In hop-by-hop routing, each MPLS router independently selects the next hop for
a given Forwarding Equivalency Class (FEC). A FEC describes a group of
packets of the same type; all packets assigned to a FEC receive the same routing
treatment. FECs can be based on an IP address route or the service requirements
for a packet, such as low latency.
In the case of hop-by-hop routing, MPLS uses the network topology information
distributed by traditional Interior Gateway Protocols (IGPs) routing protocols
such as OPSF or IS-IS. This process is similar to traditional routing in IP
networks, and the LSPs follow the routes the IGPs dictate.

3 BFD
Explicit Routing
In explicit routing, the entire list of nodes traversed by the LSP is specified in
advance. The path specified could be optimal or not, but is based on the overall
view of the network topology and, potentially, on additional constraints. This is
called Constraint-Based Routing. Along the path, resources may be reserved to
ensure QoS. This permits traffic engineering to be deployed in the network to
optimize use of bandwidth.
Label Information Base
As the network is established and signaled, each MPLS router builds a Label
Information Base (LIB), a table that specifies how to forward a packet. This table
associates each label with its corresponding FEC and the outbound port to
forward the packet to. This LIB is typically established in addition to the routing
table and Forwarding Information Base (FIC) that traditional routers maintain.
Connections are signaled and labels are distributed among nodes in an MPLS
network using one of several signaling protocols, including Label Distribution
Protocol (LDP) and Resource reSerVation Protocol with Tunneling Extensions
(RSVPTE). Alternatively, label assignment can be piggybacked onto existing IP
routing protocols such as BGP.
The most commonly used MPLS signaling protocol is LDP. LDP defines a set of
procedures used by MPLS routers to exchange label and stream mapping
information. It is used to establish LSPs, mapping routing information directly to
Layer 2 switched paths. It is also commonly used to signal at the edge of the
MPLS network, the critical point where non-MPLS traffic enters. Such signaling
is required when establishing MPLS VPNs.
RSVP-TE is also used for label distribution, most commonly in the core of
networks that require traffic engineering and QoS. A set of extensions to the
original RSVP protocol, RSVP-TE provides additional functionality beyond
label distribution, such as explicit LSP routing, dynamic rerouting around
network failures, preemption of LSPs, and loop detection. RSVP-TE can
distribute traffic engineering parameters such as bandwidth reservations and QoS
requirements.
Multi-protocol extensions have been defined for BGP, enabling the protocol to
also be used to distribute MPLS labels. MPLS labels are piggybacked onto the
same BGP messages used to distribute the associated routes. MPLS allows
multiple labels (called a label stack) to be carried on a packet. Label stacking
enables MPLS nodes to differentiate between types of data flows, and to set up
and distribute LSPs accordingly. A common use of label stacking is for
establishing tunnels through MPLS networks for VPN applications.
BFD
Bidirectional Forwarding Detection (BFD) is a network protocol used to detect
faults between two forwarding engines. It provides low-overhead detection of

CFM
faults even on physical media that don't support failure detection of any kind,
such as ethernet, virtual circuits, tunnels and MPLS LSPs.
BFD establishes a session between two endpoints over a particular link. If more
than one link exists between two systems, multiple BFD sessions may be
established to monitor each one of them. The session is established with a three-
way handshake, and is torn down the same way. Authentication may be enabled
on the session. A choice of simple password, MD5 or SHA1 authentication is
available.
BFD does not have a discovery mechanism; sessions must be explicitly

configured between endpoints. BFD may be used on many different underlying
transport mechanisms and layers, and operates independently of all of these.
Therefore, it needs to be encapsulated by whatever transport it uses. For example,
monitoring MPLS LSPs involves piggybacking session establishment on LSP-
Ping packets. Protocols that support some form of adjacency setup, such as OSPF
or IS-IS, may also be used to bootstrap a BFD session. These protocols may then
use BFD to receive faster notification of failing links than would normally be
possible using the protocol's own keepalive mechanism.
A session may operate in one of two modes: asynchronous mode and demand
mode. In asynchronous mode, both endpoints periodically send Hello packets to
each other. If a number of those packets are not received, the session is
considered down.
In demand mode, no Hello packets are exchanged after the session is established;
it is assumed that the endpoints have another way to verify connectivity to each
other, perhaps on the underlying physical layer. However, either host may still
send Hello packets if needed.
Regardless of which mode is in use, either endpoint may also initiate an Echo
function. When this function is active, a stream of Echo packets is sent, and the
other endpoint then sends these back to the sender through its forwarding plane.
This is used to test the forwarding path on the remote system.
CFM
Ethernet CFM is an end-to-end per-service-instance Ethernet layer OAM
protocol that includes proactive connectivity monitoring, fault verification, and
fault isolation. End to end can be PE to PE or customer edge (CE) to CE. Per
service instance means per VLAN.
Being an end-to-end technology is the distinction between CFM and other metro-
Ethernet OAM protocols. For example, MPLS, ATM, and SONET OAM help in
debugging Ethernet wires but are not always end-to-end. 802.3ah OAM is a
single-hop and per-physical-wire protocol. It is not end to end or service aware.
Ethernet Local Management Interface (E-LMI) is confined between the uPE and
CE and relies on CFM for reporting status of the metro-Ethernet network to the
CE.

3 CFM
Troubleshooting carrier networks offering Ethernet Layer 2 services can be

difficult. Customers contract with service providers for end-to-end Ethernet
service and service providers may subcontract with operators to provide
equipment and networks. Compared to enterprise networks, where Ethernet
traditionally has been implemented, these constituent networks belong to distinct
organizations or departments, are substantially larger and more complex, and
have a wider user base. Ethernet CFM provides a competitive advantage to
service providers for which the operational management of link uptime and
timeliness in isolating and responding to failures is crucial to daily operations.

FCoE and NPIV
FCoE and NPIV

IxExplorer provides GUI access to all Ixia platform functionality with full
support for stateless FCoE functional and scalability testing. The FCoE and
Priority Flow Control (PFC) and FCoE Initialization Protocol (FIP) features
allow testing of FCoE switches running both FCoE traffic and traditional
Ethernet traffic.
Supported Load The following Ixia load modules have the Fibre Channel over Ethernet (FCoE)
Modules capability:
• LSM10GXM8-01, GXMR8-01, and GXM8XP-01, including 10GBASE-T
versions LSM10GXM(R)8GBT-01
• LSM10GXM4-01, GXMR4-01, and GXM4XP-01, including 10GBASE-T
versions LSM10GXM(R)4GBT-01
• LSM10GXM2XP-01 and GXMR2-01, including 10GBASE-T versions
LSM10GXM(R)2GBT-01
• LSM1000XMVDCx-01 load modules. 4-port, 8-port, 12-port, and 16-port
• LSM1000XMVDC4-NG load modules. 4-port
Data Center Mode FCoE support requires a new port mode, Data Center Mode. You need to switch
port mode between Normal Mode and Data Center Mode to use the desired
features in each mode.
• Mode switching (to or from Data Center Mode) triggers an FPGA re-
download.
• There is no Packet Stream Mode support in Data Center Mode; only
Advanced Scheduler Mode is supported.
• Supports 4-Priority traffic mapping for frame size up to 9216-byte. The
different frame size support is determined by a sub mode in Data Center
Mode. This limitation applies to all frames in Data Center Mode, whether
FCoE frame or not.
• Data Center Mode only supports auto instrumentation mode for both TX and
RX.
• When the port is in Data Center Mode, both existing Ethernet frames and
FCoE frames are generated.
Priority Traffic The scheduling function is based on the existing Advanced Scheduler. A new
Generation parameter called ‘Priority Group’ has been added to each stream. You can map
Priority Group to the priority field in the frame. The priority field in the same
stream should not change (for example, if the priority is a VLAN priority field,
then you cannot configure a UDF to control this field within a stream).

3 FCoE and NPIV
Priority-based Flow Control (PFC)
The Ixia port responds to either IEEE 802.3x pause frame or to IEEE 802.1Qbb
Priority-based Flow Control (PFC) frame. The flow control type is determined by
the selection made on the Flow Control tab of the Port Properties dialog, in
IxExplorer.
IxExplorer Reference
See IxExplorer User Guide, Chapter 6 topic Frame Data for FCoE Support,
subtopic Priority-based Flow Control.
Fibre Channel over When the port is in Data Center Mode, both existing Ethernet frames and FCoE
Ethernet frames are generated.
The Fibre Channel CRC is generated on the fly. This CRC is inserted at offset of
Ethernet frame size minus 12 bytes. For example:
Ethernet Frame Size 2000 2001 2002 2003

(bytes)
FC-CRC Offset in FCoE 1988 1989 1990 1991

Frame (bytes)
The FC-CRC can be set to No Error or to Bad CRC.
Packet View Support
For Fibre Channel frame, there is no Extended Header and Optional Header
support. It decodes only FC-2 Frame Header field.
FCoE Initialization Protocol (FIP)
FIP (FCoE Initialization Protocol) has been implemented (in addition to FCoE).
It is used to discover and initialize FCoE capable entities connected to an
Ethernet cloud.
IxExplorer Reference
See the IxExplorer User Guide, Chapter 6 topic Frame Data for FCoE Support.
NPIV Protocol NPIV stands for N_Port ID Virtualization. These can be used to virtually share a
Interface single physical N_Port. This allows multiple Fibre Channel initiators to occupy a
single physical port, easing hardware requirements in SAN design. Up to 256
N_Port_IDs can be assigned to a single N_Port. NPIV interfaces can be
configured using the Protocol Interface Wizard.
See the IxExplorer User Guide, Chapter 10, topic NPIV Protocol Interface.

Precision Time Protocol (PTP) IEEE 1588v2
Precision Time Protocol (PTP)

IEEE 1588v2
Precision Time Protocol (IEEE 1588v2) allows precise synchronization of clocks
in measurement and controls systems implemented with technologies such as
network communications, local computing and distributed objects. The protocol
supports system wide synchronization accuracy in sub-microseconds range with
minimal network and local clock computing resources. The protocol operates in
master/subordinate configuration. IEEE1588 deploys Multicast over an Ethernet
network, and devices such as routers and switches can sync to the provided
timing source.
Supported Load The following Ixia load modules have the PTP capability:
Modules • LSM1000XMV(R)16, XMV(R)12, XMV(R)8, XMV(R)4
• ASM1000XMV12X
• Xcellon-Ultra XP, NP, and NG
Supported The following messages are supported between clocks participating in the PTP
Messages protocol.
• Event messages
• Sync
• Delay Request
• General Messages
• Announce
• Follow_up
• Delay_Response
Supported Features The following PTP features are supported.

• Only one two-step clock is supported on an Ixia port, at this time. One-step
clock is not supported.
• Ixia ports can run other (non-PTP) traffic along with PTP traffic. Ixia ports
have the ability to throttle transmit based on flow control packets being
received.
• IEEE 1588 version 2.2 in IPV4 (multicast) is supported.
• Ports are manually configured in Master or Subordinate mode.
• A histogram reporting Subordinate clock OFFSET from master is provided in
the form of plot along with PTP messages transmitted and received.
• Aggregate statistics are displayed in Statistics View in IxExplorer.
• Session/Per Interface stats is displayed in IxNw/Tcl/csv file.

3 Precision Time Protocol (PTP) IEEE 1588v2
• Per Interface configuration is done in protocol interfaces.

• Ability to compose or decode PTP messages from the IxExplorer user
interface.
• Negative testing is supported.
• Programmable follow-up messages as a percentage of sync messages.
See how dropping 10-90% of follow-up messages (while sending
100% of sync messages) affects the DUT.
• Send follow-up messages with a bad packet.
• Purposely send data with timestamps that include jitter (to try forcing
a sync to fail).
• Negative testing is done with packet streams/linux.
Local Clock The local clock of the is synchronized to the ’s master clock by minimizing the
synchronization Offset_from_master value of the current data set. The time and the rate
through PTP to characteristics of the local clock are modified upon receipt of either a sync
message or follow-up message. Figure 3-19 illustrates the PTP communication
another PTP clock path.

Figure 3-19. PTP Communication Path
Table 3-7. PTP Communication Path
Term Value
sync_receipt_time = Ts1 Ts1 =Tm1+O+master_to__delay
preciseOriginTimestamp Tm1
= Tm1
master_to__delay Ts1–Tm1
(computed)
delay_req_sending_tim Ts2
e = Ts2
delayReceiptTimestamp Tm2 = Ts2 – O + _to_master_delay

= Tm2
_to_master_delay Tm2 – Ts2

(computed)

3 Precision Time Protocol (PTP) IEEE 1588v2
Table 3-7. PTP Communication Path
Term Value
one_way_delay {(master_to__delay as computed) +

(_to_master_delay as computed)}/2
{(Ts1-Tm1) + (Tm2-Ts2)}/2
{(O + master_to__delay ) +
–O +_to_master_delay)}/2
{(master_to__delay ) + (_to_master_delay)}/2
master_to__delay if path is symmetrical
Notes:
1. Offset shall be computed as O= Ts1-Tm1 - one_way_Delay. Offset and One way delay
shall be stored.
2. Offset correction shall be applied to the local clock.
Local clock In Slave mode of operation, the Ixia port implements a local clock in software
frequency transfer (Linux). The frequency of the oscillator is not adjusted but allowed to free-run.
The local clock shall be implemented based on time information synchronized
from sync/follow_up messages and hardware timestamps associated with these
messages. The local clock is associated with a constant and a slope. The rate of a
local clock relative to a master clock is illustrated in Figure 3-20.
IxExplorer See the IxExplorer User Guide, Chapter 10, Protocol Interfaces, especially topics
References Protocol Interfaces Tab, PTP Discovered Information, and PTP Clock
Configuration.
Figure 3-20. Rate of Local Clock Relative to Master
• Clock = K+ Slope*(TS-TS1),

• Slope = (T2-T1)/(TS2-TS1).
• K = T1
Where T1 is the time synchronized from the master and TS1 is the hardware
timestamp associated with sync message 1. T2 and TS2 are corresponding
parameters associated with sync message 2. T is the time at any point of time.
With a sync message, the parameters K and the slope are updated. The Clock
Offset from master is calculated as discussed above and applied to K for
correction.
Timestamps are cleared once when PTP is enabled.
In master mode of operation, server provides timestamp to the ports at the instant
timestamps are cleared and slope is 1. OFFSET from master is 0.
If a GPS source is interfaced to the chassis, ports emulating the master are
configured as Grand Master.
Local clock time format is seconds (32 bits) and nanoseconds (32 bits). The Ixia
port supports a 2-step clock.

3 ATM Interfaces
ATM Interfaces
On Asynchronous Transport Mode (ATM) is a Layer 2, connection-oriented,
switching protocol, based on L2 Virtual Circuits (VCs). For operation in a
connectionless IP routing or bridging environment, the IP PDUs must be
encapsulated within the payload field of an ATM AAL5 CPCS-PDU (ATM
Adaptation Layer 5—Common Part Convergence Sublayer—Protocol Data
Unit). The ATM CPCS-PDUs are divided into 48-byte segments which receive
5-byte headers to form 53-byte ATM cells.
The ATM cells are then switched across the ATM network, based on the Virtual
Port Identifiers (VPIs) and the Virtual Connection Identifiers (VCIs). The
relationship between VPIs (identifying one hop between adjacent nodes) and
VCIs (identifying the end-to-end virtual connection) is illustrated in Figure 3-21
on page 3-46.
Figure 3-21. ATM VPI/VCI Pairs (PVCs)
‘Bridged ATM’ The ATM AAL5 frames allow for the overlay of the connectionless IP bridging
Versus ‘Routed or routing environment over the network of ATM nodes (that have frame
ATM’ handling capability). Each ATM node examines the payload of the AAL5 frame,
and forwards the frame to the next node, based on the payload’s MAC
destination address (for IP bridging) or IP destination address (for IP routing). In
effect, the ATM environment functions as a simulated Ethernet or IP network,
respectively.
In the case of Label Distribution Protocol (LDP) routing over ATM, the process
becomes more complex since MPLS tunnels are created over ATM core
networks. For more information on the signaling, session setup, and label

ATM Interfaces
distribution for LDP routing over ATM, see the IxNetwork Users Guide:
Network Protocols - LDP chapter.
ATM Encapsulation There are two main types of ATM Multiplexing encapsulations defined by RFC
Types 2684, ‘Multiprotocol Encapsulation over ATM Adaptation Layer 5.’ The ATM
AAL5 Frame is described in ATM Frame Formats on page 3-50. The various
encapsulation types and references to diagrams of the encapsulated frame
payloads are listed as follows:
• VC Multiplexing (VC Mux): used when only one protocol is to be carried on
a single ATM VC. Separate VCs are used if multiple protocols are being
transported.
• VC Mux IPv4 Routed: see Figure 3-27 on page 3-52
• VC Mux Bridged Ethernet/802.3 (FCS): see Figure 3-23 on page 3-51
• VC Mux Bridged Ethernet/802.3 (no FCS): see Figure 3-24 on page 3-51
• Logical Link Control (LLC): used for multiplexing multiple protocols over
a single ATM virtual connection (VC).
• LLC Routed AAL 5 Snap: see Figure 3-29 on page 3-53
• LLC Bridged Ethernet (FCS): see Figure 3-25 on page 3-51
• LLC Bridged Ethernet (no FCS): see Figure 3-26 on page 3-52
Note: The Protocol Configuration Wizards for BGP, OSPFv2, and ISIS allow
configuration on ATM ports, but ONLY for the VC Mux Bridged Ethernet/802.3
(FCS) encapsulation type.
Encapsulation Types by Protocol
The types of RFC 2684 ATM encapsulations available for each Ixia routing
protocol emulation are listed in Table 3-8 on page 3-47.
Table 3-8. ATM Encapsulations for Protocols
Routing Protocol ATM Encapsulation Type
BGP ‘Bridged ATM’:

• VC Mux Bridged Ethernet/802.3 (FCS) - (the default)
• VC Mux Bridged Ethernet/802.3 (no FCS)
• LLC Bridged Ethernet (FCS)
• LLC Bridged Ethernet (no FCS)
‘Routed ATM’:
• VC Mux IPv4 Routed
• LLC Routed AAL5 Snap

3 ATM Interfaces
OSPF (v2 only) ‘Bridged ATM’:

Note: Supported for • VC Mux Bridged Ethernet/802.3 (no FCS)
both Point-to-Point • LLC Bridged Ethernet (FCS)
and Point-to- • LLC Bridged Ethernet (no FCS)
MultiPoint links.
‘Routed ATM’:
• LLC Routed AAL5 Snap
LDP ‘Bridged ATM’:

Note: Discovery • VC Mux Bridged Ethernet/802.3 (no FCS)
Mode must be set to • LLC Bridged Ethernet (FCS)
Basic, and • LLC Bridged Ethernet (no FCS)
Advertising Mode
‘Routed ATM’:
must be set to
Downstream on • VC Mux IPv4 Routed
Demand (DoD). • LLC Routed AAL5 Snap
RSVP-TE ‘Bridged ATM’:

ISIS ‘Bridged ATM’:

RIP ‘Bridged ATM’:

RIPng ‘Bridged ATM’:

IGMP ‘Bridged ATM’:


ATM Interfaces
MLD ‘Bridged ATM’:

• VC Mux Bridged Ethernet/802.3 (FCS)-(the default)
PIM-SM ‘Bridged ATM’:

• VC Mux Bridged Ethernet/802.3 (FCS)-(the default)

3 ATM Interfaces
ATM Frame The format of the ATM AAL5 CPCS-PDU (ATM AAL5 Frame) is shown in
Formats Figure 3-22 on page 3-50. The formats of the various types of AAL5 CPCS-PDU
payloads for these frames are shown in the following diagrams:
• BRIDGED:
• VC Mux Bridged Ethernet/802.3 (FCS): see Figure 3-23 on page 3-51
• VC Mux Bridged Ethernet/802.3 (no FCS): see Figure 3-24 on page 3-51
• LLC Mux Bridged Ethernet (FCS): see Figure 3-25 on page 3-51
• LLC Mux Bridged Ethernet (no FCS): see Figure 3-26 on page 3-52
• ROUTED:
• LLC Routed AAL5 Snap: see Figure 3-29 on page 3-53
Figure 3-22. ATM AAL5 CPCS-PDU (ATM AAL5 Frame)

ATM Interfaces
Figure 3-23. VC Mux Bridged Ethernet/802.3 (FCS)
Figure 3-24. VC Mux Bridged Ethernet/802.3 (no FCS)
Figure 3-25. LLC Bridged Ethernet (FCS)

3 ATM Interfaces
Figure 3-26. LLC Bridged Ethernet (no FCS)
Figure 3-27. VC Mux IPv4 Routed
Figure 3-28. VC Mux IPv6 Routed

Generic Routing Encapsulation (GRE)
Figure 3-29. LLC Routed AAL5 Snap
Generic Routing Encapsulation

(GRE)
RFC 2784, ‘Generic Routing Encapsulation’ (GRE), provides a mechanism for
encapsulating a payload packet to send that packet over a network of a different
type. First, a GRE header is prepended to the payload packet, and the Ethertype
for the protocol used in that packet is included in the GRE header. Then, a
Delivery header is prepended to the GRE header, which adds a Layer 2 Data Link
Layer address plus a Layer 3 Network address (for a network protocol in this
implementation, either IPv4 or IPv6). After a GRE-encapsulated payload packet
has reached the last router of the GRE ‘tunnel,’ this router removes the GRE
header and forwards the payload as a ‘normal’ packet for the native protocol in
the network.
This is a relatively simple type of encapsulation and can be used to transparently

carry packets for many different protocols, since it is based on Ethertypes. The
original specifications for this encapsulation were RFC 1701, ‘Generic Routing
Encapsulation (GRE),’ published in 1994, and RFC 1702, ‘Generic Routing
Encapsulation over IPv4 Networks,’ also published in 1994.
RFC 2890, ‘Key and Sequence Number Extensions to GRE,’ provides optional
fields for identifying individual traffic flows within a GRE tunnel through an
authentication key value, and for monitoring the sequence of packets within each
GRE tunnel.

3 Generic Routing Encapsulation (GRE)
GRE Packet Format Both control and data packets can be GRE-encapsulated. The overall format of a
GRE-encapsulated packet is shown in Figure 3-30 on page 3-54.
Figure 3-30. GRE-Encapsulated Packet
GRE Packet There are two formats for the GRE Packet Headers:
Headers • GRE Header per RFC 2784 on page 3-54
• GRE Header per RFC 2890 on page 3-55
GRE Header per RFC 2784
The format of a GRE packet header per RFC 2784 is shown in Figure 3-31 on
page 3-54.
Figure 3-31. GRE Packet Header (per RFC 2784)
The fields in the GRE header, per RFC 2784, are described in Table 3-9 on page
3-54.
Table 3-9. GRE Header Fields (per RFC 2784)
Field Description
C The Checksum Present flag bit.

If set (= 1), the Checksum and Reserved1 fields are present,
and the information in the Checksum field is valid.

Generic Routing Encapsulation (GRE)
Field Description
Reserved0 (Bits 1 - 12)

• Bits 1 - 5 unless the receiver is implementing RFC 1701,
the receiver must discard the packet if any of these bits
are non-zero.
• Bits 6 - 12 reserved for future use.
Ver The Version Number field.

The value must be zero.
Protocol Type Protocol Type field.

The protocol type of the payload packet. These values are
defined in RFC 1700, ‘Assigned Numbers’ and by the IANA
‘ETHER TYPES’ document.
When the payload is an IPv4 packet, the protocol type must
be set to 0x800 (Ethertype for IPv4).
Checksum (Optional)
The IP (one’s complement) checksum of all of the 16-bit
words in the GRE header and the payload packet. The value
of the checksum field = zero for the purpose of computing
the checksum.
The checksum field is present only if Checksum Present bit
is set (= 1).
Reserved1 (Optional)
These bits are reserved for future use.
This field is present only if the Checksum field is present
(that is, the Checksum Present bit = 0).
If present, this field must be transmitted as zero.
GRE Header per RFC 2890
The format of a GRE header, with added information per RFC 2890, is shown in
Figure 3-32. GRE Header (per RFC 2890)

3 Generic Routing Encapsulation (GRE)
The fields in the GRE header, per RFC 2890, are described in Table 3-10 on page
3-56.
Field Description
C The Checksum Present flag bit.

If set (= 1), the Checksum field and the Reserved1 is
present, and the information in the Checksum field is
valid.
Reserved0 Bits 1 - 12.

For bits 1 - 5, unless the receiver is implementing RFC
1701 the receiver must discard the packet if any of
these bits are non-zero.
For bits 6 - 12, these bits are reserved for future use.
K The Key Present flag bit.

If set (= 1), the Key field is present. If not set (= 0), this
field is not present.
(Compatible with RFC 1701)
S The Sequence Number Present flag bit.

If set (= 1), the Sequence Number Present field is
present. If not set (= 0), this field is not present.
(Compatible with RFC 1701)
Ver The Version Number field.

The value must be zero.
Protocol Type Protocol Type field.

The protocol type of the payload packet. These values
are defined in RFC 1700, ‘Assigned Numbers’ and by
the IANA ‘ETHER TYPES’ document (located at
www.iana.org/assignments/ethernet-numbers).
When the payload is an IPv4 packet, the protocol type
must be set to 0x800 (Ethertype for IPv4).
Checksum (Optional)
The IP (one’s complement) checksum of all of the 16-
bit words in the GRE header and the payload packet.
The value of the checksum field = zero for the purpose
of computing the checksum.
The checksum field is present only if Checksum
Present bit is set (= 1).
Reserved1 (Optional)
These bits are reserved for future use.
This field is only present if the Checksum field is
present (that is, the Checksum Present bit = 0).
If present, this field must be transmitted as zero.

DHCP Protocol
Field Description
Key Present (Optional)

This field is present only if the Key Present bit is set (=
1).
A 4-octet number that can be used to identify an
individual, logical traffic flow within the GRE tunnel.
The encapsulator/sender uses the same key value for
all packets within a single flow, for identification by the
decapsulator/receiver.
Sequence Number (Optional)

Present This field is present only if the Sequence Number
Present bit is set (= 1).
A 4-octet number that can be used to identify the order
of transmission of the packets, with the goal of
providing unreliable, but in-order delivery of packets.
The decapsulator/receiver uses the sequence number
to monitor the order of the packets as they are
received. Out-of-sequence packets should be silently
discarded.
The sequence number of the first packet = 0. The
value range is from 0 to (2 ** 32) -1.
DHCP Protocol
Dynamic Host Configuration Protocol (DHCP) is defined in RFC 2131, and it is
based on earlier work with the protocol for BOOTP relay agents, which was
specified in RFC 951. A DHCP Server provides permanent storage and dynamic
allocation of IPv4 network addresses and other network configuration
information. A DHCP Server is a host, and a DHCP Client is also a host. This
protocol is designed for allocating IPv4 addresses to hosts, but not to routers.
A Client Identifier (Client ID) is required so that the DHCP Server can match a
DHCP client with its ‘lease.’ If the Client does not supply a Client Identifier
option, the Client Hardware MAC Address (chaddr) is used by the Server to
identify the Client. A lease is the period of time that a DHCP Client may use an
IPv4 address that has been allocated by the DHCP Server. This lease period may
be extended, and may even be set to ‘infinity’ (0xffffffff hex), to indicate a
‘permanent’ IPv4 address allocation.
DHCP messages are exchanged between client and server using UDP as the
transport protocol. The DHCP Server port is UDP Port 67, and the DHCP Client
port is UDP Port 68.
DHCPDISCOVER messages are broadcast by the Client on the local subnet, to

reach the DHCP Server. Suggested values for a network address and lease period
may be included in the Discover message. The Server(s) may respond with a
DHCPOFFER message. The Offer message includes available IPv4 network

3 DHCPv6 Protocol
address, plus configuration parameters contained in the DHCP options (TLVs/

objects).
Note: You will not be able to select DHCP-enabled protocol interfaces for use
with Ixia protocol emulations, with the exception of IGMP.
DHCPv6 Protocol
The Dynamic Host Control Protocol for Version 6 (DHCPv6) is defined in RFC
3315. DHCPv6 uses UDP packets to exchange messages between servers and
clients. The servers provide IPv6 addresses and additional configuration
information to clients. A DHCPv6 server listens on a reserved, link-scope
multicast address. A client identifies itself to the server by a link-local source
address.
The groups of IPv6 addresses managed by the servers and clients are called
Identity Associations (IAs), where each IA has a unique identifier. IA_NAs are
identity associations of non-temporary (permanent) IPv6 addresses. IA_TAs are
identity associations of temporary addresses.
RFC 3633, ‘IPv6 Prefix Options for Dynamic Host Configuration Protocol
(DHCP) Version 6,’ adds capability for automated allocation of IPv6 prefixes
from a delegating router to a requesting router. IA_PDs are identity associations
used for delegated IPv6 address prefixes.
The setup for DHCPv6 involves a four-message exchange ‘handshake.’

Maintaining the DHCPv6 client-server relationship, and managing the return or
deletion of IPv6 addresses involves three additional messages. These messages
are described in the following list:
Message exchange (handshake):

• SOLICIT: Client sends a DHCPv6 SOLICIT message to the all DHCPv6
Agents multicast address to locate suitable servers.
• ADVERTISE: Multiple servers respond to the client’s SOLICIT message
by sending an ADVERTISE message to the client. The Client receives and
stores ADVERTISE messages until the first retransmit timeout for
SOLICIT messages, then accepts the message with the highest preference
value. Or, the client immediately accepts an ADVERTISE message that
has the preference value set to 255.
• REQUEST: Client sends a REQUEST message to the DHCPv6 server that
has the highest preference value.
• REPLY: Server responds to the client’s REQUEST message with a
REPLY message containing the IPv6 address and configuration
parameters required by the client.
Additional messages for Maintenance/Return/Deletion of Addresses:

Ethernet OAM
• RENEW: Client sends a RENEW message to the assigned server after the
Renew time specified for the IA. The server may respond with a REPLY
message.
• REBIND: If the client does not receive a response (REPLY) from the
primary (assigned) server, it multicasts a REBIND packet according to the
Rebind time specified for the IA. The server(s) may each respond with a
REPLY message.
• RELEASE: Client sends a RELEASE message to return one or more IPv6
addresses to the server when it has completed using the IPv6 address(es).
• Note: If the client does not receive any REPLY messages from the server
in response to its RENEW or REBIND messages, the client deletes the
assigned addresses according to the valid lifetimes of the addresses.
Ethernet OAM
The IEEE Std 802.3ah Operations, Administration, and Maintenance (OAM)
sublayer provides mechanisms useful for monitoring link operation such as
remote fault indication and remote loopback control. In general, OAM provides
network operators the ability to monitor the health of the network and quickly
determine the location of failing links or fault conditions.
OAM information is conveyed in Slow Protocol frames called OAM Protocol

Data Units (OAM PDUs). OAM PDUs contain the appropriate control and status
information used to monitor, test and troubleshoot OAM-enabled links.
The addition of Ethernet OAM support in IxOS involves the following :

• support in stream configuration dialogs to send OAM packets.
• support for a PCPU based state machine that is configured to act as a
passive mode endpoint and reply to OAM packets.
A list of load modules and the Ethernet OAM statistics they can generate are
provided in Table B-31 on page B-160. Ethernet OAM statistics counters are
defined in Table B-6 on page B-9.

3 Ethernet OAM

Chapter 4: Optixia XM12 Chassis
4
This chapter provides details about the Optixia XM12 chassis—its specifications
and features.
The Optixia XM12 is a next generation chassis that is a combination of the

Optixia backplane architecture and a XM form factor. The 12-slot platform
allows for higher port density load modules. The XM12 High Performance
version has two 2.0 kW powersupplies, while the Standard version has two 1.6
kW power supplies. An upgrade kit is available to convert the Standard XM12 to
the High Performance version. See High Performance Upgrade Kit on page 18.
Caution: This equipment is intended to be installed and maintained by Service

Personnel.
The Optixia XM12 Chassis has 12 slots for support of up to 12 single wide load
modules. The Optixia XM12 supports all load modules with improved system
power and cooling. The Optixia XM12, shown in Figure 4-1, was specifically
designed to allow the hot-swapping of modules, without requiring the chassis to
be powered down.

(or SFP+) ports on load modules uncovered. When transceivers are not
installed, end caps must be used. For details, see Use End Caps on Open Ports
on page xxxvii.

Optixia XM12 Chassis
4
Figure 4-1. Optixia XM12 Chassis
The Optixia family of chassis has improved data throughput between Load
Modules and the chassis, with improved backplane performance.
The Optixia chassis provides improved modularity of major components to

reduce downtime of a failed chassis and reduce the probability of needing to
remove a failed chassis from the test environment. Among the modular features
provided are:
• Power supplies
• Motherboard and support components (RAM, Hard Drive)
• Fans
The motherboard and power supplies are accessible from the front of the chassis.
Each of the modular components is capable of being removed in the field and
replaced with minimum downtime for the customer.
Note: In the event of indications of inadequate power, remove load modules

starting from the low-number slots (slot 1, 2, 3), then working upward toward
slot 12 until the problem is solved.


4 Specifications
Specifications
XM12 Chassis The Optixia XM12 computer and chassis specifications are contained in
Table 4-1.
Table 4-1. Optixia XM12 Specifications
CPU Intel Pentium D, 3.0 GHz
Caution–Battery replacement
There is danger of explosion if battery is incorrectly
replaced. Do not attempt to replace the battery.
Return to Ixia Customer Service for replacement with
the same or equivalent type of battery. Ixia disposes of
used batteries according to the battery manufacturer's
instructions.
Memory 4 GB
Disk 250GB SATA Disk

DVD Drive
Operating System Windows XP Professional
Physical
Load Module Slots 12
Size 19.25 in. W x 17.5 in. H x 21 in. D

(48.9cm W x 44.45cm H x 53.34cm D)
Weight (empty) 83 lb (37.65 kg)
Avg. Shipping Wt. 88 lb (39.92 kg)
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 41°F to 104°F, (5°C to 40°C)

Note: Some high-density/high performance load
modules require a lower maximum ambient operating
temperature than the standard for the chassis. When a
load module that requires the lower maximum operating
temperature is installed in an XM chassis, the maximum
operating temperature of the chassis is adjusted
downward to match the maximum operating
temperature of the load module. The operating
temperature range specification is specified in the
published datasheet for these load modules.
Storage 41°F to 122°F, (5°C to 50°C)
Humidity
Operating 0% to 85%, non-condensing

Specifications
Storage 0% to 85%, non-condensing
Clearance Rear: 4 in (10 cm); fan openings should be clear of all

cables or other obstructions. Sides: 2 in (5 cm) unless
rack mounted.
Power Upper line cord 1: 200-240V 60/50Hz

Standard: 10A, High Performance: 15A
Lower line cord 2: 200-240V 60/50Hz
Standard: 8A, High Performance: 11A
Note: Both power cords must be connected to the AC
power source to provide sufficient power to the chassis.
The upper line cord power supply provides power to the
motherboard, fans, and some load modules. and the
lower line cord power supply provides power to the
remainder of the load modules. The chassis does not
power up unless the upper power cord is installed.
For North American customers, the power cords have
NEMA L6-20P plugs for attachment to the power source
and IEC-60320-C19 connectors that attach to the XM12
chassis.
Caution: The chassis’ safety approvals (UL and CE) are

only valid when the unit is operating from 200-240VAC
mains.
Caution: The socket/outlets used to power the unit

must be installed near the equipment and be easily
accessible because the power plug may be used to
disconnect the unit from the power source.
Caution: Replacement of the power supply cord must

be conducted by a Service Person. The same type cord
and plug configuration shall be utilized.
Power Supplies Standard: two 1.6 kW; High Performance: two 2.0 kW
Front Panel Switches On/Off momentary power push button
Front Panel Connectors
Mouse PS/2 6-pin DIN
Keyboard PS/2 6-pin DIN
Monitor HD-DB15 Super VGA
Printer Female DB25 parallel port
Ethernet RJ-45 10/100/1000Mbps Gigabit Ethernet Management

Port
Firewire IEEE 1394
Serial 1 male DB9 port
USB 4 USB dual type A, 4-pin jack connectors

4 Specifications
Sync In 4-pin RJ11
Sync Out 4-pin RJ11
Line In/Line Out/Mic 3.5mm mini-TRS stereo jacks (qty 3)
Front Panel Indicators See LEDs/LCD Display on page 6
2 Paired LEDs above each slot position indicating

Power and Active status
LCD on front panel indicating chassis information
Back Panel Switches/ Power On/Off rocker switch/Circuit Breakers (qty 2)

Connectors
Power 2 male receptacles (IEC 60320-C19)
Noise The XM12 chassis running at maximum fan speed

capacity may produce noise levels up to 84 db (A).
Electrical Grounding To ensure consistent grounding:

requirements for • All equipment must be mounted and screwed in to grounded 19" racks.
Multi-Chassis
• Equipment should not be powered via distribution units with isolated
system grounding.
configuration
If equipment grounding is not consistent, the software will detect this and
shutdown to protect equipment from damage.
LEDs/LCD Display The Optixia XM12 has the following set of front panel LEDs, for each load
module slot:
Table 4-2. Optixia XM12 LEDs
Label Color Description
Power Green For each load module slot, the Power LED is
illuminated when the board is being powered.
When the Power LED is flashing, the board is being
detected or initialized.
In Use Green For each load module slot, the Active LED is
illuminated when a Load Module in a particular slot
is owned by you.
LCD Display
An LCD display is provided on the chassis to indicate the status of the chassis
without an external display device (monitor). The LCD operates in two modes:
• Startup: The LCD displays messages from IxServer to indicate the
operation of IxServer as it initializes.

Specifications
• Run: The LCD display provides chassis information. Information

displayed includes chassis name, IxOS version, IP address, master/
subordinate, and chassis status.
Supported Modules The modules that are supported on the Optixia XM12 are listed in Table 4-3..
Table 4-3. Optixia XM12 Supported Modules
Module SFF - Function

Requires
Adapter
HSE40GETSP1-01 40 and 100 Gigabit Ethernet 1-port, 2-

HSE100GETSP1-01 slot CFP interface (Full feature)
HSE40/100GETSP1-01 dual-speed, 1-port, 2-slot CFP interface
(Full feature)
HSE40GEQSFP1-01 1-port, 1-slot, QFSP interface (Full

feature)
Xcellon-Ultra NP-01 12-port 10/100/1000 Mbps and 1-port

1GE aggregated and 1-port 10GE
aggregated, Base T Ethernet copper,
single-slot load module
Xcellon-Ultra XP-01 12-port 10/100/1000 Mbps and 1-port

Xcellon-Ultra NG-01 12-port 10/100/1000 Mbps and 1-port

ASM1000XMV12X-01 12-port 10/100/1000 Mbps and 1-port

LSM1000XMSP12-01 12-Port Gigabit Ethernet Load Module,

Dual-PHY RJ45 10/100/1000 Mbps and
SFP fiber
LSM1000XMVDC4-01 4/8/12/16-Port Dual-PHY RJ45 10/100/

LSM1000XMVDC-NG 1000 Mbps and SFP fiber. FCoE enabled
LSM1000XMVDC8-01
LSM1000XMVDC12-01
LSM1000XMVDC16-01
LSM1000XMVDC16NG
LSM1000XMS12-01 10/100/1000 Ethernet 12 port module
LSM1000XMSR12-01 10/100/1000 Ethernet 12 port module,

reduced feature set

4 Specifications

Requires
Adapter
LSM10GXM2XP-01 10 Gigabit Ethernet 2 port module,

LSM10GXM2GBT-01 1GHz, 1GB, Extra Performance.
LSM10GXM2S-01 Includes 10GBASE-T version and SFP+
version.
LSM10GXMR2-01 10 Gigabit Ethernet 2 port module,

LSM10GXMR2GBT-01 400MHz, 128MB, single slot, reduced L2/
LSM10GXMR2S-01 3 support with limited L3 routing, Linux
SDK, and L4-7 applications.
Includes 10GBASE-T version and SFP+
version.
LSM10GXM3-01 10 Gigabit Ethernet 3 port module

reduced feature set
LSM10GXM4-01 10 Gigabit Ethernet 4 port single slot, full-

featured load module, 800MHz, 512MB.
Full L2/7 support. Linux SDK, and L4-7
applications.

version.

version.

featured module, 800MHz, 512MB. Full
L2/7 support. Linux SDK, and L4-7
applications.

LSM10GXM8GBT-01 800MHz, 1GB, Extra Performance
version.

version.
NGY-NP8-01 10 Gigabit Application Network

NGY-NP4-01 Processor Load Module, 2/4/8-Port LAN/
NGY-NP2-01 WAN, SFP+ interface

Specifications

Requires
Adapter
AFM1000SP-01 X 10/100/1000 3 port Stream extraction

module
LSM1000XMV4-01 4-port Dual-PHY (RJ45 and SFP) 10/

100/1000 Mbps Ethernet load module
LSM1000XMVR4-01 4-port Dual-PHY (RJ45 and SFP) 10/

100/1000 Mbps Ethernet load module,
reduced performance


reduced performance


reduced performance


reduced performance
CPM1000T8 X Special 10/100/1000 Ethernet load

module
MSM10G1-02 X LAN/WAN/POS Multimode load module
LM100TXS2 X 10/100 Ethernet load module
LM100TXS8 X 8-port multilayer 10/100Mbps Ethernet

load module
LM100TX8 X 8-port 10/100Mbps Ethernet, reduced

features
LM1000STXR4 X 4-port Dual-PHY (RJ45 and SFP) 10/

reduced feature set
LM1000STXS2 X 2-port Dual-PHY (RJ45 and SFP) 10/

100/1000 Mbps Ethernet load module.


4 Specifications

Requires
Adapter
LM1000STXS4-256 X 4-port Dual-PHY (RJ45 and SFP) 10/

100/1000 Mbps Ethernet load module; -
256 version has 256MB of processor
memory per port
LM1000STX2 X 2-port Dual-PHY (RJ45 and SFP) 10/


LM1000TXS4 X 4-port 10/100/1000 Mbps Base-T

Ethernet copper
LM1000TXS4-256 X 4-port 10/100/1000 Mbps Base-T

Ethernet copper;
-256 version has 256MB of processor
memory per port
LM1000TX4 X 4-port 10/100/1000 Mbps Base-T

Ethernet copper, reduced features
LM1000SFPS4 X 4-port Gigabit Ethernet fiber
ALM1000T8 X Special 10/100/1000 Ethernet load

module
ELM1000ST2 X Special 10/100/1000 Ethernet load

module
LSM10G1-01 X 10 Gigabit Ethernet load module
LSM10G1-01M X 10 Gigabit Ethernet load module
LSM10GL1-01 X 10 Gigabit Ethernet load module
LSM1000POE4-02 X 4-port PoE load module
PLM1000T4-PD X Power over Ethernet load module
LM622MR X ATM/POS load module
LM622MR-512 X ATM/POS load module
MSM2.5G1-01 X OC-48c load module

Hot-Swap Procedure

Requires
Adapter
VQM01XM Voice Quality Resource Module performs

real-time processing of speech quality
analysis using PESQ algorithm, on
streams received on ports of the
following load modules:
• Xcellon-Ultra NP-01
• Xcellon-Ultra XP-01
• Xcellon-Ultra NG-01
• ASM1000XMV12X-01
• LSM1000XMV4-01
• LSM1000XMV16-01
• ALM1000TS
• CPM1000TS
See Voice Quality Resource Module on
page 19.
EIM10G4S SFP 10 Gigabit Ethernet LAN Impairment

adapter module, 1-slot with 4-ports of SFP+
interfaces
EIM1G4S SFP 1Gigabit Ethernet LAN Impairment

adapter module, 1-slot with 4-ports of SFP
interfaces
LavaAP40/100GE 2P CFP to This is the dual speed 40GE/100GE

QSFP Ethernet Lava load module with
Accelerated Performance. Each load
module consists of 2-ports and 1-slot with
CFP MSA interfaces. This load module
supports full feature for layer 1 to layer 7
testing
LavaAP40/100GE 2RP CFP to This is the dual speed 40GE/100GE

QSFP Ethernet Lava load module with data
plane support only. It is an economic
alternative to the Accelerated
Performance load module, perfectly
suitable for testing layer 1 to layer 3
applications that does not require routing
protocol emulation. Each load module
consists of 2-ports and 1-slot with CFP
MSA interfaces
Hot-Swap Procedure
Each Optixia XM12 chassis provides the ability of removing and reinstalling a
Load Module without requiring the removal of power from the rest of the chassis.
The process of removing/installing a Load Module does not impact either the
operation of the OS or load modules installed in the chassis.

4 SFF Adapter Module
The hot-swap procedure is detailed in Appendix D, Hot-Swap Procedure.
SFF Adapter Module

The Optixia XM12 adapter module allows legacy modules to be fit into the
XM12 chassis. Figure 4-2 on page 4-12 shows an SFF adapter module.
Figure 4-2. SFF Adapter
A legacy module is inserted into the front of the adapter module and connects to
the pins in the rear of the adapter. The entire assembly can then be inserted into
any Optixia XM12 slot.
Once an adapter module is installed in a chassis, legacy load modules can be hot-
swapped without removing the adapter module from the chassis.
Figure 4-3 on page 4-12 shows an SFF Adapter module with a legacy ATM card.
Figure 4-3. SFF Adapter with ATM Module
Table 4-3 on page 4-7 identifies the modules that can be used with the SFF
Adapter.

Installing Filler Panels

The airflow in an Optixia XM12 chassis is inefficient if load modules are
installed in a few slots and the rest of the chassis is left open. For best cooling
results, filler panels are required. It is required that filler panels are used in
situations where the slots in the chassis are not all in use.
An empty Optixia XM12 chassis includes:

• 5 ea. 1-slot wide XM12 Filler Panel/Air Baffle units (p/n 652-0648-04)
• 1 ea. 6-slot wide XM12 Filler Panel/Air Baffle unit (p/n 652-0353)
Prerequisites for • The technician should use industry-standard grounding techniques, such as
Filler Panel wrist and ankle grounding straps, to prevent damage to electronic
Installation: components on any Ixia Load Modules.
Filler Panel
Installation ESD Caution: Use industry-standard grounding techniques to prevent
Procedure: Electrostatic Damage to the delicate electronic components on the Ixia Load
Modules.
Example: Slide the one-slot filler panel, with the Ixia logo at the top, into the
correct slot. The panel slides in on the slot rails in the chassis. Secure the
faceplate of the filler panel to the chassis with two of the supplied screws.
Caution: Use extreme care to prevent damage to delicate electronic

components on an adjacent load module.
Not using filler panels could cause random failures in port operations or damage
installed modules.
Cooling Fan Speed Control

The XM12 chassis automatically senses the temperature of specified modules
and adjusts the cooling fan speed. If the system and board heat load is low
enough, the cooling fan operates at a lower (quieter) speed.
The following modules have thermal sensors that report temperature readings:
• LSM1000XMS(R)12
• LSM1000XMV(R)16/12/8/4
• LSM10GXM(R)3
• NGY LSM10GXM2/4/8(R), LSM10GXM2/4/8XP, LSM10GXM(R)2/4/8S,
and 10GBASE-T versions LSM10GXM(R)2/4/8GBT-01, NGY-NP2/4/8,
and NGY SFP+ 2/4/8.
• LavaAP40/100GE 2P and LavaAP40/100GE 2RP

4 Cooling Fan Speed Control
Other modules control the fan speed by means of a fixed speed setting. For a list
of supported modules, see Table 4-3 on page 4-7.

XM12 Sound Reducer Installation
XM12 Sound Reducer

Installation
The XM12 Sound Reducer (PN 942-0021) is an optional accessory that installs
on the rear of the XM12 chassis to reduce the sound of the cooling fans. It
reduces the sound by approximately 10 dB.
Refer to the following figure when performing the installation.
Figure 4-4. XM12 Sound Reducer Installation
Note: The chassis should be placed in a horizontal position, in a well-lighted

work area.
1. On the XM12 chassis rear, remove the four shoulder screws that hold the fan
panel in place. Do not remove the fan panel.
2. Attach the sound reducer mounting bracket to the fan panel using the same
four shoulder screws removed in Step 1.
3. Slide the sound reducer onto the mounting bracket.
4. Secure the sound reducer onto the mounting bracket using the four pan-head
screws included in the XM12 Sound Reducer kit.

4 Install XM12 Chassis
Install XM12 Chassis

The following steps describe the procedure of installing an XM12 chassis:
1. On the XM12 chassis rear, remove the four shoulder screws (marked in red
circles) that hold the fan panel in place. Do not remove the fan panel.
2. Put two screws in the rack. Screw them in half way.

3. Put the empty chassis into the rack.
4. Reset the bottom of the empty XM12 chassis on top of the two screws. (refer
to the area marked using red circles in the image below). The entire weight of
the empty XM12 will be supported by these two screws.

Install XM12 Chassis
5. Locate the two holes above that line up with the rack and screw in the other
two screws (preferably the upper hole or one right below that)
6. Screw-in the bottom two screws all the way.
7. Find two or four more screws and screw them in. Do this optionally, and only
if the holes line up.
8. Insert modules (ensure that any empty slots have the blank metal covers in
them as marked in red in the image below).

4 Rack Mount Cautions
Rack Mount Cautions
Caution: If this unit is installed in a Rack Mount, observe the following

precautions.
a: Elevated Operating Ambient Temperature: If installed in a closed or

multi-unit rack assembly, the operating ambient temperature of the rack
environment may be greater than room ambient temperature. Therefore,
consider installing the equipment in an environment that is compatible
with the maximum allowable ambient temperature specified for the
chassis (40° C).
b: Reduced Air Flow: Install the equipment in a rack so that the amount of air
flow required for safe operation of the equipment is not reduced.
c: Mechanical Loading: Mount the equipment in the rack so that a hazardous
condition is not caused due to uneven mechanical loading.
d: Circuit Overloading: Consider the connection of the equipment to the
supply circuit and the effect that overloading of the circuits might have on
overcurrent protection and supply wiring. Pay attention to equipment
nameplate ratings when addressing this concern.
e: Reliable Earthing: Maintain reliable earthing (grounding) of rack-mounted
equipment. Chassis frame should be screwed down to racks to ensure
proper grounding path. In Addition, Pay special attention to supply
connections other than direct connections to the branch circuit (such as use
of power strips).
f: Replacement of the power supply cord must be conducted by a Service
Person. The same type cord and plug configuration shall be utilized.
High Performance Upgrade Kit

A standard XM12 chassis (with two 1.6 kW power supplies) can be converted to
a high performance XM12 (with two 2.0 kW power supplies) using an upgrade
kit that is available from Ixia. Request ‘Field Replaceable Unit, Power Supply
Upgrade Kit’ (FRU-OPTIXIAXM12-01) PN 943-0005.
Note: Standard XM12 chassis that are running more than ten NGY load
modules must have a power supply upgrade kit installed.
We recommend the upgrade kit for existing XM12s with a fully loaded chassis
combined with one or more NGY modules.

Personnel.

High Performance Upgrade Kit
Voice Quality Resource Module

Voice Quality Resource Module (VQM01XM) performs real-time processing of
speech quality analysis using PESQ algorithm, on streams received on ports of
the following load modules:
• ASM1000XMV12X-01
• LSM1000XMV4-01
• LSM1000XMV16-01
• ALM1000TS
• CPM1000TS
The VQM01XM communicates with load modules through the chassis

backplane. A single VQM01XM module can perform PESQ analyses, including
necessary decoding, on up to 300 narrowband streams concurrently in real time.
The PESQ stats are published in Stats View just after the last RTP packet of the
analyzed sequence is received on port.
Statistics and The following real time metrics (Min, Max, and Average values) are provided by
Measurements the Voice Quality Resource Module, depending on the application being run:
• Active level
• Activity factor
• Noise level
• Peak level
• Listening effort (effort required to understand the meaning of spoken
material)
• Listening quality (quality of speech)
These statistics are available in aggregated mode and individual per stream, as
part of ‘VoIP RTP Per Channel’ statistics.

4 High Performance Upgrade Kit

Chapter 5: Optixia XM2 Chassis
5
This chapter provides details about the Optixia XM2 chassis—its specifications
and features.
The Optixia XM2 is the next generation portable chassis that is a combination of
the Optixia architecture with the XM form factor. The 2-slot platform allows for
higher port density load modules in a portable chassis.
The Optixia XM2 Chassis has 2 slots for support of up to 2 single wide load
modules. The Optixia XM2 supports all XM form factor load modules and many
standard form factor load modules with improved system power and cooling. The
Optixia XM2 was specifically designed to allow the hot-swapping of load
modules, without requiring the chassis to be powered down. The Optixia XM2 is
shown in Figure 5-1.
Note: The Optixia XM2 must only be operated in the horizontal position as

on page xxxvii.

Optixia XM2 Chassis
5 Specifications
Figure 5-1. Optixia XM2 Chassis
Modules and the chassis, with improved backplane performance.

provided are:
• Power supplies
• Hard drive
The power supply is accessible from the back of the chassis. The hard drive is
accessible from the bottom of the chassis.
Specifications
XM2 Chassis The Optixia XM2 computer and chassis specifications are contained in
Table 5-1.
CPU Intel Pentium Mobile, 2.0 GHz
instructions.
Memory 2 GB
Disk 250GB SATA Disk HD

USB Drive
DVD Drive is not present in newer versions of XM2
chassis (starting with 941-0003-07 and 941-0023-02).

Optixia XM2 Chassis
Specifications
Physical Note: The Optixia XM2 must only be operated in the

horizontal position as shown in Figure 5-1 on page 5-2.
Load Module Slots 2 XM form factor
Size 4.8 in. H x 20.0 in. W x 14.2 in. D

(12.2cm H x 50.8cm W x 36.1cm D)
Weight (empty) 25 lb (11.34 kg)
Avg. Shipping Wt. 30 lb (13.61 kg)
Environmental
Temperature

published datasheet for each load module.
Humidity
Clearance Sides: 4 in (10 cm); fan openings should be clear of all

cables or other obstructions.
Power 100-240V 60/50Hz 12-6A

USB 1 USB dual type A, 4-pin jack connector
Sync In 4-pin RJ11
Sync Out 4-pin RJ11
Front Panel Indicators See LEDs/LCD Display on page 4.

Optixia XM2 Chassis
5 Specifications

1 LED indicating chassis Power ON

1 LED indicating HDD operation
LCD on front panel to display chassis information
Rear Panel Connectors
Mouse PS/2 6-pin DIN

You must use the supplied Y-cable when using the PS/2
mouse.
Keyboard PS/2 6-pin DIN (with or without the Y-cable)

Port
Serial 1 male DB9 ports
Power Male receptacle (IEC 60320-C13)
Noise Condition:Ixia XM2

Front Back Right Left
Plugged in not started 56 54 57 58
Only CPU Running
On Low Speed 58 56 58 60
On Medium Speed-
On Full Speed 70 67 70 73
LEDs/LCD Display The Optixia XM2 has the following set of front panel LEDs:
Table 5-2. Optixia XM2 LEDs
Active Green For each load module slot, the Active LED is
is owned by you.
Pwr Green For the chassis, indicated Power ON
HDD Green For the chassis, indicates hard disk is active

Optixia XM2 Chassis
Specifications
LCD Display
Supported Modules The modules that are supported on the Optixia XM2 are listed in Table 5-3..

Requires
Adapter
HSE40GETSP1-01 40 and 100 Gigabit Ethernet 1-port, 2-

HSE100GETSP1-01 slot CFP interface (Full feature)
HSE40/100GETSP1-01 dual-speed, 1-port, 2-slot CFP interface
(Full feature)
HSE40GEQSFP1-01 1-port, 1-slot, QFSP interface (Full

feature)
Xcellon-Ultra NP-01 12-port 10/100/1000 Mbps and 1-port

Xcellon-Ultra XP-01 12-port 10/100/1000 Mbps and 1-port

Xcellon-Ultra NG-01 12-port 10/100/1000 Mbps and 1-port

ASM1000XMV12X-01 12-port 10/100/1000 Mbps and 1-port

LSM1000XMSP12-01 12-Port Gigabit Ethernet Load Module,

Dual-PHY RJ45 10/100/1000 Mbps and
SFP fiber
LSM1000XMVDC4-01 4/8/12/16-Port Dual-PHY RJ45 10/100/

LSM1000XMVDC4-NG 1000 Mbps and SFP fiber. FCoE enabled
LSM1000XMVDC8-01
LSM1000XMVDC12-01
LSM1000XMVDC16-01
LSM1000XMVDC16NG

Optixia XM2 Chassis
5 Specifications

Requires
Adapter
LSM1000XMS12-01 10/100/1000 Ethernet 12 port module
LSM1000XMSR12-01 10/100/1000 Ethernet 12 port module,

reduced feature set

version.

version.
LSM10GXM3-01 10 Gigabit Ethernet 3 port module

reduced feature set

featured load module, 800MHz, 512MB.
Full L2/7 support. Linux SDK, and L4-7
applications.

version.

version.

featured module, 800MHz, 512MB. Full
L2/7 support. Linux SDK, and L4-7
applications.

LSM10GXM8GBT-01 800MHz, 1GB, Extra Performance.
version.

Optixia XM2 Chassis
Specifications

Requires
Adapter

version.
NGY-NP8-01 10 Gigabit Application Network

NGY-NP4-01 Processor Load Module, 2/4/8-Port LAN/
NGY-NP2-01 WAN, SFP+ interface
AFM1000SP-01 X 10/100/1000 3 port Stream extraction

module


reduced performance


reduced performance


reduced performance


reduced performance
CPM1000T8 X Special 10/100/1000 Ethernet load

module
MSM10G1-02 X LAN/WAN/POS Multimode load module
LM100TXS2 X 10/100 Ethernet load module
LM100TXS8 X 8-port multilayer 10/100Mbps Ethernet

load module
LM100TX8 X 8-port 10/100Mbps Ethernet, reduced

features

Optixia XM2 Chassis
5 Specifications

Requires
Adapter
LM1000STXR4 X 4-port Dual-PHY (RJ45 and SFP) 10/

reduced feature set

100/1000 Mbps Ethernet load module.

LM1000STXS4-256 X 4-port Dual-PHY (RJ45 and SFP) 10/

100/1000 Mbps Ethernet load module; -
256 version has 256MB of processor
memory per port


LM1000TXS4 X 4-port 10/100/1000 Mbps Base-T

Ethernet copper
LM1000TXS4-256 X 4-port 10/100/1000 Mbps Base-T

Ethernet copper;
-256 version has 256MB of processor
memory per port
LM1000TX4 X 4-port 10/100/1000 Mbps Base-T

Ethernet copper, reduced features
LM1000SFPS4 X 4-port Gigabit Ethernet fiber
ALM1000T8 X Special 10/100/1000 Ethernet load

module
ELM1000ST2 X Special 10/100/1000 Ethernet load

module
LSM10G1-01 X 10 Gigabit Ethernet load module
LSM10G1-01M X 10 Gigabit Ethernet load module
LSM10GL1-01 X 10 Gigabit Ethernet load module
LSM1000POE4-02 X 4-port PoE load module
PLM1000T4-PD X Power over Ethernet load module
LM622MR X ATM/POS load module
LM622MR-512 X ATM/POS load module
MSM2.5G1-01 X OC-48c load module

Optixia XM2 Chassis
Rack Mount Instructions

Requires
Adapter
VQM01XM Voice Quality Resource Module performs

real-time processing of speech quality
analysis using PESQ algorithm, on
streams received on ports of the
following load modules:
• ASM1000XMV12X-01
• LSM1000XMV4-01
• LSM1000XMV16-01
• ALM1000TS
• CPM1000TS
See Voice Quality Resource Module on
page 19.
EIM10G4S SFP 10 Gigabit Ethernet LAN Impairment

adapter module, 1-slot with 4-ports of SFP+
interfaces
EIM1G4S SFP 1Gigabit Ethernet LAN Impairment

adapter module, 1-slot with 4-ports of SFP
interfaces
LavaAP40/100GE 2P CFP to This is the dual speed 40GE/100GE

QSFP Ethernet Lava load module with
Accelerated Performance. Each load
module consists of 2-ports and 1-slot with
CFP MSA interfaces. This load module
supports full feature for layer 1 to layer 7
testing
LavaAP40/100GE 2RP CFP to This is the dual speed 40GE/100GE

QSFP Ethernet Lava load module with data
plane support only. It is an economic
alternative to the Accelerated
Performance load module, perfectly
suitable for testing layer 1 to layer 3
applications that does not require routing
protocol emulation. Each load module
consists of 2-ports and 1-slot with CFP
MSA interfaces
Caution: If this unit is installed in a rack mount, observe the following

precautions:

Optixia XM2 Chassis
5 Rack Mount Instructions

chassis (40° C).
equipment. Pay special attention to supply connections other than direct
connections to the branch circuit (such as use of power strips).
Installing Rack- To mount the Optixia XM2 chassis into an equipment rack, first attach the rack-
Mount Ear Brackets mount ears to the sides of the chassis.
1. If side feet are present (on left side of chassis) remove them. Discard the
rubber feet, but keep the screws. See Figure 5-2 on page 5-11.
2. Reinstall the screws removed in step 1 (into the same holes).
3. Install left-side ear bracket (Ixia PN 652-0688-02) using supplied screws (PN
600-0105). See Figure 5-3 on page 5-11.
4. Install right-side ear bracket (Ixia PN 652-0688-01) using supplied screws
(PN 600-0105). See Figure 5-4 on page 5-12.

Optixia XM2 Chassis
Figure 5-2. Remove Side Feet (If Present)
Remove side feet (if present).

Discard rubber feet, keeping screws.
Reinstall screws into same holes.
Figure 5-3. Install Left Ear Bracket
Install left ear bracket using

supplied screws.

Optixia XM2 Chassis
5 Hot-Swap Procedure
Figure 5-4. Install Right Ear Bracket
Install right ear bracket using

supplied screws.
Hot-Swap Procedure
Each Optixia XM2 chassis provides the ability of removing and reinstalling a
SFF Adapter Module

The Optixia XM adapter module allows legacy modules to be fit into the XM2
chassis. Figure 5-5 on page 5-13 shows an SFF adapter module.

Optixia XM2 Chassis
A legacy module is inserted into the front of the adapter module and connects to
the pins in the rear of the adapter. The entire assembly can then be inserted into
either Optixia XM2 slot.
Once an adapter module is installed in a chassis, legacy load modules can be hot-
swapped without removing the adapter module from the chassis.
Figure 5-6 on page 5-13 shows an SFF Adapter module with a legacy ATM card.
Table 5-3 on page 5-5 identifies the modules that can be used with the SFF
Adapter.

The airflow in an Optixia XM2 chassis can be inefficient if a load module is
installed in one slot and the other is left open. For best cooling results, filler
panels are required. Filler panels must be used in situations where the slots in the
chassis are not all in use.
An empty Optixia XM2 chassis includes:

Optixia XM2 Chassis
5 Installing Filler Panels
• 1 ea. 1 slot wide XM2 Filler Panel/Air Baffle units (p/n 652-0648-04)
Prerequisites for The technician should use industry-standard grounding techniques, such as wrist
Filler Panel and ankle grounding straps, to prevent damage to electronic components on any
Installation: Ixia Load Modules.
Filler Panel
Modules.

Not using filler panels could cause random failures in port operations or damage
installed modules.

Optixia XM2 Chassis
.Cooling Fan Speed Control
. Cooling Fan Speed Control

The XM2 chassis automatically senses the temperature of specified modules and
adjusts the cooling fan speed. If the system and board heat load is low enough,
the cooling fan operates at a lower (quieter) speed.
The following modules have thermal sensors that report temperature readings:
• LSM1000XMS(R)12
• LSM1000XMV(R)16/12/8/4
• LSM10GXM(R)3
• NGY LSM10GXM2/4/8(R), LSM10GXM2/4/8XP, LSM10GXM(R)2/4/8S,
10GBASE-T versions LSM10GXM(R)2/4/8GBT-01, NGY-NP2/4/8, and
NGY SFP+ 2/4/8.
• LavaAP40/100GE 2P and LavaAP40/100GE 2RP
Other modules control the fan speed by means of a fixed speed setting. For a list
of supported modules, see Table 5-3 on page 5-5.

Optixia XM2 Chassis
5 .Cooling Fan Speed Control

Chapter 6: XG12 Chassis
6
This chapter provides details about the XG12 chassis—its specifications and
features.
The XG12 Chassis is the next generation high performance platform capable of
supporting all XM form factor load modules, including full chassis
configurations of the Xcellon load modules. It is a 12-slot chassis with increased
total power capacity available for all load modules and front-to-back airflow
delivery along with increased bandwidth from the CPU to the load modules.
The chassis provides improved modularity and access to the major components
to reduce downtime of a failed chassis and to reduce the probability of needing to
remove a failed chassis from the test environment. The four separate modules
that make up the chassis are shown in Table 6-1.
Table 6-1. XG12 Part Numbers and Modules
Part Number Description
941-0017 XG12, 12-Slot Chassis Frame Module
942-0031 XG12, 12-Slot Chassis Fan Module
942-0032 XG12, 12-Slot Chassis Power Supply Module
942-0033 XG12, 12-Slot Chassis Processor Module
The XG12, shown in Figure 6-1, allows the hot-swapping of load modules,
without requiring the chassis to be powered down. The Processor module for the
XG12 chassis is not hot swappable.
The Processor Module is plugged into the front of the chassis. The power
supplies and fans are accessible from the rear of the chassis. Each of the modular
components is capable of being removed in the field and replaced with minimum
downtime.

XG12 Chassis
6
Figure 6-1. XG12 Chassis
The component modules of the XG12 chassis are shown in the following figure:

XG12 Chassis
Specifications
Specifications
The XG12 chassis specifications are contained in the following tables:.
Table 6-2. XG12 Processor Module Specifications
Processor Module Field replaceable and removable processor card

module with an Intel 2.26 GHz Core™ 2 Duo processor
with 4 GB CPU memory, and 250 GB SATA hard drive
Memory 4GB
Hard Disk Drive 250GB
Operating System Windows 7

XG12 Chassis
6 Specifications
Table 6-2. XG12 Processor Module Specifications
instructions.
Note: The serial number for the Processor Module is

located on module itself. This is used as the overall
chassis serial number.

XG12 Chassis
Specifications
Table 6-3. XG12 Chassis Specifications
Size • 19.0 in. W x 19.21 in. H x 27.2 in. D

• 48.26cm W x 48.79cm H x 69.09cm D
• 11 rackmount units (11RU)
Load Module Slots 12 (compatible with Ixia XM form factor load modules)
Chassis Power The chassis requires three single phase, 200-240VAC,

50/60Hz circuits, each capable of providing 3680 watts.
These circuits must provide protection against over-
currents, short circuits and earth faults for the XG12
chassis. A 20A circuit breaker for each circuit is also
required.
All three power cords must be plugged into their single
phase 200-240VAC, 50Hz/60Hz power sources at the
same time for correct operation of the chassis.
Note: The chassis power supplies are interlocked with
the rear cover which must be installed for them to be
enabled. After removing or installing the rear panel,
ensure thumbscrews have been tightened down with a
'Flat Blade' screwdriver.
Note: The load module power is enabled by the Ixia
server program. If it is not running, the load modules will
not be powered on.
Power Cords All three power cords are required to operate the XG12
chassis power supplies.
Power Cord shipments:
• Ixia provides three power cords that are configured
and rated to meet the specifications of the target
country where the chassis is being installed
• For North American customers, the power cords
have NEMA L6-20P plugs for attachment to the
power source and IEC-60320-C19 connectors that
attach to the XG12 chassis
• For International shipments, the power cords sup-
plied has plugs suitable for each destination country’s
attach to the XG12 chassis
• The XG12 chassis is CE marked and UL™ certified
when using the 200-240VAC power cords supplied
with the chassis. However, these certifications for
the chassis safety approvals are only valid when the
unit is operating from all three 200-240VAC main
power sources

XG12 Chassis
6 Specifications
Chassis Weights Frame:

• 64 lbs. (29.1 kg) empty, component weight
• 97 lbs. (44.1 kg) average shipping weight (with filler
panels)
Fan module:
• 10.2 lbs. (4.63 kg) component weight
• 17.3 lbs. (7.86 kg) average shipping weight
Power Supply module:
• 28 lbs. (12.72 kg) component weight
Processor module:
Warning: Total chassis weight, without any load
modules installed is 104.9 lbs. (47.6 kg). Do not attempt
to lift the fully assembled chassis.
Fan Module Field replaceable chassis fan assembly that is easily

installed and removed.
Air flow Clearance 12 inches is required at the rear of the chassis.

24 inches of clearance is preferred.
Power Supply Module Field replaceable power supply module that is easily
There are three 2825W power supplies in the Power
Supply Module.
Each power supply may be removed or replaced
separately.
Timing Sources Internal clock, synchronized with another Ixia chassis,

GPS AFD-1unit, AFD2 IRIG-B unit or with the Timing
Distribution Module.
Operating temperature 41×F to 104×F, (5×C to 40×C)

Storage temperature 41oF to 122oF, (5oC to 50oC)
Operating Humidity 0% to 85%, non-condensing

XG12 Chassis
Specifications
Storage Humidity 0% to 85%, non-condensing
Noise The XG12 chassis running at maximum fan speed

capacity may produce noise levels up to 87 dB(A). This
is measured per the GR-63-CORE, Issue 1, paragraph
5.6.3 specification. The use of appropriate ear
protection is recommended to protect against hearing
impairment. Consult local health and safety regulations
for recommended maximum exposure levels for noise
and ear protection devices.
Shown below are the maximum XG12 chassis sound

levels measured according to GR-63-CORE, Issue 1,
Paragraph 5.6.3.
• Front: 83.5 dB(A)
• Left Side: 84.2 dB(A)
• Rear: 86.5 dB(A)
• Right Side: 84.4 dB(A)
Hearing Protection: The XG12 chassis generates noise levels above 80

dB(A). Ear protection must be worn. The use of appropriate ear protection is
recommended to protect against hearing impairment. Consult local health and
safety regulations for recommended maximum exposure levels for noise and
ear protection devices.

XG12 Chassis
6 Specifications
Table 6-4. XG12 Chassis controls and indicators
Ethernet Two RJ-45 10/100/1000Mbps Gigabit Ethernet

Management Port.
Sync In Single Sync In jack with a 4-pin RJ11
Sync Out Single Sync Out jack with a 4-pin RJ11
Front Panel Indicators See LEDs/LCD Display.

Power and Active status.
2x16 LCD on front panel indicating chassis information.
Figure 6-2. Safety Features
XG12 chassis installation precautions:

• The chassis should be installed in the rack before installing the power supply
module, fan module and load modules, thereby reducing the weight of the
chassis.

XG12 Chassis
Specifications
• The two lower bolts used to secure the chassis to a rack can be used to hold
the chassis frame in place while securing all of the other bolts (See Figure 6-
2).
• Secure the chassis to rack face with all six bolts. Fully depress power supply
clamps when installing power supply module.
• Secure the power supply module thumb bolt when installing power supply
module.
• Install the rear power supply cover before applying AC power.
Note: After removing or installing this cover, ensure that the thumbscrews
are tightened down with a screwdriver.
• Do not use the chassis without installing the Fan module.
• Do not use the chassis without installing the Processor module.
• Do not leave unused slots open. Use the filler panels to cover the un-used
slots. See Installing Filler Panels for more information.
• Do not block the front air intake.
• A minimum air flow clearance of 12 inches is required. 24 inches of air flow
clearance is preferred at the rear of the chassis.
• Operator intervention may be required to power cycle the XG12 chassis or
restart a software program in the event the XG12 chassis operation is upset or
stopped by electrostatic discharge.
LEDs/LCD Display The XG12 chassis has front panel LEDs for each load module slot.
Table 6-5. XG12 LEDs
Power Green When the Power LED is flashing, the board is being
The Power LED is illuminated when the board is
powered..
In Use Green The Active LED is illuminated when a user has

taken ownership of the load module.
LCD Display

XG12 Chassis
6 Specifications
CPU Slot LED Definitions
The specifications of LEDs for the Processor module and the LEDs above the
Processor module slot are shown in the following table:
ESD Discharge Warning: Operator intervention may be required to power

cycle the unit or restart a software program in the event the unit is upset by
electrostatic discharge.
Table 6-6. LED Specifications
LED Color Description
On the chassis CPU card Slot Yellow The backplane

front face LED is initializing.
Green The backplane

has initialized
Processor Stdby Pwr LED Green 5V Stand-by

module - front power is
panel available
CPU Pwr LED Green CPU Card

power is
available
HDD Act LED
Bkpln Link LED Green PCIe link to

backplane is up
Processor Link LED Green Port has link

module -
Ethernet LEDs
for each
management
port
Act LED Flashes when

port has activity

XG12 Chassis
Specifications
Supported Modules The modules that are supported on the XG12 are listed in the following table.
Table 6-7. Supported Modules
Family Module Function
XM Form Xcellon- • Xcellon-FlexAP10G16S 10 Gigabit Ethernet

Factor (XMFF) Flex™ High LAN Load Module, L2-7 Accelerated Perfor-
load modules density mance, a 1-slot module with 16-ports of
10GbE SFP+ interfaces
products • Xcellon-FlexFE10G16S 10 Gigabit Ether-
net LAN Load Module, L2-3 Full Emulation
Performance, a 1-slot module with 16-ports
of SFP+ interfaces
Xdensity™ Xdensity, XDM10G32S, Ultra-high density, 10-

Ultra-high Gigabit Ethernet load module with 32-ports of
density SFP+ interfaces and L2-3 data plane support
10GbE
Xcellon- • Xcellon-FlexAP10/4016SQ 10/40 Gigabit

Flex™ High Ethernet Accelerated Performance Load
density Module, 16-Ports of SFP+ interfaces and 4-
10GbE and ports of QSFP 40 GE interfaces with full
40 GE performance L1-7 support
products • Xcellon-FlexFE40G4Q 40 Gigabit Ethernet
Full Emulation Load Module, 4-ports of
QSFP 40 GE with L1-3 support
K2 Higher • HSE40GETSP1-01, 40-Gigabit Ethernet

Speed Load Module, 1-port, 2-slots, with the CFP
Ethernet MSA interface
product line • HSE100GETSP1-01, 100- Gigabit Ethernet
Load Module, 1-port, 2-slots, with the CFP
MSA interface
• HSE40/100GETSP1-01 Dual-Speed, 1-port,
2-slots, with CFP MSA interface
• HSE40/100GETSPR1-01, Dual Speed, 40
and 100-Gigabit Data Plane Ethernet Load
Module, 1-port, 2-slots, with the CFP MSA
interface
• HSE40GEQSFP1-01, 40-Gigabit Ethernet
Load Module, 1-port, 1-slot with the QSFP+
pluggable interface for multimode fiber,
850nm, or QSFP+ copper cables
Xcellon Xcellon-Ultra NP-01, Application Network

Ultra™ High Processor Load Module, 1-10G XFP port and/
Performanc or 12-Ports of Dual-PHY (SFP fiber and RJ45
e copper) 10/100/1000 Mbps
Application
Test product
line

XG12 Chassis
6 Specifications
NGY High • LSM10GXMR2/4/8-port, reduced perfor-

Density 10 mance, load modules with the XFP interface
Gigabit • LSM10GXM2/4/8XP-port, Extra perfor-
Ethernet mance, load modules with the XFP interface
product line • LSM10GXM2S/4S/8S-port, Extra perfor-
mance, load modules with the SFP+ inter-
face
• LSM10GXM2S/4S/8S-port, reduced perfor-
mance, load modules with the SFP+ inter-
face
• LSM10GXM2GBT/4GBT/8GBT-port, Extra
performance, load modules with the
10GBASE-T interface
• LSM10GXM2GBT/4GBT/8GBT-port,
reduced performance, load modules with
the 10GBASE-T interface
Fibre • FCMGXM4S-01, 4-Port Fibre Channel Load

Channel Module, with 2Gbps, 4Gbps, and 8Gbps
load module support, SFP+ interface
products • FCMGXM8S-01, 8-Port Fibre Channel Load
Module, with 2Gbps, 4Gbps, and 8Gbps
support, SFP+ interface
ImpairNet • ImpairNet EIM1G4S Gigabit Ethernet LAN

Load Impairment module, 1-slot with 4-ports of
module SFP interfaces
products • ImpairNet EIM10G4S 10 Gigabit Ethernet
LAN Impairment module, 1-slot with 4-ports
of SFP+ interfaces
Voice VQM0001, Resource module, for real time

Quality quality of voice measurement. Must purchased
module with VQM0001-B1, Solution Bundle, Resource
module with IXLOAD-PESQ and IXLOAD-
AUDIO-CODECS software license
NGY NP • NGY-NP8-01, 10 Gigabit Application Net-

High work Processor Load Module, 8-Port LAN/
Density WAN, SFP+ interface
10GbE • NGY-NP4-01, 10 Gigabit Application Net-
Application work Processor Load Module, 4-Port LAN/
Test product WAN, SFP+ interface
line • NGY-NP2-01, 10 Gigabit Application Net-
work Processor Load Module, 2-Port LAN/
WAN, SFP+ interface

XG12 Chassis
Specifications
High • LSM1000XMVDC 4/8/12/16-port, full perfor-

Density mance, load modules with dual-phy SFP
Gigabit fiber and 10/100/1000Mbps RJ45 copper
Ethernet • LSM1000XMVR4/8/12/16-port, reduced
product line performance, load modules with dual-phy
SFP fiber and 10/100/1000Mbps RJ45 cop-
per
• LSM1000XMSP12-01, Gigabit Ethernet,
Load Module, 12-Ports Dual-PHY (SFP
fiber and RJ45 copper) 10/100/1000 Mbps
Standard Form Gigabit • LM100TX8, 100MB Ethernet Load Module,

Factor (SFF) Ethernet 8-Port 10/100Mbps, L2-3 data plane support
load modules TX, TXS, only
for XG12 STX and • LM100TXS8, 10/100Mbps Ethernet Load
chassis STXS Module, 8-Port RJ45, 64MB Port CPU
Note: Requires products memory
944-0007 • LM100TXS2, 10/100Mbps Ethernet Load
Adapter Card Module, 2-Port RJ45, 64MB Port CPU
for XM Chassis memory
installations • LM1000STX4, Gigabit Ethernet Load Mod-
ule, 4-Port Dual-PHY (RJ45 and SFP) 10/
100/1000 Mbps, L2-3 data plane support
only
• LM1000STX2, Gigabit Ethernet Load Mod-
ule, 2-Port Dual-PHY (RJ45 and SFP) 10/
100/1000 Mbps, L2-3 data plane support
only
• LM1000STXS2, Gigabit Ethernet Load
Module, 2-Port Dual-PHY (RJ45 and SFP)
10/100/1000 MbpsLM1000STXS4-256,
Gigabit Ethernet Load Module, 4-Port Dual-
PHY (RJ45 and SFP) 10/100/1000 Mbps
10 Gigabit • LSM10G1-01, 10 Gigabit Ethernet Load

Ethernet Module, 1-Port, Full L2-7 support, requires
LSM interface adapter module
products Interchangeable interface adapter modules
for SFP+, 10GBASE-T, XENPAK, X2, and
CX4 interfaces for the LSM10G1-01
Application • AFM (Auxiliary Function Module):

and AFM1000SP-0
Encryption • ALM (Application Load Module):
Test product ALM1000T8
line • ELM (Encryption Load Module):
ELM1000ST2
• Gigabit Ethernet Content Processing Mod-
ule (CPM), 8-port RJ-45 10/100/1000 Ether-
net

XG12 Chassis
6 Specifications
10-Gigabit • MSM10G1- 10 Gigabit Ethernet OC192

UNIPHY Load Module, 1-port Multi Services Module
and with an XFP interface, supports 10GE LAN/
MacSec WAN and optional OC-192c POS
products • LSM10GMS1-01, 10 Gigabit Ethernet Load
Module, 1-Port, LAN/WAN, Full perfor-
mance and supports 802.1ae Media Access
Control Security (MacSec) L2 security,
including GCM/AES128
Packet over • MSM2.5G1-01, OC48 Load Module, 1-Port

SONET and 2.5G Multi Service Module supporting
ATM OC48c, Supports POS, Full L2-7 support
products • LM622MR, OC3/OC12 ATM/POS, Load
Module, 2-port ATM/Packet over SONET
(POS); Full L2-7 Support. Supports 622 and
155 Mbps data rates
• LM622MR-512, OC3/OC12 ATM/POS,
Load Module, 2-port ATM/Packet over
SONET (POS), Full L2-7 Support. Supports
622 and 155 Mbps data rates, 512MB Port
CPU memory
• OC3OC12PHY, OC3/OC12 ATM/POS
Adapter, Dual-SC optical connector, Single-
port OC-3/OC-12 PHY 1310nm Multimode;
For the LM622MR or LM622MR-512) load
modules
Power over • PLM1000T4-PD (20W), Gigabit Ethernet

Ethernet Load Module, 4-Port PoE, supports 10/100/
(IEEE802.3 1000 Mbps Ethernet, and emulates up to 4
af) powered devices
• LSM1000POE4-02 (30W), Gigabit Ethernet
Load Module, 4-Port PoE, supports 10/100/
1000 Mbps Ethernet, and emulates up to 4
powered devices
Hot-Swap Procedure
Each XG12 chassis provides the ability of removing and reinstalling a load
module without requiring the removal of power from the rest of the chassis. The
process of removing/installing a Load Module does not impact either the
operation of the OS or remaining load modules installed in the chassis.
The hot-swap procedure is detailed in Appendix D Hot-Swap Procedure.
SFF Adapter Module

The XG12 adapter module allows Ixia Standard Form Factor (SFF) load modules
to be adapted into the XG12 chassis. Figure 6-3 shows an SFF adapter module.

XG12 Chassis
Specifications
A SFF load module is inserted into the front of the adapter and connects to the
pins in the rear of the adapter. The entire assembly can then be inserted into any
XG12 chassis slot.
Once an adapter module is installed in a chassis, SFF load modules can be hot-
swapped without removing the SFF load module from the chassis.
Figure 6-4 shows an SFF Adapter module with a legacy ATM card.
Table 6-7 identifies the modules that can be used with the SFF Adapter.

The XG12 chassis automatically monitors and measures the temperature of
installed load modules. The XG12 automatically adjusts the fan speed to
maintain proper cooling.

XG12 Chassis
6 Specifications
Power outage The BIOS on the XG12 is set to Power On after a power failure.
recovery and
Automatic booting The XG12 chassis will start up, boot Windows 7 and automatically login to the
Ixia user account. Anything that is in the Startup folder will also launch..
scenario
Rack Mount Cautions
Caution: If this unit is installed in a network equipment rack, please observe the
following precautions.

chassis (40° C).
flow required for safe operation of the equipment is not reduced. Do not
block the back or the front of the chassis, and leave approximately 12
inches of space, 24 inches preferred, for the back of the unit for proper
ventilation. The air flow clearance should be 12 inches on the front.
c: Mechanical Loading: Mount the chassis so that is it level in the rack and
that a hazardous condition is not caused. Please install all six mounting
bolts.
of power strips).
f: Replacement of the power supply cord must of the same type cord and
plug configuration that was shipped with the unit.

Chapter 7: XGS12 Chassis
7
This chapter provides details about the XGS12 chassis—its specifications and
features.
The XGS12 Chassis is the next generation high performance platform capable of
supporting all XM form factor load modules, including full chassis
configurations of the Xcellon load modules. It is a 12-slot chassis with high-
speed backplane (160 Gbps between each adjacent two cards) designed for
aggregation across load modules.
XGS12 supports both IxLoad and BreakingPoint software applications. The

chassis architecture supports easy setup and management of high scale, multi-
user system. It has a pluggable system controller for chassis management.
Additional applications and load modules will be supported in future software
releases.
The following are the two chassis bundles:

• XGS12-HS, 12-SLOT CHASSIS BUNDLE with XGS12 rack mountable
chassis and High Performance Controller Module. The XGS12-HS bundle
supports both IxLoad and BreakingPoint software applications.
The chassis includes the following:
• Chassis frame assembly, w/ STD SYNC (941-0041)
• High Performance Processor Module (942-0048),
• Fan assembly module (942-0031),
• 6000W power supply module (942-0032)
• Linux & Windows 7 operating systems
This chassis requires selection of a free IxOS software version.
• XGS12, 12-SLOT CHASSIS BUNDLE with XGS12 rack mountable
chassis and Standard Performance Controller Module. The XGS12 bundle
supports IxLoad application only.
The chassis includes the following:
• Chassis frame assembly, w/ STD SYNC (941-0041)
Ixia Platform Reference Guide, Release 6.60 EA P1 7-1

XGS12 Chassis
7
• Standard Processor Module (942-0033)
• Fan assembly module (942-0031)
• 6000W power supply module (942-0032)
• Windows 7 operating system
This chassis requires selection of a free IxOS software version.
The chassis provides improved modularity and access to the major components
to reduce downtime of a failed chassis and to reduce the probability of needing to
remove a failed chassis from the test environment.
The four XGS12-HS chassis modules that are bundled together are shown in
Table 7-1.
Table 7-1. XGS12-HS Part Numbers and Modules
941-0041 Chassis Frame Assembly, with STD SYNC
942-0048 High Performance Processor Module
942-0031 Fan Assembly Module
942-0032 6000W Power Supply Module
The four XGS12-Standard chassis modules that are bundled together are shown
in Table 7-2.
Table 7-2. XGS12-Standard Part Numbers and Modules
941-0041 Chassis Frame Assembly, with STD SYNC
942-0033 Standard Processor Module
942-0031 Fan Assembly Module
942-0032 6000W Power Supply Module
The XGS12 chassis, shown in Figure 7-1, allows the hot-swapping of load
modules, without requiring the chassis to be powered down. The Processor
module for the XGS12 chassis is not hot swappable.
The System Controller is plugged into the front of the chassis, slot 0. The power
supplies and fans are accessible from the rear of the chassis. Each of the modular
components is capable of being removed in the field and replaced with minimum
downtime.
7-2 Ixia Platform Reference Guide, Release 6.60 EA P1

XGS12 Chassis
Figure 7-1. XGS12 Chassis

XGS12 Chassis
7
The component modules of the XGS12 chassis are shown in the following figure:

XGS12 Chassis
Specifications
Specifications
The XGS12 chassis specifications are contained in the following tables.
Table 7-3. XGS12-HS Processor Module Specifications

module with 2 x INTEL Sandy Bridge EP, E5-2658 2.1
GHz processors
Memory 64 GB RAM
Hard Disk Drive Dual 400 GB Solid-State Drives
Operating System Native Linux OS and Win7 VM for IxOS
Other Specs IPMI support
Table 7-4. XGS12-Standard Processor Module Specifications

module with an Intel 2.26 GHz Core™ 2 Duo processor
with 4 GB CPU memory, and 250 GB SATA hard drive
Memory 4GB
Hard Disk Drive 250GB
Operating System Windows 7
instructions.
Note: The serial number for the Processor Module is

located on module itself. This is used as the overall
chassis serial number.

XGS12 Chassis
7 Specifications
Table 7-5. XGS12 Chassis Specifications
Size • 19.0 in. W x 19.21 in. H x 27.2 in. D

• 48.26cm W x 48.79cm H x 69.09cm D
• 11 rackmount units (11RU)
Load Module Slots 12 (compatible with Ixia XM form factor load modules)
Chassis Power The chassis requires three single phase, 200-240VAC,

50/60Hz circuits, each capable of providing 3680 watts.
These circuits must provide protection against over-
currents, short circuits and earth faults for the XGS12
chassis. A 20A circuit breaker for each circuit is also
required.
All three power cords must be plugged into their single
phase 200-240VAC, 50Hz/60Hz power sources at the
same time for correct operation of the chassis.
Note: The chassis power supplies are interlocked with
the rear cover which must be installed for them to be
enabled. After removing or installing the rear panel,
ensure thumbscrews have been tightened down with a
'Flat Blade' screwdriver.
Note: The load module power is enabled by the Ixia
server program. If it is not running, the load modules will
not be powered on.
Power Cords All three power cords are required to operate the
XGS12 chassis power supplies.
Power Cord shipments:
• Ixia provides three power cords that are configured
and rated to meet the specifications of the target
country where the chassis is being installed.
• For North American customers, the power cords
have NEMA L6-20P plugs for attachment to the
attach to the XGS12 chassis.
• For International shipments, the power cords sup-
plied has plugs suitable for each destination country’s
attach to the XGS12 chassis.

XGS12 Chassis
Specifications
Chassis Weights Frame:

• 64 lbs. (29.1 kg) empty, component weight
• 97 lbs. (44.1 kg) average shipping weight (with filler
panels)
Fan module:
Power Supply module:
Processor module (Standard):
Processor module (High Performance
Warning: Total chassis weight, without any load
modules installed is 112.2 lbs. (50.89 kg). Do not
attempt to lift the fully assembled chassis.
Fan Module Field replaceable chassis fan assembly that is easily

Air flow Clearance 12 inches is required at the rear of the chassis.

24 inches of clearance is preferred.
Power Supply Module Field replaceable power supply module that is easily
There are three 2825W power supplies in the Power
Supply Module.
Each power supply may be removed or replaced
separately.
Timing Sources Internal clock, synchronized with another Ixia chassis,

GPS AFD-1unit, AFD2 IRIG-B unit or with the Timing
Distribution Module.
Operating temperature 41×F to 104×F, (5×C to 40×C)

Storage temperature 41oF to 122oF, (5oC to 50oC)
Operating Humidity 0% to 85%, non-condensing

XGS12 Chassis
7 Specifications
Storage Humidity 0% to 85%, non-condensing
Noise The XGS12 chassis running at maximum fan speed

capacity may produce noise levels up to 87 dB(A). This
is measured per the GR-63-CORE, Issue 1, paragraph
5.6.3 specification. The use of appropriate ear
protection is recommended to protect against hearing
impairment. Consult local health and safety regulations
for recommended maximum exposure levels for noise
and ear protection devices.
Shown below are the maximum XGS12 chassis sound

levels measured according to GR-63-CORE, Issue 1,
Paragraph 5.6.3.
• Front: 83.5 dB(A)
• Left Side: 84.2 dB(A)
• Rear: 86.5 dB(A)
• Right Side: 84.4 dB(A)
Hearing Protection: The XGS12 chassis generates noise levels above 80

dB(A). Ear protection must be worn. The use of appropriate ear protection is
recommended to protect against hearing impairment. Consult local health and
safety regulations for recommended maximum exposure levels for noise and
ear protection devices.

XGS12 Chassis
Specifications
Table 7-6. XGS12 Chassis controls and indicators
Ethernet The Standard XGS12 chassis has two RJ-45 10/100/

1000Mbps Gigabit Ethernet Management Port.
The High Performance XGS12 chassis has one RJ-45
1GBaseT/10GBaseT management port, one RJ-45
RS232 serial port.
USB The Standard XGS12 chassis has 4 USB dual type A, 4-

pin jack connectors.
The High Performance XGS12 chassis has two USB
ports. Additionally there are four SFP+ sockets and one
RJ-45 1GBaseT/10GBaseT port that are for future use.
Sync In Single Sync In jack with a 4-pin RJ11
Sync Out Single Sync Out jack with a 4-pin RJ11
Front Panel Indicators See LEDs/LCD Display.

Power and Active status.
2x16 LCD on front panel indicating chassis information.
Figure 7-2. Safety Features

XGS12 Chassis
7 Specifications
XGS12 Chassis XGS12 chassis installation precautions are as follows:

Installation • The chassis should be installed in the rack before installing the power supply
Precautions module, fan module and load modules, thereby reducing the weight of the
chassis.
• The two lower bolts used to secure the chassis to a rack can be used to hold
the chassis frame in place while securing all of the other bolts (See Figure 6-
2).
• Secure the chassis to rack face with all six bolts. Fully depress power supply
clamps when installing power supply module.
• Secure the power supply module thumb bolt when installing power supply
module.
• Install the rear power supply cover before applying AC power.
Note: After removing or installing this cover, ensure that the thumbscrews
are tightened down with a screwdriver.
• Do not use the chassis without installing the Fan module.
• Do not use the chassis without installing the Processor module.
• Do not leave unused slots open. Use the filler panels to cover the un-used
slots. See Installing Filler Panels for more information.
• Do not block the front air intake.
• A minimum air flow clearance of 12 inches is required. 24 inches of air flow
clearance is preferred at the rear of the chassis.
• Operator intervention may be required to power cycle the XGS12 chassis or
restart a software program in the event the XGS12 chassis operation is upset
or stopped by electrostatic discharge.
LEDs/LCD Display The XGS12 chassis has front panel LEDs for each load module slot.
Table 7-7. XGS12 LEDs
Power Green When the Power LED is flashing, the board is being
The Power LED is illuminated when the board is
powered.
In Use Green The Active LED is illuminated when a user has

taken ownership of the load module.

XGS12 Chassis
Specifications
LCD Display
CPU Slot LED Definitions
The specifications of LEDs for the Processor module and the LEDs above the
Processor module slot are shown in the following table:
ESD Discharge Warning: Operator intervention may be required to power

cycle the unit or restart a software program in the event the unit is upset by
electrostatic discharge.
Table 7-8. LED Specifications
LED Color Description
On the chassis CPU card Slot Yellow The backplane

front face LED is initializing.
Green The backplane

has initialized
Processor Stdby Pwr LED Green 5V Stand-by

module - front power is
panel available
CPU Pwr LED Green CPU Card

power is
available
HDD Act LED
Bkpln Link LED Green PCIe link to

backplane is up
Processor Link LED Green Port has link

module - Note: Link and
Ethernet LEDs Activity LEDs
for each port are included for
all Ethernet
ports.
Act LED Flashes when

port has activity

XGS12 Chassis
7 Specifications
Supported Modules The modules that are supported on the XGS12 are listed in the following table.
Part Module Function

Number
944-1200 PerfectStorm PerfectStorm 10GE Fusion 8-port Load Module,

10GE 8-port 10GE 8-port SFP+ with support for IxLoad and
Fusion BreakingPoint software.
(PS10GE8NG) Compatible ONLY with XGS12-HS, 12-SLOT
CHASSIS BUNDLE with XGS12 rack mountable
chassis and High Performance Controller
Module (940-0006).
944-1201 PerfectStorm PerfectStorm 40GE Fusion 2-port Load Module,

40GE 2-port 40GE 2-port QSFP+ with support for IxLoad and
Fusion BreakingPoint software.
(PS40GE2NG) Compatible ONLY with XGS12-HS, 12-SLOT
CHASSIS BUNDLE with XGS12 rack mountable
chassis and High Performance Controller
Module (940-0006).
944-1204 PerfectStorm PerfectStorm 10GE 8-port Load Module, 10GE

10GE 8-port 8-port SFP+ with support for only IxLoad
(PS10GE8) software.
Compatible with XGS12-HS, 12-SLOT CHASSIS
BUNDLE with XGS12 rack mountable chassis
and High Performance Controller Module (940-
0006) and XGS12, 12-SLOT CHASSIS BUNDLE
with XGS12 rack mountable chassis and
Standard Performance Controller Module (940-
0007).
944-1205 PerfectStorm PerfectStorm 40GE 2-port Load Module, 40GE

40GE 2-port 2-port QSFP+ with support for only IxLoad
(PS40GE2) software.
Compatible with XGS12-HS, 12-SLOT CHASSIS
and High Performance Controller Module (940-
0006) and XGS12, 12-SLOT CHASSIS
and Standard Performance Controller Module
(940-0007).

XGS12 Chassis
Specifications
Hot-Swap Procedure
Each XGS12 chassis provides the ability of removing and reinstalling a load
module without requiring the removal of power from the rest of the chassis. The
operation of the OS or remaining load modules installed in the chassis.
The hot-swap procedure is detailed in Appendix D Hot-Swap Procedure.

The XGS12 chassis automatically monitors and measures the temperature of
installed load modules. The XGS12 automatically adjusts the fan speed to
maintain proper cooling.
Power outage The BIOS on the XGS12 is set to Power On after a power failure.
recovery and
Automatic booting The XGS12 chassis will start up, boot Windows 7 and automatically login to the
Ixia user account. Anything that is in the Startup folder will also launch..
scenario
Rack Mount Cautions
Caution: If this unit is installed in a network equipment rack, please observe the
following precautions.
a: Elevated Operating Ambient Temperature: If installed in a closed or multi-

unit rack assembly, the operating ambient temperature of the rack
chassis (40° C).
flow required for safe operation of the equipment is not reduced. Do not
block the back or the front of the chassis, and leave approximately 12
inches of space, 24 inches preferred, for the back of the unit for proper
ventilation. The air flow clearance should be 12 inches on the front.
c: Mechanical Loading: Mount the chassis so that it is level in the rack and
that a hazardous condition is not caused. Please install all six mounting
bolts.

XGS12 Chassis
7 Specifications

proper grounding path. In addition, pay special attention to supply
of power strips).
f: Replacement of the power supply cord must of the same type cord and
plug configuration that was shipped with the unit.

Chapter 8: Optixia X16 Chassis
8
This chapter provides details about Optixia X16 chassis—its specifications and
features.
The Optixia X16 Chassis has 16 slots for support of up to 16 single wide load
modules. The Optixia X16 supports all high power load modules with enhanced
power supplies and cooling. The Optixia X16 was specifically designed to allow
the hot-swapping of modules, without requiring a restart of the chassis. The
Optixia X16 is shown in Figure 8-1.

Personnel.
Figure 8-1. Optixia X16 Chassis

Optixia X16 Chassis
8
Modules and the chassis. Two methods of data throughput improvements is used:
High Speed IxBus and Module to Module data transfer.

provided are:
• Power supplies
• Motherboard and support components (RAM, Hard Drive)
• Backplane power control and interface
Each of the modular components is capable of being removed in the field and
replaced with minimum downtime for the customer.


on page xxxvii.

Optixia X16 Chassis
Specifications
Specifications
X16 Chassis Optixia X16 computer and chassis specifications are contained in Table 8-1.
Table 8-1. Optixia X16 Specifications
CPU Intel Pentium 4, 3.0 GHz
Caution-Battery replacement
instructions.
Memory 2 GB
Disk 80GB Sata Disk

DVD Drive
Physical
Size 17.5"w x 14.5"h x 20.5"d

(44.5cm x 36.8cm x 52.1cm)
Weight (empty) 47lbs (21kg)
Avg. Shipping Wt. 51lbs (23kg)
Environmental
Temperature

modules may require a lower operating temperature; if
this is the case, the operating temperature is specified in
the load module datasheet.
Humidity

cables or other obstructions. Sides: 2 in (5 cm) unless
rack mounted.
Power 100-240V 60/50Hz 16-8A

Optixia X16 Chassis
8 Specifications
Table 8-1. Optixia X16 Specifications
Caution: The X16 unit requires the building installation

to be fitted with a separate circuit fitted with a 20A circuit
breaker.


Mouse PS/2 6-pin DIN for external mouse
Keyboard PS/2 6-pin DIN for external keyboard
Monitor HD-DB15 Super VGA for external monitor
Printer Female DB25 parallel port for external printer

Port
Sync In 4-pin RJ11
Sync Out 4-pin RJ11
Line In/Line Out/Mic 3.5mm mini-TRS stereo jacks
Back Panel Switches/ Power On/Off rocker switch

Connectors
Front Panel Indicators See LEDs/LCD Display on page 5

LCD on front panel to display chassis information
XM2 Noise Spec(Fan Condition:Ixia XM2

db) Front Back Right Left
Only CPU Running
On Medium Speed-

Optixia X16 Chassis
Specifications
LEDs/LCD Display The Optixia X16 has the following set of front panel LEDs, for each load module
slot:
Table 8-2. Optixia X16 LEDs
In Use Green For each load module slot, the In Use LED is
is owned by you.
LCD Display
displayed includes chassis name, IxOS version, IP address, and chassis
status.
Supported Modules The modules that are supported on the Optixia X16 are listed in Table 8-3.
Table 8-3. Optixia X16 Supported Modules
Gigabit Ethernet TXS 10/100/1000 Ethernet Load Modules

family
TXS8 10/100 Ethernet Load Module
ALM1000T8 Special 10/100/1000 Ethernet Load Module
CPM1000T8 Special 10/100/1000 Ethernet Load Module
ELM1000ST2 Special 10/100/1000 Ethernet Load Module
LM622MR ATM/POS Load Module
LSM1000POE4-02 4-port PoE Load Module
2.5G MSM POS OC-48c Load Module
10GE LSM 10 Gigabit Ethernet Load Module, including 10GE

LSM MACSec
10G MSM LAN/WAN/POS Multimode Load Module
PLM1000P4-PD Power over Ethernet Load Module

Optixia X16 Chassis
Hot-Swap Procedure
Each Optixia X16 chassis provides the ability of removing and reinstalling a

The airflow in an Optixia X16 chassis can be inefficient if high density load
modules are installed in a few slots and the rest of the chassis is left open. For
best cooling results, filler panels are required. It is required that filler panels are
used in situations where the slots in the chassis are not all in use.
An empty Optixia X16 chassis includes:

• Three 4-slot wide X16 Filler Panel units (p/n 652-0118-01)
• Two 1-slot wide X16 Filler Panel units (p/n 652-0117-01)
• Screws for attaching the panel faceplates to the chassis
Prerequisites for • The technician should use industry-standard grounding techniques, such as
Filler Panel wrist and ankle grounding straps, to prevent damage to electronic
Installation: components on any Ixia Load Modules.
• The chassis should be placed in a horizontal position, in a well-lighted work
area.
Filler Panel
Modules.
1. To install a 4-slot filler panel:

Example: Slide the 4-slot filler panel, with the Ixia logo at the top, into Slots
1 through 4. The panel slides in on the slot rails in the chassis. Secure the
faceplate of the filler panel to the chassis with 4 of the supplied screws.
2. .To install a 1-slot filler panel:
Example: Slide the 1-slot filler panel, with the Ixia logo at the top, into the
faceplate of the filler panel to the chassis with 2 of the supplied screws.

Optixia X16 Chassis
Rack Mount Cautions

Not using filler panels could cause random failures in port operations or
damage installed modules..
Rack Mount Cautions

precautions:

chassis (40° C).
of power strips).

Optixia X16 Chassis

Chapter 9: Optixia XL10 Chassis
9
This chapter provides details about Optixia XL10 chassis—its specifications and
features.
Optixia XL10 is a highly modular design intended for long-term continuous use
and ease of maintenance. The modular design allows for the replacement of load
modules and power supplies without the need to take the chassis offline. The
number and position of load modules may similarly be changed without taking
the chassis offline. All of the critical components of an Optixia XL10 chassis
may be removed without removing the chassis from its rack mount. Upgrades to
the power supply and processing components are also possible through simple
module interchange while the Optixia XL10 remains rack mounted.
The chassis supports 240 ports of 10/100/1000Mbps modes.
The Optixia XL10 chassis has 10 slots for Optixia XL10 Load Modules. The
Optixia XL10 power is organized with two separate AC inputs which in turn feed
1-4 1200W power supplies. To use Optixia XL10 in a minimal power
configuration, power supplies number 1 and 2 are installed for use with up to 5
blades. Power supplies number 3 and 4 are installed for use with all 10 blades.


Personnel.
The Optixia XL10 is shown in Figure 9-1 on page 9-2.

on page xxxvii.

Optixia XL10 Chassis
9
Figure 9-1. Optixia XL10 Chassis


9 Specifications
Specifications
XL10 Chassis Optixia XL10 computer and chassis specifications are contained in Table 9-1.
Table 9-1. Optixia XL10 Specifications
CPU Intel Celeron 1.2 GHz
instructions.
Memory 2 GB
Disk IDE disk: 20 GB, removable
CD-ROM Integrated CD-ROM drive
Physical
Size 17.5”w x 35.5”h x 22.5”d

(44.5cm x 90.5cm x 57.5cm)
Avg. Shipping Wt. 160lbs (72.5kg)
Environmental
Temperature

Humidity
Power Line cord 1: 200-240V 60/50Hz 15A

Line cord 2: 200-240V 60/50Hz 15A
Note: Both power cords must be connected to the AC
power source to provide sufficient power to the chassis.

Specifications

Caution: The chassis’ safety approvals (UL and CE) are

only valid when the unit is operating from 200-240VAC
mains.

Clearance Front and Rear: 4 in (10 cm); fan openings should be

clear of all cables or other obstructions.
Sides: 2 in (5 cm) unless rack mounted
Front Panel Indicators System Power (behind sliding door)

LEDs:
System
System Ready
System Fault
System Temperature
CPU Power
Standby Power
GPS Enabled*
Time Stamp 1, 2, 3*
Satellite Lock*
Arm
OK
Lock
Sync
Master
Ext. Sync.
CDROM
* = optional features
Mouse PS/2 6-pin DIN with or without Y-connector, for external

mouse
Keyboard PS/2 6-pin DIN with or without Y-connector, for external

keyboard
Video HD-DB15 Super VGA for external monitor
Parallel (Printer) Female DB25 parallel port for external printer
10/100 Ethernet RJ-45 10/100Mbps

Fully integrated PC with 10/100 NIC.
Com 1 (Serial) 1 male DB9 serial port

Sync In 4-pin RJ11
Sync Out 4-pin RJ11
Trigger In BNC
Power 2 male receptacles (IEC 60320-C19)

Only CPU Running
On Medium Speed-
Supported Modules The modules that are supported on the Optixia XL10 are listed in Table 9-2..
Table 9-2. Optixia XL10 Supported Modules

Requires
Adapter
OLM1000STXS24 24-Port Dual-PHY (RJ45 and SFP) 10/

100/1000 Mbps Ethernet Optixia XL10
full-featured Load Module (does not
include transceivers)
OLM1000STX24 24-Port Dual-PHY (RJ45 and SFP) 10/

100/1000 Ethernet Optixia XL10 Load
Module (does not include SFP
transceivers); Reduced features - NO
support for routing protocols, Linux SDK,
and L4-7 applications
LSM10GXL6-02 6-port 10GE LAN/WAN, single slot, full

featured load module for Optixia XL10.
Supports routing/bridging protocols,
Linux SDK, and L4-7 applications.
Requires 6 XFP transceivers (not
included - options are either 948-0003
(XFP-850), XFP-1310, or XFP-1550)
Hot-Swap Procedure
Each Optixia XL10 chassis provides the ability of removing and reinstalling a


The airflow in an Optixia XL10 chassis can be inefficient if a load module is
installed in one slot and the other is left open. For best cooling results, filler
panels are required. Filler panels must be used in situations where the slots in the
chassis are not all in use.
An empty Optixia XL10 chassis includes:

• 7 ea. 1 slot wide XL10 Filler Panel/Air Baffle units (p/n 652-0517)
Prerequisites for The technician should use industry-standard grounding techniques, such as wrist
Filler Panel and ankle grounding straps, to prevent damage to electronic components on any
Installation: Ixia Load Modules.
Filler Panel
Modules.

Not using baffles could cause random failures in port operations or damage
installed modules.
Rack Mount Cautions

precautions:

chassis (40° C).


Chapter 10: IXIA 1600T Chassis
10
This chapter provides details about Ixia 1600T chassis—its specifications and
features.
The Ixia 1600T Chassis has 16 slots for support of up to 16 single wide load
modules, or eight double-wide load modules. The Ixia 1600T supports all high
power load modules with enhanced power supplies and cooling. The Ixia 1600T
was specifically designed to support OC-192c and 10 Gigabit Ethernet load
modules. The Ixia 1600T is shown in the following figure.
Figure 10-1. Ixia 1600T Chassis

IXIA 1600T Chassis
10

on page xxxvii.

IXIA 1600T Chassis
Specifications
Specifications
1600T Chassis Ixia 1600T computer and chassis specifications are contained in the following
table.
Table 10-1. IXIA 1600T Specifications
CPU Intel Celeron 1.2Ghz
instructions.
Memory 1 GB
Disk IDE disk: 20 GB
Physical
Size 17.5”w x 15.7”h x 20.4”d

(44.5cm x 39.9cm x 52cm)
Avg. Shipping Wt. 51lbs (23kg)
Environmental
Temperature

Humidity

cables or other obstructions. Bottom: 1 in (2.5cm). Top
and sides: none.
Power 100-240V 60/50Hz 16-10A

IXIA 1600T Chassis
10 Specifications
Fuse 250V 20A Fast Acting
Back Panel Switches On/Off rocker switch
Front Panel Indicators Power, Standby, Master, External Clock

See LEDs on page 5.
Back Panel Connectors
Power Male receptacle (IEC 60320-C19).
Mouse PS/2 6-pin DIN with or without Y-connector, for external

mouse.
Keyboard PS/2 6-pin DIN with or without Y-connector, for external

keyboard.
Monitor HD-DB15 Super VGA for external monitor.
Printer Female DB25 parallel port for external printer.
Ethernet RJ-45 10/100Mbps
USB 2 USB dual type A, 4-pin jack connectors.
Sync In 4-pin RJ11
Sync Out 4-pin RJ11
Audio Line In 3 3.5mm mini-TRS

Line Out
Mic In
Trigger In BNC

Only CPU Running
On Medium Speed-

IXIA 1600T Chassis
LEDs
LEDs
The IXIA 1600T has the following set of front panel LEDs:
Table 10-2. IXIA 1600T LEDs
Power Green The power LED is illuminated when the chassis is

using power.
Standby Yellow The standby LED indicates that the chassis is in

standby mode. Standby mode is defined as: the
chassis is plugged into an active power outlet, the
chassis power block switch is active (or ‘On’), and
the system power is not on. Pressing the front panel
Power On/Off button enables system power and
start the system.
Master Green This LED is illuminated during chassis power up.

After IxServer is loaded, the LED is only illuminated
when the chassis is enabled in Master Mode.
Master Mode indicates that the chassis operates
based on its local system clock and it is not
dependent upon any external synchronization. In a
chassis chain this LED is illuminated on the first
chassis in the chain. All other chassis downstream
receive their clock from the Master chassis and
therefore does not illuminate this LED.
External Sync Green This LED is illuminated during chassis power up.
After the IxServer load the LED is only illuminated
when the chassis detects an external
synchronization clock. The external synchronization
clock is used to synchronize to an adjacent chassis
when defining a chassis chain. This LED does not
indicate that a chassis is a device in a chain. It only
indicates that a clock signal has been detected on
the line.

When using the IXIA 1600T for fewer than eight OC192 modules, it is best to
redirect the airflow to the installed load modules to optimize operating
conditions. Consequently, 1-slot and 4-slot 1600T cover plates have been
designed to redirect the airflow to the installed load modules from empty slots.
The following components are included with each IXIA 1600T:

• Three 4-slot wide 1600T Filler Panel units (p/n 652-0118)
• Two 1-slot wide 1600T Filler Panel units (p/n 652-0117)
• Screws for attaching the panel faceplates to the chassis

IXIA 1600T Chassis
10 Installing Filler Panels
Prerequisites for
Filler Panel Warning: Power to the chassis must be OFF.
Installation:
• The technician should use industry-standard grounding techniques, such as
wrist and ankle grounding straps, to prevent damage to electronic
components on any Ixia Load Modules.
• The chassis should be placed in a horizontal position, in a well-lighted work
area.
• The Load Module(s) must have been previously installed, per the instructions
before application of power.
Insert one or more OC192 or 10GE modules into the chassis. Other load modules
may be installed at any location
Table 10-3. Slot Preferences for Installing Multiple OC192 Load Modules
Module Slots Filler Panels Required
1st 11 & 12 (3) 4-slot and (2) 1-slot
2nd 5&6 (3) 4-slot
3rd 8&9 (2) 4-slot and (2) 1-slot
4th 14 & 15 (1) 4-slot and (4) 1-slot
5th 2&3 (6) 1-slot
6th 1&2 (4) 1-slot (shift the 5th module to slots 3 & 4)
7th 7&8 (2) 1-slot (shift the 3rd module to slots 9 & 10)
8th 13 & 14 None (shift the 4th module to slots 15 & 16)
The filler panels are required when there are empty slots in the chassis. However,
any other Ixia load modules, such as 10/100, Gigabit, OC12/3c, and OC48c, can
be installed in the chassis, alongside the OC192c load modules. First, insert the
OC192c load modules into the respective slots, as described in the second
column of the table above. Second, install any other load modules in any empty
slots. Last, fill the remaining slots with the filler panels.
Filler Panel
Modules.
To install a filler panel, do the following:

1. Verify that the chassis is powered OFF and the power cable is unplugged.
2. To install a 4-slot filler panel, slide the 4-slot filler panel, with the Ixia logo at
the top, into Slots 1 through 4, or as indicated in the Slot Preference table
above.

IXIA 1600T Chassis
Rack Mount Cautions
The panel slides in on the slot rails in the chassis.

3. Secure the faceplate of the filler panel to the chassis with 4 of the supplied
screws.
4. To install a 1-slot filler panel, slide the 1-slot filler panel, with the Ixia logo at
the top, into the correct slot, per the Slot Preference table above.
The panel slides in on the slot rails in the chassis.
5. Secure the faceplate of the filler panel to the chassis with 2 of the supplied
screws.

Not using filler panels could cause random failures in port operations or
damage installed modules..
Rack Mount Cautions

precautions:

chassis (40° C).

IXIA 1600T Chassis

Chapter 11: IXIA 400T Chassis
11
This chapter provides details about Ixia 400T chassis—its specifications and
features.
The IXIA 400T is shown in Figure 11-1. The IXIA 400T chassis has 4 slots for
Ixia Load Modules, but may also be used to support the high-powered load
modules, including all OC192 and 10GE modules. The IXIA 400T Chassis is
specifically designed to accommodate up to 2 OC192/10GE Load Modules and
up to 3 TXS8, TXS4 or SFPS4 Load Modules. It has an enhanced power supply,
providing more than twice the power of the original IXIA 400T. Additional
cooling fans have been added to the 400T to meet the requirements of the high-
powered modules.
Note: The Ixia 400T must only be operated in the horizontal position as shown
in Figure 11-1.
Figure 11-1. Ixia 400T Chassis

IXIA 400T Chassis
11
Warning: In order to prevent accidental injury to personnel, do not leave

unused SFP (or SFP+) ports on load modules uncovered. When transceivers
are not installed, end caps must be used. For details, see Use End Caps on
Open Ports on page xxxvii.

IXIA 400T Chassis
Specifications
Specifications
400T Chassis The computer specifications are contained in the following table.
CPU Intel Celeron 1.2Ghz
instructions.
Memory 512 MB
Disk IDE disk: 250 GB
Physical
Load Module Slots 4
Size 10.25”w x 5.75”h x 16”d (26.1cm x 14.6cm x 40.6cm)
Weight (empty) 10lbs (4.5kg)
Environmental
Temperature

Humidity

Sides: 2 in (5 cm) unless rack mounted.

IXIA 400T Chassis
11 Use of Filler Panels
Power 100-240 V 60/50 Hz 4-2 A
Note: The CPU monitors each card’s power

requirements and refrains from applying power to the
backplane if the card’s required load would cause the
total power to exceed 350W.
Fuse 4.0A 250V Time Lag
Front Panel Switches Momentary Standby Power push button
Back Panel Switches Power On/Off rocker switch
Front Panel Indicators Power, Master, External Clock
Keyboard/Mouse PS/2 6-pin DIN with Y-connector, for external mouse

and/or keyboard
mouse.
Ethernet 2 each RJ-45 10/100Mbps Fully integrated PC with 10/

100 NIC
Com 2 1 male DB9 serial port
Sync In 4-pin RJ11
Sync Out 4-pin RJ11
Trigger In BNC connector

Only CPU Running
On Medium Speed-
Use of Filler Panels

Proper cooling of the cards in the Ixia 400T requires that the Ixia 400T chassis is
always mounted in a horizontal position and that the filler panels are installed in
the unused slots. High powered cards available for use in the Ixia 400T chassis

IXIA 400T Chassis
Rack Mount Cautions
include all variants of the OC192 load modules, all variants of the 10GE load
modules, and all variants of the ALM1000T8. Refer to Installing Filler Panels
on page 5 for instructions on the installation of filler panels.
Rack Mount Cautions

precautions:

chassis (40° C).

IXIA 400T Chassis

Chapter 12: IXIA 400T v2 Chassis
12
This chapter provides details about Ixia 400 chassis—its specifications and
features.
The IXIA 400 is shown in the following figure. The IXIA 400 chassis has 4 slots
for Ixia Load Modules, but may also be used to support the high-powered load
modules, including all OC192 and 10GE modules. The IXIA 400 Chassis is
specifically designed to accommodate up to 2 OC192/10GE Load Modules and
up to 3 TXS8, TXS4 or SFPS4 Load Modules.
Note: The Ixia 400T v2 must only be operated in the horizontal position as
Figure 12-1. Ixia 400T v2 Chassis - Front View

IXIA 400T v2 Chassis
12
Figure 12-2. Ixia 400T v2 Chassis - Rear View


Specifications
Specifications
400T v2 Chassis The computer specifications are contained in the following table.
Table 12-1. IXIA 400T v2 Specifications
CPU Intel Atom N455 1.66Ghz
instructions.
Memory 2 GB
Disk SATA HDD.250 GB
Operating System Windows 7 Ultimate
Physical
Load Module Slots 4
Size 10.25”w x 5.75”h x 18.5”d (26.1cm x 14.6cm x 47cm)
Weight (empty) 13.65lbs (6.2kg)
Avg. Shipping Wt. 19.65lbs (8.9kg)
Environmental
Temperature

Humidity


12 Use of Filler Panels
Table 12-1. IXIA 400T v2 Specifications
Power 100-240 V 60/50 Hz 4-2 A
Note: The CPU monitors each card’s power

requirements and refrains from applying power to the
backplane if the card’s required load would cause the
total power to exceed 350W.
Front Panel Switches Momentary Standby Power push button
Front Panel Indicators Power, Master, External Clock
Keyboard/Mouse PS/2 6-pin DIN with Y-connector, for external mouse

and/or keyboard
mouse.
Ethernet 1 RJ-45 10/100/1000Base-T Interface
Com 2 male DB9 Serial Port
USB 4 USB dual type A (2 Front Mounted and 2 Rear

Mounted), 4-pin jack connectors
Sync In 4-pin RJ11
Sync Out 4-pin RJ11

Only CPU Running
On Medium Speed-
Use of Filler Panels

Proper cooling of the cards in the Ixia 400T v2 requires that the Ixia 400T v2
chassis is always mounted in a horizontal position and that the filler panels are
installed in the unused slots. High powered cards available for use in the Ixia
400T v2 chassis include all variants of the OC192 load modules, all variants of
the 10GE load modules, and all variants of the ALM1000T8. Refer to Installing
Filler Panels on page 5 for instructions on the installation of filler panels.

Rack Mount Cautions
Rack Mount Cautions

precautions:

chassis (40° C).


Chapter 13: IXIA 250 Chassis
13
This chapter provides details about Ixia 250 chassis—its specifications and
features.
The IXIA 250 is a Field Service Unit (FSU) chassis with a built-in 10/100/1000
port and an additional two slots for Ixia Load Modules, which may be high-
powered modules. The IXIA 250 is shown in the following figure.
Note: The Ixia 250 must only be operated in the horizontal position as shown in
Figure 13-1.
Figure 13-1. IXIA 250 Chassis

IXIA 250 Chassis
13 Operation
Operation
Setup The IXIA 250 incorporates an adjustable support, shown collapsed in Figure 13-
2 and extended in Figure 13-3.
Figure 13-2. IXIA 250 Integrated Support (Collapsed)
Figure 13-3. IXIA 250 Integrated Support (Extended)
The support is extended by placing your thumbs at the upper left and right
corners of the cutouts and pushing down as shown in Figure 13-4. Ensure that the
stand is stable in one of its available locking positions.

IXIA 250 Chassis
Operation
Figure 13-4. IXIA 250 Integrated Support Operation
The keyboard is released by pressing on the button at the top of the chassis, as
Figure 13-5. IXIA 250 Keyboard Release
Unfold the keyboard and press down on the hinge until it lies flat.
Caution: The Ixia 250 can only be operated in the horizontal position shown in

IXIA 250 Chassis
13 Operation

Figure 13-6. IXIA 250 Keyboard
Caution: Do not block the back or sides of the chassis, and leave
approximately two inches of space around the unit for proper ventilation.
Power is applied to the unit by plugging it in and toggling the ‘1/0’ switch as

IXIA 250 Chassis
Operation
Figure 13-7. IXIA 250 Power
This applies power to the chassis, but does not turn on the computer within. The
separate Standby switch must be pressed, as shown in Figure 13-8. This may also
be used to put the computer into standby mode at a later time. Should the IXIA
250 experience a power failure, it does not automatically start the operating
system.

IXIA 250 Chassis
13 Operation
Figure 13-8. IXIA 250 Standby Switch
Computer The computer on the IXIA 250 is operated as any other computer system running
Operation Windows 2000 Server. The keyboard is used for all typed input. The touchpad at
the bottom of the keyboard, as shown in the following figure, is used to position
the cursor and click the left and right mouse buttons.
Figure 13-9. IXIA 250 Keyboard and Touchpad
LCD Brightness
Right button
Touchpad
Left button
Right button
Move around the touchpad, following the cursor on the screen. Use the buttons
under the touchpad as you would use the left and right mouse buttons on a

IXIA 250 Chassis
Operation
mouse. Double tapping on the touchpad is equivalent to a double-mouse click.

Pressing in the shaded area at the top-right of the touchpad is equivalent to a right
mouse button click.
The intensity of the LCD screen is controlled by the slide switch at the upper
right corner of the keyboard.
In addition to the use of the touchpad, an external mouse may be connected to the
Keyboard/Mouse port at the back of the chassis. Furthermore, the LCD screen is
touch sensitive and may be used as an alternative to the touchpad or mouse.
Touching the screen is equivalent to pressing and holding the left mouse button
at that point and taking your finger off the screen is equivalent to releasing the
mouse button.
An external keyboard may be attached to the Keyboard/Mouse port at the back of

the chassis. When both an external mouse and keyboard are required, they may
be attached with the use of the supplied ‘Y’ adapter, as shown in Figure 13-10.
Attach the keyboard and mouse to either connector.
Figure 13-10.IXIA 250 Keyboard/Mouse ‘Y’ Adapter
Keyboard or
mouse connectors
The rear panel of the IXIA 250 contains additional connectors for external
devices. This is shown in Figure 13-12 and further explained in Table 13-1.
Table 13-1. IXIA 250 Computer Connections
Connector Usage
Keyboard/Mouse Used to connect an external mouse and/or keyboard.
VGA An external monitor may be attached to this connector.

The monitor must have at least a 1024 x 768 resolution.
Parallel Port May be used for an external printer.

IXIA 250 Chassis
13 Operation
Table 13-1. IXIA 250 Computer Connections

COM1 May be used to communicate with an external serial
device.
10/100 Management Two 10/100 Ethernet ports may be used for remote
management of the chassis. Three LEDs are provided:
Activity, Link, and 10/100. Link and 10/100 glow a steady
green when link has been established and the port is
operating in 100 Mbps mode, respectively. The Activity
light blinks green as data is sent or received.

IXIA 250 Chassis
Operation
A floppy drive and access to the hard disk is provided on the left rear of the
chassis, as shown in the following figure.
Figure 13-11. IXIA 250 Floppy and Hard Drive Access
Hard Disk
Floppy
CDMA
Antenna
Input
Test Operation Device testing may be accomplished using the built-in port or by plugging in
additional Ixia load modules. The following figure shows two additional boards
in an IXIA 250 chassis.
Figure 13-12.IXIA 250 with Additional Load Modules
Card #1
Card #3
Card #2
The IXIA 250 accepts any two single-wide or one double-wide load modules.
See the remaining chapters of this manual for a discussion of available load
modules. When using Ixia software to access the load modules, the cards are
numbered as shown in Figure 13-12. That is, the built-in port is card number 1,
the lower card in the chassis is card number 2, and the card above that is card
number 3.
When the IXIA 250 is ordered with the Gigabit-only option, then one of two
optional connectors may be attached to the Test Port. The connectors are either
copper (RJ-45) or fibre optic SFP module. The module to which the connector is

IXIA 250 Chassis
13 Operation
attached is hot-swappable. Merely press the release tabs on either side of the
connector and pull out the connector.
Sync-in/Sync-out connectors are provided to daisy chain the IXIA 250 with other
chassis.
When the CDMA option is installed, an appropriate antenna should be attached

to the rear panel, as shown in Figure 13-11. Refer to Ixia 100 Chassis for a full
discussion of the use of the CDMA feature. LEDs are provided to indicate the
status of the CDMA time lock; the aforementioned chapter has a discussion of
their interpretation.

IXIA 250 Chassis
Specifications
Specifications
Ixia 250 Chassis Ixia 250 computer and chassis specifications are contained in Table 13-2.
Table 13-2. IXIA 250 Specifications
CPU Intel Celeron 850Mhz
instructions.
Memory 512 MB
Disk Removable IDE disk: 20 GB
Operating System Windows 2000 Server
Keyboard Integrated keyboard
Mouse Integrated touchpad
Integrated Display 12.1 inch TFT active matrix LCD panel

• 1024 x 768 resolution
• Touchscreen
• Adjustable brightness
Physical
Load Module Slots 2-accepts single or double-wide module
Size 17.5” x 11.25” x 7” (44.5cm x 28.5cm x 17.8cm)
Weight (empty) 20 lb. (9 kg)
Avg. Shipping Wt. 22 lb. (10 kg)
Environmental
Temperature

Humidity

IXIA 250 Chassis
13 Specifications
Table 13-2. IXIA 250 Specifications

Power 100-240V 60/50Hz 3.0-1.5A
Fuse 3.15A 250V Fast Acting
Front Panel Switches LCD brightness slide switch (on built-in keyboard)
Momentary Power-On switch
Back Panel Indicators Power, Master, External Clock, CDMA status
Keyboard/Mouse 1 PS/2 6-pin DIN connector with Y-connector cable, for

external mouse and/or keyboard
Ethernet RJ-45 10/100Mbps dual port
Com 1 Male DB9 serial port
Test port RJ-45 or SFP
Sync In/Out two 4-pin RJ11 (provided by Ixia)
CDMA Antenna BNC connector (only on 250-CDMA)

Only CPU Running
On Medium Speed-

IXIA 250 Chassis
Specifications
Test System The test system specifications are contained in Table 13-3 on page 13-13.
Table 13-3. IXIA 250 Test System Specifications
Built-in Load One port of LM1000TXS4 load module with 10/100/1000

Module capability. Refer to Chapter 21, IXIA 10/100/1000 Load
Modules for a description of the port characteristics. Load
module must be ordered with a copper or SFP connector.
This port is available as card 1, port 1 in Ixia software.
Load Module Slots Any of Ixia’s single-wide or double-wide modules may be

used. Load modules are hot-swappable. These cards are
available as cards 2 and 3 in Ixia software.
CDMA Optional CDMA clock synchronization module.

IXIA 250 Chassis
13 Specifications

Chapter 14: Ixia 100 Chassis
14
Ixia 100
The IXIA 100 provides the means for accurate worldwide timing using GPS or
CDMA antenna inputs. The IXIA 100 chassis has 1 slot for an Ixia Load Module
and includes either an integral GPS unit (IXIA 100 GPS) or CDMA unit (IXIA
100 CDMA). The IXIA 100 is shown in the following figure.
Figure 14-1. Ixia 100 Chassis
The IXIA 100 with integrated Global Positioning System (GPS) or Code-
Division Multiple Access (CDMA) technology is designed for distributed end-to-
end measurements of key metrics, including point-to-point latency and jitter.

Ixia 100 Chassis
14 IXIA 100 Specifications
IXIA 100 Specifications

The IXIA 100 chassis specifications are contained in the following table.
Table 14-1. Ixia 100 Chassis Specifications
Physical
Load Module Slots 1
Size 17.5”w x 1.75”h x 20.15”d (44.5cm x 4.5cm x 38.1cm)
Weight 14lbs (6.4kg)
Environmental
Temperature

Humidity
Power 100-240V 60/50Hz 1.5-0.75A
Front Panel Indicators Power, Satellite Lock, Time Stamp
Mouse & Keyboard PS/2 6-pin DIN
Ethernet RJ-45 10/100Mbps

Fully integrated PC with 10/100 NIC
Com 1 2 male DB9 ports

Ixia 100 Chassis
Rack Mount Cautions
Table 14-1. Ixia 100 Chassis Specifications

Only CPU Running
On Medium Speed-
Rack Mount Cautions

precautions:

chassis (40° C).

Ixia 100 Chassis

Chapter 15: IXIA Impairment Load
15 Modules
This chapter provides specification and details of Ethernet Impairment Modules

(EIM). This family of load modules consist of the following cards:
• EIM1G4S—1G Ethernet LAN Impairment Module
• EIM10G4S—10G Ethernet LAN Impairment Module
• EIM40G2Q—40G Ethernet LAN Impairment Module
The Impairment load modules have a single-slot form factor and are inserted into
a high-density XM2 or XM12 chassis to provide 2 to 12 modules per chassis
configuration. The load modules offer 4x1GE, 4x10GE, or 2x40GE Ethernet
interfaces that can emulate 64, 32, or 8 unidirectional network clouds
respectively.
The high density 1GE, 10GE, and 40GE Impairment test modules are ideal for
emulating real-life network impairments. The modules can emulate a WAN
environment and simulate network characteristics, such as delay, delay variation,
and impairments, such as packet loss, duplication, and re-ordering.
EIMs support the Impairment feature in IxNetwork and IxLoad applications that
provides a quick and easy way to set up impairments, across multiple emulated
WAN links. Using EIM ports, IxNetwork and IxLoad is capable of generating a
number of impairments, for example packet drops, latency, or packet re-ordering,
which replicates real-life WAN traversal conditions, whereby packet flows are
impaired in different modes when traversing a network.
The EIM40G2Q load module is not supported in IxLoad.
For more information on the Impairment feature, refer to chapter on ‘Network

Impairment’ in the IxNetwork Help and IxLoad Help.
The key features of EIM are as follows:

• High density 1GE, 10GE, and 40GE load modules
• Realistic, high-scale WAN emulation
• Hardware-based impairment generation

IXIA Impairment Load Modules
15
• Integration with traffic generation, protocol emulation and analysis
• Scale port counts with high port density
• Simulate ultra-high latency: 500ms on each 40GE link, 600ms on each 10GE
link and 6 sec. on each 1GE link at line rate traffic
• Leverage a single hardware chassis for traffic load modules
• Use IxNetwork for integrated traffic generation and impairment
• Quickly configure traffic flows and apply impairment
• Automate tests
• Analyze measurements with StatViewer interface
• Achieve 1GE, 10GE and 40GE line-rate impairment on all frame sizes (64 to
9180 byte frames) with no packet loss
The 1/10GE EIM load module is shown in the following figure:
Figure 15-1. ImpairNetTM 1/10GE Load Module
The 40GE EIM load module is shown in the following figure:
Figure 15-2. ImpairNetTM 40GE Load Module

Part Numbers
Part Numbers
The part numbers are shown in Table 15-1.
Table 15-1. Part Numbers for Ethernet Impairment Load Module
Model Number Part Number Description
EIM1G4S 944-1081 ImpairNet EIM1G4S Gigabit

Ethernet LAN Impairment
module, 1-slot with 4-ports of
SFP interfaces.
For XM12-02 (P/N 941-
0009) High Performance
and XM2-02 (P/N 941-0003)
portable chassis, SFP
transceivers are required.
Options for transceivers
include SFP-LX, SFP-SX,
and SFP-CU (for RJ45
copper support).
EIM10G4S 944-1082 ImpairNet EIM10G4S 10

Gigabit Ethernet LAN
Impairment module, 1-slot
with 4-ports of SFP+
interfaces.
For XM12-02 (P/N 941-
and XM2-02 (P/N 941-0003)
portable chassis, SFP+
transceivers are required.
Options for transceivers
include 10GBASE-SR/SW
(948-0013), or 10GBASE-
LR/LW (948-0014).
EIM40G2Q 944-1083 ImpairNet EIM40G2Q 40

Gigabit Ethernet LAN
Impairment module, 1-slot
with 2-ports of QSFP+
interfaces.
For XM12-02 (P/N 941-
and XM2-02 (P/N 941-0003)
portable chassis QSFP+
40GBASE-SR4 transceivers
(P/N 948-0028) is required.

15 Specifications
Specifications
The load module specifications are described in the following table:
Table 15-2. Ethernet Impairment Load Module 1/10GE Specifications
Feature Specification
Number of ports per module 4-ports
Number of chassis slots per 1

module
Chassis support The EIM load modules are supported on

the following XM2 chassis:
• 941-0003-01 Rev. G and later version
• 941-0003-02 Rev. C and later version
• 941-0003-03 Rev. F and later version
• 941-0003-04 Rev. G and later version
• 941-0003-05 Rev. G or later version
• 941-0003-06 Rev. A or later version
Note: Earlier models of XM2 chassis
require factory upgrade for compatibility
with EIM load modules.
Module support Up to 12 modules per XM12 Chassis

Up to 2 modules per XM2 Chassis
SFP+ transceiver support Available with 1GE SFP, Electrical SFP

RJ45 1GE Transceiver, and 10GE SFP+
Ethernet interface options

Specifications
Traffic Selection and Impairment • 16 traffic classifiers per link, total of 64

Configuration unidirectional classifiers per module for
granular traffic classification
• 16 impairment profiles per link, total of
64 profiles per module for granular ser-
vice class emulation
• Emulate 32 unidirectional or 16 bidirec-
tional network clouds per port pair
• Emulate 64 unidirectional or 32 bidirec-
tional network clouds per module
• Easy-to-use, packet-analyzer-based
selection interface
• Traffic classifier support for numerous
protocols and applications like bridging,
routing, carrier Ethernet, broadband,
MPLS, IPv6, and miscellaneous applica-
tion-layer protocols
• Multiple service/traffic class emulation
through independent and unique impair-
ments per profile
• Emulate network cloud aggregation
using mask and match support for
packet classifiers
• Support for 8x16 bit frame matchers for
each traffic classifier

15 Specifications
Supported Impairments • Delay up to 600ms at 10GE, and up to

1.2s per module by cascading ports
• Delay up to 6s at 1GE, and up to 12s per
module by cascading ports
• Packet Delay Variation using a selection
of probability distributions
• Delay resolution of 1µs
• Emulate SLA validation by using normal/
Gaussian, exponential, uniform, and
custom probability distribution for delay
variations
• Packet drop at rates of up to 100% in
clusters up to 65535 packets
• Reorder packets at rates of up to 50% in
clusters up to 255 packets
• Packet duplication at a rate up to 100%
in clusters up to 65535 packets by creat-
ing up to 31 copies of each packet
• Emulation of network/transmission/pro-
cessing error conditions through bit error
insertion for L2-L7 protocols
• WAN forwarding error emulation
• Ethernet FCS correction
• Emulation of DS3, OC3, DS1, DS0, E1,
E3, and cable modem link speeds using
rate limiting
Multi-core processor technology Yes
Operating temperature range 41°F to 86°F (5°C to 30°C), ambient air
Minimum Delay • 1G: 300us

• 10G: 30us
Table 15-3. EIM Load Module 40GE Specification
Interface Options QSFP+
Ports/Module 1 port pair per module
Module/Chassis • 1 module per XM2 chassis

• Up to 6 modules per XM12 chassis

Specifications
Table 15-3. EIM Load Module 40GE Specification
Traffic Selection and • 16 traffic classifiers per up/down link, total of 32 uni-
Impairment directional classifiers per module for granular traffic
Configuration classification
• 4 impairment profiles per link, total of 8 profiles per
module for granular service class emulation
• Emulates 32 unidirectional or 16 bidirectional net-
work clouds per port pair
• Emulate 64 unidirectional or 32 bidirectional net-
work clouds per module
• Easy to use packet analyzer based selection inter-
face
• Traffic classifier support for numerous protocols and
applications like bridging, Routing, Carrier Ethernet,
Broadband, MPLS, IPv6, and miscellaneous appli-
cation-layer protocols
• Multiple service/traffic class emulation through inde-
pendent and unique impairments per profile
• Emulate network cloud aggregation using mask and
match support for packet classifiers
• Real-time preview of classifier match on live traffic
• Support for 8x16 bit frame matchers for each traffic
classifier
Supported • Delay up to 500ms at 40GE, and up to 1s per mod-

Impairments ule by cascading ports
• Delay resolution of 1µs
• Emulate SLA validation by using normal/Gaussian,
exponential, uniform, and custom probability distri-
bution for delay variations
• Packet drop at rates of up to 100% in clusters up to
65535 packets
• Reorder packets at rates of up to 50% in clusters up
to 255 packets
• Packet duplication at a rate up to 100% in clusters
up to 65535 packets by creating up to 31 copies of
each packet
• WAN forwarding error emulation
• Ethernet FCS correction
• Emulation of DS3, OC3, DS1, DS0, E1, E3, and
cable modem link speeds using rate limiting.

15 Specifications

Chapter 16: IXIA Xcellon-Lava Load
16 Modules
This chapter provides specification and feature details of the Xcellon-Lava 40/
100 Gigabit Ethernet load modules. This family of load modules consist of the
following 3-port cards:
• LavaAP40/100GE 2P
• LavaAP40/100GE 2RP
• LavaAP40/100GE 2P-NG
The Xcellon-Lava 40/100-Gigabit Ethernet load modules belong to the family of

Ixia’s High Speed Ethernet (HSE) products. These load modules combine the
advantages of the Xcellon architecture and provide the highest 40GE and 100GE
port densities. Lava load modules can be used for testing layer 1 to layer 7
applications. They are supported by Ixia's test applications, including IxNetwork
and IxLoad.
Xcellon-Lava load modules are used for testing high-density data center 40
Gigabit Ethernet (40GbE) and 100 Gigabit Ethernet (100GbE) network
equipments. 40GbE and 100GbE are high-speed computer network standards
developed by the IEEE 802.3ba. Lava load modules extends the 802.3 protocol to
operating speeds of 40 Gbps and 100 Gbps in order to provide greater bandwidth
while maintaining maximum compatibility with the installed base of 802.3
interfaces.
Xcellon-Lava load modules are compatible with Ixia's XG12™, XM12, and
XM2 chassis, and a broad range of Ethernet interfaces, allowing real-world, layer
1 to layer 7 test and measurement in a single chassis.
LavaAP40/100GE 2P-NG load module has capabilities similar to LavaAP40/

100GE 2P and includes N2X support.

IXIA Xcellon-Lava Load Modules
16
The Xcellon-Lava load module is shown in the following figure:
Figure 16-1. Xcellon-Lava Load Module
LED function table The LED functions are described in the following tables.
Table 16-1. Xcellon-Lava LED Ports
LED Label Usage
Link Green if Ethernet link is up (established) or the port is in a

forced Link Up state, OFF (no color) if link is down. Link
may be down due to no signal or no PCS lock.
Tx Active Green indicates that Tx is active and frames being sent; red
indicates Tx is paused; off indicates Tx is not active.
Rx Active Green indicates that Rx is active and frames being

received; red indicates Rx is paused; off indicates Rx is not
active.
Rx/Error Green indicates valid Rx frames are being received; red

indicates error frames being received; off indicates no
frames being received.
Pwr Good Green when power is on, red if power fault occurs.

CFP adapter CFP adapter diagrams are as follows:.

diagrams
The CFP-to-QSFP+ Interface adapter module is shown in the following figure:
Figure 16-2. CFP-to-QSFP+ Interface adapter
The CFP-to-QSFP+ Dual-Port Interface adapter module is shown in the following

figure:
Figure 16-3. CFP-to-QSFP+ Dual-Port Interface adapter

16
The CFP to CXP-Adapter is shown in the following figure:
Figure 16-4. CFP-to-CXP-Adapter.

Part Numbers
Part Numbers
Table 16-2. Part Numbers for Xcellon-Lava Load Module and Supported
Adapters
Lava AP40/ 944-1067 This is the dual speed 40GE/

100GE 2P 100GE Ethernet Lava load
module with Accelerated
Performance. Each load
module consists of 2-ports
and 1-slot with CFP MSA
interfaces. This load module
supports full feature for layer
1 to layer 7 testing.
Note: If XM12-01 (941-
0002) chassis is used with
this load module, the FRU-
OPTIXIAXM12-01 (943-
0005) power supply upgrade
kit must be installed.
Lava AP40/ 944-1068 This is the dual speed 40GE/

100GE 2RP 100GE Ethernet Lava load
module with data plane
support only. It is an
economic alternative to the
Accelerated Performance
load module, perfectly
suitable for testing layer 1 to
layer 3 applications that
does not require routing
protocol emulation. Each
load module consists of 2-
ports and 1-slot with CFP
MSA interfaces.
Note: If XM12-01 (941-
0002) chassis is used with
this load module, the FRU-

16 Part Numbers
Adapters
CFP-to-QSFP+ 948-0022 A pluggable unit that

Interface Adapter converts an Ixia CFP MSA
Module port interface to 1-port of the
pluggable 40 GE QSFP+ for
multimode fiber or copper
cable assemblies or
standalone transceivers.
The adapter is compatible
with the HSE40GETSP1-01,
40-Gigabit Ethernet load
module (944-0069), HSE40/
100GETSP1-01, 40/100-
Gigabit Ethernet, dual-
speed, load module (944-
0091), HSE40/
100GETSPR1-01, 40/100-
speed, Data Plane Ethernet
load module (944-0099),
Xcellon-Lava 40/100-Gigabit
Ethernet, Accelerated
Performance, load module
(944-1067) and Xcellon-
Lava 40/100-Gigabit
Ethernet, Reduced
Performance load module
(944-1068).

Part Numbers
Adapters
CFP-to-QSFP+ 948-0023 A pluggable, 2-port unit that

Dual-Port converts an Ixia Xcellon-
Interface Adapter Lava CFP MSA port
Module interface to 2-ports of
pluggable 40 GE QSFP+ for
fiber or copper cable
assemblies or standalone
transceivers. The adapter is
compatible with the Xcellon-
Lava 40/100-Gigabit
(944-1067) and Xcellon-
Lava 40/100-Gigabit
Ethernet, Reduced
(944-1068). Both load
modules accept up to two of
the Dual Interface Adapter
Modules.
CFP-to-CXP 948-0027 A pluggable unit that

Interface Adapter converts an Ixia CFP MSA
Module port interface to 1-port of the
pluggable 100 GE CXP for
multimode fiber or copper
cable assemblies or
standalone transceivers.
The adapter is compatible
with the HSE100GETSP1-
01 100- Gigabit Ethernet
load module (944-0070),
HSE40/100GETSP1-01, 40/
100-Gigabit Ethernet, dual-
speed, load module (944-
0091), HSE40/
100GETSPR1-01, 40/100-
speed, Data Plane load
module (944-0099), Xcellon-
Lava 40/100-Gigabit
(944-1067) and the Xcellon-
Lava 40/100-Gigabit
Ethernet, Reduced
Performance load module
(944-1068).

16 Part Numbers
CFP Adapter usage Table 16-3. The CFP Slot #1 specification

for Xcellon-Lava
Adapter CFP Mode Speed Port(s) Available
Ethernet Load Present
Modules
948-0027 Single 100G/40G Port 1
Dual N/A Not Supported
948-0022 Single 40G Port #1
Dual 40G Port #3
948-0023 Single 40G Top port: Unavailable

Bottom port: Port #1
Dual 40G Top port: Port #4

Table 16-4. The CFP Slot #2 specification
Adapter CFP Mode Speed Port(s) Available

Present
948-0027 Single 100G/40G Port 2
Dual 40G Not Supported
948-0022 Single 40G Port #2
Dual 40G Port #5
948-0023 Single 40G Top port: Unavailable

Dual 40G Top port: Port #6

CFP Mode
The CFP mode can be of two types:

• Single Port Operation: CFP provides one port of 40G or 100G. Speed is
selected in a Port Property.
• Dual Port Operation: CFP provides two ports of 40G, when using CFP-to-
QSFP+ Dual-Port Interface Adapter.
Dual Port Operations has following limitations:

• BERT functionality not available
• Capture buffer is half the capacity of Single Port Operation.
• Max Streams supported = 256
• “No CRC” option not supported
• Value List memory is half that of Single Port Operation

Specifications
• TX Flow sequence memory is half that of Single Port Operation

• Sequence Checking memory is half that of Single Port Operation
• PPM adjustment is per CFP (pair of QSFP+ ports)
• DCE support not available at this time
• Front panel LEDs not functional
Specifications
The load module specifications are described in the following table:
Table 16-5. Xcellon-Lava Ethernet Load Module Specifications
Feature LavaAP40/100GE 2P LavaAP40/100GE 2RP
Load Modules LavaAP40/100GE 2P LavaAP40/100GE 2RP
Number of ports per module 2-100GE CFP MSA 2-100GE CFP MSA
2-40GE CFP MSA or (4) 40GE 2-40GE CFP MSA or (4) 40GE
QSFP+ [with interface adapter] QSFP+ [with interface adapter]
Number of chassis slots per 1 1

module
Chassis Support XG12™ XG12™

XM12 XM12
XM2 XM2
Maximum ports per chassis XG12™: (24) 100GE CFP MSA XG12™: (24) 100GE CFP MSA
and (48) and (48)
40GE QSFP+ 40GE QSFP+
XM12: (20) 100GE CFP MSA XM12: (20) 100GE CFP MSA
and (40) 40GE QSFP+ and (40) 40GE QSFP+
XM2: (2) 100GE CFP MSA and XM2: (2) 100GE CFP MSA and
(4) (4)
40GE QSFP+ 40GE QSFP+
Capture buffer size 1.4 GB 1.4 GB
Streams per port 256.

Note: In packet stream (sequential) or advanced stream
(interleaved) mode, each stream definition can generate millions
of unique traffic flows. In the Data Center mode, the number of
transmit streams is 256.
Latency Standard resolution in packet No

timestamp is
20ns. User selectable high
resolution in packet timestamp
is 2.5ns

16 Specifications
Transceiver support • CFP MSA 1.4, pluggable

• SFF-8436 QSFP+, pluggable fiber/copper cables (passive/
active) with adapter
CFP interface adapters • 1-port, CFP-to-QSFP+ for 40GE

• 2-port, CFP-to-QSFP+ for 40GE
• 1-port CFP-to-CXP for 100GE operation
Hardware capture buffer per 1.4 GB

port
Interface protocols 40-Gigabit Ethernet 40GBASE-R and 100-Gigabit Ethernet

100GBASE-R as per IEEE802.3ba-2010 standard
Layer 2/3 routing protocol The following protocols are supported in LavaAP40/100GE 2P Full
emulation Performance load module:
• MPLS: RSVP-TE, RSVP-TE P2MP, LDP, PWE, L3 MPLS VPN,
6VP, MPLSTP
• Routing: RIP, RIPng, OSPFv2/v3, ISISv4/v6, EIGRP,
EIGRPv6, BGP-4,BGP+
• VPLS: 6PE, BGP Auto-Discovery with LDP FEC 129 Support,
VPLS-LDP, VPLS-BGP
• IP Multicast: IGMPv1/v2/v3, MLDv1/v2, PIM-SM/SSM, PIM-
BSR, Multicast VPN, VPNv6
• Switching: STP/RSTP, MSTP, PVST+/RPVST+, LACP
• Carrier Ethernet: Link OAM, CFM, Service OAM, PBT/PBB-
TE, SyncE, IEEE 1588v2 PTP
• High-Availability: BFD
The following Host/Client protocols are supported in LavaAP40/
100GE2 RP Full Performance load module:
• ARP
• NDP
• ICMP (PING)
• IPv4
• IPv6
Layer 4-7 application traffic This is suppoted only in LavaAP40/100GE 2P Accelerated

testing Performance load module.
Transmit flows per port Billions Billions

(sequential values)
Transmit flows per port 1 million 1 million
Trackable receive flows per port 1 million 1 million
Table UDF entries 512K

Note: Comprehensive packet editing function for emulating large
numbers of sophisticated flows is supported by Xcellon-Lava load
module. Entries of up to 256 bytes, using lists of values can be
specified and placed at designated offsets within a stream. Each
list consists of an offset, a size and a list of values in a table
format.

Specifications
Packet flow statistics Xcellon-Lava load module tracks over 1 million flows.
Transmit engine The Xcellon-Lava load module supports wire-speed packet

generation with timestamps, sequence numbers, data integrity
signature, and packet group signatures.
Receive engine The Xcellon-Lava load module supports wire-speed packet

filtering, capturing, realtime latency and inter-arrival time for each
packet group, data Integrity, and sequence checking.
User Defined Field (UDF) The Xcellon-Lava load module supports the UDF features of fixed,
Features increment or decrement by user-defined step, value list, cascade,
random, and chained.
Filters The Xcellon-Lava load module uses 48-bit source/destination

address, 2x128-bit userdefinable pattern and offset, frame length
range, CRC error, data integrity error, sequence checking error
(small, big, reverse)
Error Generation CRC (good/bad/none), undersize, oversize
Transmit Line Clock Adjustment Xcellon-Lava load module has the ability to adjust the parts per
million (ppm) line frequency over a range of -100 ppm to +100
ppm.
Latency measurements Standard resolution in packet timestamp is 20ns.

User selectable high resolution in packet timestamp is 2.5ns
Layer 1 BERT capability The Xcellon-Lava load module supports the following BERT
features on both 40 GE and 100 GE speeds:
• User selected PRBS pattern for each PCS Lane
• User can select from a wide range of PRBS data patterns to be
transmitted with the ability to invert the patterns
• Send single, continuous, and exponentially controlled amounts
of error injection
• Wide range of statistics, including Pattern Lock, Pattern Trans-
mitted, Pattern Received, Total Number of Bits Sent and
Received, Total Number of Errors Sent and Received, Bit Error
Ratio (BER), and Number of Mismatched 1's and 0's.
• Lane Stats Grouping per lambda for SMF and MMF 40GE and
100GE based on IEEE 802.3ba defined physical medium
dependent (PMD).

16 Specifications
40/100 GE Physical Coding The Xcellon-Lava load module supports IEEE 802.3ba compliant
Sublayer (PCS) test features PCS transmit and receive side test capabilities. The supported
PCS features are as follows:
• Per PCS lane, transmit lane mapping: Supports all combina-
tion of PCS lane mapping: Default, Increment, Decrement,
Random, and Custom.
• Per PCS lane, skew insertion capability: User selectable
from zero up to 3 microseconds of PCS Lane skew insertion on
the transmit side.
• Per PCS lane, lane marker, or lane marker and payload
error injections: User selectable ability to inject errors into the
PCS Lane Marker and simultaneously into PCS Lane Marker
and Payload fields. This includes the ability to inject sync bit
errors into the Lane Marker and Payload. User can control the
PCS lane, number or errors, period count and manage the rep-
etition of the injected errors.
• Per PCS lane, receive lanes statistics: PCS Sync Header
and Lane Marker Lock, Lane Marker mapping, Relative lane
deskew up to 52 microseconds for 40GE and 104 microsec-
onds for 100GE, Sync Header and PCS Lane Marker Error
counters, indicators for Loss of Synch Header and Lane
Marker, and BIP8 errors.
IPv4, IPv6, UDP, TCP Xcellon-Lava load module supports hardware checksum
checksum generation and verification.
Frame length controls Xcellon-Lava load module supports fixed, random, weighted
random, or increment by user-defined step, random, and weighted
random.
Preamble view Xcellon-Lava load module allows to select to view and edit the
preamble contents.
Link Fault Signaling Xcellon-Lava load module generates local and remote faults with
controls for the number of faults and order of faults, plus the ability
to select the option to have the transmit port ignore link faults from
a remote link partner.
Operating temperature range 41°F to 95°F (5°C to 35°C), ambient air

Note: When an Xcellon-Lava load module is installed in an XM12,
XM2, or XG12 chassis, the maximum operating temperature of the
chassis is 35°C (ambient air).
Load module dimensions 16.0" (L) x 12.0" (W) x 1.3" (H)

406mm (L) x 305mm (W) x 33mm (H)
Weight Module only: 9.8 lbs (4.45 kg)

Shipping: 12.0 lbs (5.45 kg)
ppm Adjust range +/-100ppm +/-100ppm
ppm Adjust port/card Card Card
Trigger out No No
External Clock In(Frequence) No No

Specifications
External Clock Out No No
Ambient Operating 5-40 5-40

Temperature Range (C)
Timestamp - Resolution 20ns 20ns
Timestamp - High Resolution No No
Timestamp - End of Frame No No

Instrumentation
Timestamp - Floating No No
Intrumentation
IEEE802.3x Flow control No No
WAN No No
Streams per port 16 16
Number of streams in 16 16
Advanced Scheduler Mode
(Data Center Mode)
Transicevier Intrinsic Latency No No

Calibration
Intrinsic Latency Yes Yes
Data Integrity Yes Yes
Auto Instrumentation Yes Yes
Preamble - Changeable No No
Content
Preamble - Byte Count Mode No No
Preamble - SFD Detect Mode Yes Yes
Preamble - Cisco CDL Mode No No
The Ixia application support for Lava AP40/100GE 2P and Lava AP40/100GE
2RP is provided in the following table:
Table 16-6. Xcellon-Lava Application Support
Lava AP40/100GE 2P Lava AP40/100GE 2RP
IxExplorer IxExplorer
IxNetwork IxNetwork
IxAutomate IxAutomate
TCL API TCL API

16 Updated enumerated types in API for LavaAP support in IxN2X
Updated enumerated types in

API for LavaAP support in IxN2X
AgtPortSelector ModuleType
• AGT_CARD_TWOPORT_100GBASE_R
• AGT_CARD_TWOPORT_40GBASE_R
AgtPortSelector Personality
Please note that the port speed is selected by the personality

• AGT_PERSONALITY_100GBASE_R
• AGT_PERSONALITY_40GBASE_R
AgtEthernetLinkMode
• AGT_ETHERNET_LINK_40G_FULLDUPLEX,
• AGT_ETHERNET_LINK_100G_FULLDUPLEX
EAgtPluginMediaType
• AGT_PLUGIN_CXP
• AGT_PLUGIN_QSFP
• AGT_PLUGIN_CFP
EAgtPcsStatus
• AGT_PCS_STATUS_SYNC_ERROR
• AGT_PCS_STATUS_ILLEGAL_CODE
• AGT_PCS_STATUS_ILLEGAL_IDLE
• AGT_PCS_STATUS_EXTENDED_ERROR_MASK
• AGT_PCS_STATUS_ALL_ERROR_MASK
Note: The Xcellon-Lava AP is a CFP module. CFP-to-CXP and CFP-to-QSFP

adaptors are available separately.

2x40 QSFP adaptor
2x40 QSFP adaptor

N2X only supports single port mode, even with the dual-port adaptors. In a
vertical orientation, it is the bottom port in each adaptor that is supported by N2X
and the upper port is inactive.
Single Port Mode: Single and Dual CFP-to-QSFP+ adapter module

configurations

16 2x40 QSFP adaptor

Chapter 17: IXIA Power over
17 Ethernet Load Modules
This chapter provides details about Power over Ethernet (PoE) Load Modules—
specifications and features.
Ixia’s Power over Ethernet (PoE) Load Modules are used to test Power Sourcing
Equipment (PSE) in accordance with IEEE Std 802.3af. The PoE Load Modules
emulate Powered Devices (PDs) with programmable characteristics, and include
data acquisition circuits for measuring voltage, current, and time.
The PoE Load Modules are intended to be used in conjunction with Ixia’s line of
Ethernet traffic generator/analyzer load modules. The PoE Load Modules handle
the detection, classification, and power loading aspects of 802.3af, while
passively conveying Ethernet data between the PSE and the traffic generator/
analyzer load modules.
Ixia offers two models of PoE Load Modules. The basic model (PLM1000T4-
PD) is rated for 20 Watts continuous power dissipation per port. The advanced
module (LSM1000POE4-02) is rated for 30 Watts per port, and has several
additional advanced features, including configurable ZAC2 settings. Both
models include 4 independent and isolated PD emulators on a single-slot load
module.

IXIA Power over Ethernet Load Modules
17 Part Numbers
Figure 17-1. PLM1000T4-PD Load Module
Figure 17-2. PLM1000T4-PD Load Module Face Plate
Part Numbers
The part numbers are shown in Table 17-1. Items without a Price List Name
entry are no longer available.
Table 17-1. Part Numbers for Gigabit Modules
Load Module Price List Name Description
PLM1000T4-PD PLM1000T4-PD 4-port PoE Load Module, 20W/Port,

emulating Powered Devices.
LSM1000POE4-02 LSM1000POE4-02 4-port PoE Load Module, 30W/Port,

emulating Powered Devices.

Specifications
Specifications
The load module specifications are contained in the following table. The
limitations of -3, Layer 2/3, and Layer 7 cards are discussed in Ixia Load
Modules on page 1-5.
Table 17-2. PoE Load Module Specifications
PLM1000T4-PD LSM1000POE4-02
# ports 4 4
Data Rate 10/100/1000 Base-T 10/100/1000 Base-T
Connector RJ-45 RJ-45
R_SIG Range/ 2–45k/200 Ohms 2–45k/200 Ohms

Resolution
C_SIG Range/ 0–220nF/10nf 0–220nF/10nf

Resolution
I_CLASS Range –60mA 0–60mA
I_CLASS 0.25mA 0.25mA

Resolution/
Accuracy
DC MPS Range/ 0–60mA/0.25mA 0–60mA/0.25mA

Resolution
AC MPS R_PD Zac1: 10–45k/200 Ohms Zac1: 10–45k/200 Ohms

Range/Resolution Zac2: Fixed/ > 4 Ohms Zac2: 200–1200k/ 8k
AC MPS C_PD 0–220nF/10nF 0–220nF/10nF

Range/Resolution
Data Acquisition 5MSPS 5MSPS

Sample Rate
Data Acquisition 0–64V/10 bits/0.5% 0–64V/10 bits/0.5%

Voltage Range/
Resolution/
Accuracy
Data Acquisition 0–1024mA/10 bits/0.5% 0–1024mA/10 bits/ 0.5%

Current Range/
Resolution/
Accuracy
Data Acquisition 100mW 100mW

Power Readback
Accuracy
Maximum 20W per port 30W per port

Continuous Power
Load Modes Constant Current (CC) Constant Current (CC)

Power (CP) Power (CP)

17 Port LEDs
Table 17-2. PoE Load Module Specifications
PLM1000T4-PD LSM1000POE4-02
Pulse Modes Single, Continuous, Inrush Single, Continuous, Inrush

(CC only)
Programmable Amplitude, Width, Duty, Amplitude, Width, Duty,

Pulse Parameters Slew Rate Slew Rate
Port LEDs
Each port incorporates a set of LEDs, as described in Table 17-3 on page 17-4.
Table 17-3. PoE Load Module Port LEDs
LED Label Usage
Detect When green, indicates the PSE is in the detection process.
Classify When green, indicates the PSE is in the classification process.
Powered When green, indicates the PSE is powering the emulated PD.
Fault When red, indicates the PSE has performed an illegal operation.
PoE disconnects under a fault condition until the PSE resets.
Test Monitor Output Ports

There are two test monitor output ports on each PoE module, used to measure the
power/current into a selected port. These ports can be used in conjunction with an
oscilloscope to view input characteristics. The ports have the following scale:
Table 17-4. Test Monitor Ports
Factor Measurement
DC Measurements 62.5mV out/Volts input
DC Current 4mV out/ mA Input
AC Measurement .05V out/Volts Input (Planned Feature)
Statistics
Statistics counters for PoE cards may be found in Table B-6 on page B-9.

Chapter 18: XOTN Chassis Unit
18
This chapter provides details about the XOTN chassis—its specifications and
features.
The XOTN chassis unit is a part of the XOTN system. This system allows you to
use IxNetwork protocols and scalable data plane test capabilities to test Optical
Transport Network (OTN) devices. It provides flexible mapping of Ethernet
frames to different OTN rates and structures according to ITU-T G.709.
Each system comprises an XOTN chassis unit, a USB cable, power cord, CFPs,
and software. The XOTN ports are configured and managed by the IxNetwork
application and can be used with any XM K2 load module (40Gb/s or 100Gb/s).
To test OTN devices, you must connect the XOTN chassis unit to a load module
on the Client side, a DUT on the OTN side, and an XM chassis to centrally
manage the XOTN chassis units using IxNetwork. Refer to XOTN Installation
Guide for installation information and the online help for configuration
information.
An XOTN system allows you to convert a 40Gb/s or 100Gb/s Ethernet signal to

an Optical Channel Transport Unit (OTU3 or OTU4) signal and vice versa. On
the Transmit side, XOTN can generate a PRBS pattern or transmit an Ethernet
client signal from IxNetwork. The XOTN chassis unit converts the Ethernet
traffic into an OTU3 (43.01Gb/s) or OTU4 (112Gb/s) signal; then transmits it to
your OTN DUT. On the Receive side, XOTN receives OTU3 or OTU4 signals
from your OTN DUT, converts the signal to 40Gb/s or 100Gb/s Ethernet, then
transmits the received traffic to IxNetwork for further analysis. This means you
can perform all IxNetwork Ethernet tests on your OTN enabled DUT. You also
get detailed OTN statistics on the traffic passing through the XOTN unit.
About OTN Technology

The Optical Transport Network (OTN) emerged in the late 1990's as a "digital
wrapper" around client signals before they are transported over a WDM
(Wavelength-division multiplexing) network. Since then, the amount of traffic,
particularly data and video, has increased significantly, placing higher demands

XOTN Chassis Unit
18 About OTN Technology
on the edge and core networks. This has been a major driver for the IP-optical
integration. There is now an increasing need for a technology to replace the
performance monitoring and fault-handling characteristics of SONET/SDH.
The OTN with G.709 framing has emerged as a way to add management
capabilities directly to wavelengths. Using this technology, a client signal can be
mapped directly into an optical network rather than requiring costly protocols,
such as SONET/SDH, to provide the administrative functions.
The XOTN chassis unit is shown in the following figure:
Figure 18-1. XOTN Chassis
The Part Number of XOTN chassis is 941-0030.

XOTN Chassis Unit
Specifications
Specifications
XOTN Chassis Unit The XOTN chassis unit specifications are contained in Table 18-1.
Table 18-1. XOTN Specifications
instructions.
Physical
Size • Width: 441.8 mm (17.394”)

• Height: 88.1 mm (3.469”)
• Depth: 500 mm (19.685”)
Weight 11.5 kg (25.3 lb)
Environmental
Operating 5°C to 35°C (41°F to 95°F)

Temperature
Location Indoor use only
Power Maximum:
5A@115Vac
3A@230Vac
AC Voltage 90 ~ 264Vac,
Full Range Input
Mains supply voltage fluctuations not to exceed +/- 10%
of specified nominal voltage.
Transient overvoltages are specified by Installation
category II.
Frequency 47 ~ 63Hz

XOTN Chassis Unit
18 Specifications

Chapter 19: Ixia GPS Auxiliary
19 Function Device
(AFD1)
This chapter provides details about Ixia GPS Auxiliary Function Device—its
The IXIA Auxiliary Function Device 1 (AFD1) provides the means for accurate
worldwide timing using GPS technology. The IXIA AFD1 is shown in Figure
19-1.
Figure 19-1. Ixia AFD1
The IXIA AFD1 with integrated Global Positioning System (GPS) is designed
for distributed end-to-end measurements of key metrics, including point-to-point
latency and jitter.
The Ixia AFD1 GPS receiver is controlled by an Ixia chassis through a USB port.
Chassis timing is provided by connecting the Sync Out of the AFD1 to the Sync
In of the chassis. This configuration then enables the chassis to operate as a
subordinate in a virtual chassis chain, with the Ixia AFD1 as the master.
Figure 19-2 on page 19-2 shows the AFD1 in operation with other chassis in a
local chassis chain. Multiple local chassis chains can be collected through GPS
into a virtual chassis chain.

Ixia GPS Auxiliary Function Device (AFD1)
19
Figure 19-2. AFD1 in a Chassis Chain
The IxExplorer GUI displays the status of the GPS interface to you. Figure 19-3
shows the Chassis Properties dialog with status information. The connection is
determined to be either locked or unlocked. In the Locked state, the chassis is
locked to GPS time ( GMT ) within 150nS. In the unlocked state, the AFD1 GPS
hardware operates to acquire the minimum number of satellites required to
achieve accurate GPS timing.
Caution: A chassis connected to an AFD1 chassis does not operate properly if

set to Synchronous time source, unless the sync cable is disconnected.
The process of generating the Lock status for the AFD1 consists of getting GPS
time lock and then synchronizing the internal clock to the GPS clock. The AFD1
does not enter the ‘Lock’ state until both of these conditions are met. In the
unlocked state, the chassis in the unlocked chain are not accurately time
synchronized to the rest of the chain.
In operation, once a chassis chain is constructed and the chassis are

synchronized, you can clear the timestamps to provide a baseline time for all
chassis in the chain. The chain operations are then locked until such time that the
GPS lock is lost by a member of the chain. Data sent from one port in the chain to
another provides one-way latency measurements by subtraction of the transmit
time stamp from the receive time stamp.
For large or very remote chassis chains, the chassis chain properties provide an
offset delay. This delay is defaulted to five seconds. For chassis chains where the
communication delays are significant, as in worldwide or large chains, a longer
delay should be selected to allow for setup communication delays. The delay is
the time of a particular chassis operation (for example, start transmit, stop
transmit) plus the configured delay for any synchronous operation. When an
operation for the entire chain is executed, this delay is added to the operation. A
dialog opens indicating that the operation is in process when the delays are
significant.
The chassis time is taken from any chassis with a GPS interface attached. The
setup for the chassis chain requires that all chassis in the chain be locked. This is
indicated in the IxExplorer GUI. The IxExplorer GUI also provides antenna
information such as satellite strength, to enable installation of the antenna in a
location with a good ‘view’ of the satellites.
The critical operation for a virtual chain is the reset of the System Time Stamps.
All other actions are dependent on the synchronous execution of this operation.

AFD1 Setup
To reset time stamps for a GPS-connected system, the reset operation needs to be
executed for the chassis chain, and not for the individual chassis.
Figure 19-3. Chassis Properties AFD1-Time Source
If set to Synchronous time source, a chassis

connected to GPS does not operate properly
unless the sync cable is disconnected.
AFD1 Setup
The AFD1 Kit: The AFD1 kit comes with cables and items required to install and connect the
AFD1 in a lab. The AFD1 kit does not include the cable and antenna for
permanent installation at a particular site. The antenna and cable kits need to be
ordered separately after a site survey determines the site requirements.
The kit contains the following items:

• AFD1 chassis
• AFD1 chassis rack mount ears
• 3-foot sync cable
• 6-foot USB cable
• Window antenna
The AFD1 installation uses the USB cable for communication and power. The
Ixia chassis automatically detects the connections.
The window antenna is included in the kit for demo use only and does not
reliably provide a stable lock environment. For permanent installations, order
either the 75-foot or 200-foot cable and antenna kits.
Successful GPS In the Chassis Properties dialog of IxExplorer, after selection of GPS as the timer
Synchronization in source, the satellites used are displayed. In Figure 19-3 on page 19-3, satellite 04
IxExplorer is being used and the status is ‘locked’. In the chassis tree view of IxExplorer

19 AFD1 Setup
(Figure 19-4), the chassis status is shown as ‘GPS Ready’ if it has successfully
locked onto satellite signal. The highlighted chassis is GPS enabled and ready.
Figure 19-4. Chassis Tree View in IxExplorer
Enabling/Installing GPS Based Synchronization
This procedure to set the time source needs to be followed only for the initial
installation of the AFD1 GPS unit. Thereafter, upon subsequent restarts, the
chassis and AFD1 unit starts fully operational.
1. Start the chassis without attaching the AFD1 GPS unit. Note the message
regarding timing source, as shown in the following figure.
Figure 19-5. IxServer Start Log Before Attaching AFD1
2. Attach the AFD1 GPS unit by plugging in the USB and the Sync cables.
When the chassis detects the GPS (AFD1) unit, it prompts to restart the
IxServer, as shown in the following figure.
Figure 19-6. Sync-In Detection Prompt
3. Click OK to restart IxServer.

IxServer restarts, then detects GPS as the timing source and configures the
chassis as a subordinate, since the chassis is receiving its timing through sync
cable from the ADF1 GPS source. The expected log messages are shown in
Figure 19-7 and Figure 19-8.

AFD1 Setup
Figure 19-7. IxServer Log - GPS AFD1 Detected
GPS AFD1 is detected and COM3 port is indicated as the communication

channel between chassis and AFD1.
Figure 19-8. IxServer Log - Chassis Configured as Slave to AFD1
The chassis is configured as a subordinate to AFD1.

4. Open IxExplorer. In the Chassis Properties dialog box select GPS (AFD1)
timer source, as shown in Figure 19-3 on page 19-3.
Upon selection of GPS option, IxServer must be closed and restarted for the
changes to take effect, as the prompt in Figure 19-9 shows.
Figure 19-9. Time Source Change Detection Prompt
5. Click OK to restart IxServer.

Once IxServer is restarted, the IxServer Log shows the AFD1 GPS unit is
detected as the time source and the chassis is designated as ‘Virtual Master’
rather than subordinate (Figure 19-10).
Figure 19-10.IxServer Log - Chassis is Virtual Master
6. Check IxExplorer for GPS status, as shown in Figure 19-3 on page 19-3.
Satellite details changes periodically showing satellite number and signal
strength. A good signal strength has SNR reading of more than 35.
Now the chassis is ready for operation based on GPS time source.

19 AFD1 Setup
Troubleshooting— If, after completing installation by following the steps above, there is no GPS
GPS Unit ‘Not information and the status is ‘Unlocked’ in the Time Sources tab of Chassis
Ready’ Properties in IxExplorer (Figure 19-11 on page 19-6), then follow the steps
mentioned here to ensure that the ADF1 unit comes up fully functional.
Figure 19-11. Chassis Properties AFD1 - Unsuccessful GPS Status
1. Ensure that the GPS Antenna has good positioning. Position the antenna
outdoors with a clear view of the sky. Refer to Appendix C, GPS Antenna
Installation Requirements.
2. Ensure that the antenna cabling is correctly fitted. Reseat the coaxial cable
into the AFD1 unit.
Allow five to 10 minutes to see GPS reception become established. A full
lock requires three stable satellites.

Worldwide Synchronization
Two or more Ixia chassis connected to a time reference may be distributed
worldwide forming a virtual chassis chain based on GPS and/or CDMA timing.
One possible configuration is shown in Figure 19-12 on page 19-7.
Figure 19-12.Worldwide Deployment of Synchronized Chassis
The ports on all of the chassis may be shared by one or more Ixia software users
located likewise anywhere in the world. Where GPS and CDMA sources are
used, all of the sources must have good quality time values in order for the trigger
to be transmitted.
Once the timing features of the chassis is configured, operating a worldwide set
of Ixia chassis is the same as local operation. The Ixia hardware and software
program the clocks such that they all send a master trigger pulse to all Ixia
chassis, within a tolerance of ±150 ns with GPS and ±100 us for CDMA.

19 Worldwide Synchronization
Ixia chassis timing operates by resetting at a fixed time-of-day on all chassis

from one source, and then maintaining the time accuracy through various
different means. Table 19-1 on page 19-8 describes the full set of options
available and their approximate relative accuracies.
Table 19-1. Summary of Timing Options
Available on Timing Option Time of Day Frequency Frequency Accuracy

Devices Accuracy Source
All Chassis GPS 150 nanoseconds Ixia AFD1 Stratum 1

from GMT
Ixia 100, 400T, Synchronous N/A Internal PC clock 1 microsecond/second

1600T
Ixia 250 CDMA 100 microseconds CDMA Stratum 2

from GMT

from GMT
Ixia 100 GPS (with 150 nanoseconds GPS Stratum 1

attached from GMT
antenna)
Calculating Latency Use the following calculation for latency accuracy for AFD1 ( GPS ) setups.
Accuracy for AFD1 Latency A to B = Lab
(GPS) Latency B to A = Lba
Transmit path A to B = T1
Transmit path B to A = T2
Time at A = Ta
Time at B = Tb
Time Absolute = T
Time Error at any site = Terr
Lab=Ta+T1-Tb
Lba=Tb+T2-Ta
Delta L = Lab – Lba

Delta L = Ta+T1-Tb – ( Tb+T2-Ta )
Delta L = T1-T2+2( Ta-Tb )
Delta L = 2(Ta – Tb)
If Ta = T+/-Terr and Tb = T+/-Terr

Then
Delta L= 2(T+/-Terr – T+/-Terr)

Delta L= 2( |Terr|+|Terr|)

Front Panel LEDs
Delta L = 4Terr
Front Panel LEDs

The AFD1 has the following front panel LEDs:
Table 19-2. AFD1 LEDs
USB Green Indicates that the docnnection is enabled, and

blinks with USB activity.
GPS 1PPS Green Indicates that the ‘1 Pulse Per Second’ heartbeat is
being generated by the GPS hardware. The GPS
hardware has acquired at least one satellite and is
receiving time information.
Pwr OK Green The AFD1 power has been validated.
GPS Lock Green Indicates that the GPS hardware has acquired a fix
and that the 1PPS timing is valid. It also Indicates
that the internal PLL has locked to the 1PPS signal.
Testing is invalidated if the GPS Lock signal is not
illuminated.
IXIA AFD1 Specifications

The IXIA AFD1 specifications are contained in Table 19-3 on page 19-9.
Table 19-3. Ixia AFD1 Specifications
General
Physical
Size 9.6"x7"x2.9" ( with feet, 2.70" without feet)
Weight 3.15 lb
Avg. Shipping Wt. 6 lbs
Environmental
Temperature
Power Worst case power = 2.5W
5V regulated source
Humidity

19 IXIA AFD1 Specifications
GPS Functionality
Clock 12.5Mhz System clock
Pulse Width 80 ns
Rear Panel Switches Reset switch
Front Panel Indicators USB, GPS PPS, Pwr OK, GPS Lock
USB Port Type B
Sync Out RJ14
Antenna SMA
Power (not used) 2.0mm Power jack

Chapter 20: Ixia IRIG-B Auxiliary
20 Function Device
(AFD2)
The IXIA Auxiliary Function Device 2 (AFD2) provides the means for accurate
worldwide timing using Inter-Range Instrumentation Group (IRIG-B)
technology. The ADF2 decodes the GPS satellites and time information and
sends out a pulse to the Optixia chassis. The IXIA /AFD2 is shown in Figure 20-
1.
Figure 20-1. Ixia AFD2
The IXIA AFD2 with integrated IRIG-B is designed to provide 12.5 MHz GPS
clock with a programmable 80 ns sync pulse to the Optixia chassis.
The Ixia AFD2 IRIG-B receiver is controlled by an Ixia chassis through a USB
port. Chassis timing is provided by connecting the Sync Out of the AFD2 to the
Sync In of the chassis. This configuration then enables the chassis to operate as a
subordinate in a virtual chassis chain, with the Ixia AFD2 as the master.
Figure 20-2 on page 20-2 shows the AFD2 in operation with other chassis in a
local chassis chain. Multiple local chassis chains can be collected through IRIG-
B into a virtual chassis chain.

Ixia IRIG-B Auxiliary Function Device (AFD2)
20
Figure 20-2. AFD2 in a Chassis Chain
Ixia XM2
Ixia AFD2 IRIG-B (slave)
Customer’s IRIG Receiver (master)
Receiver Sync Sync
Out In
USB cable
Sync
provides power and COM3 channel
Out
Ixia XM2
(slave)
Sync
In
The IxExplorer GUI displays the status of the IRIG-B interface to the user.
Figure 20-3 shows the Chassis Properties dialog with status information. The
connection is determined to be either locked or unlocked. In the Locked state, the
chassis is locked to IRIG-B time within 150nS. In the unlocked state, the AFD2
IRIG-B hardware operates to lock its VCXO to 1PPS pulse.
Caution: A chassis connected to an AFD2 chassis does not operate properly if

set to Synchronous time source, unless the sync cable is disconnected.
The process of generating the Lock status for the AFD2 consists of getting IRIG-
B time lock and then synchronizing the internal clock to the IRIG-B 1PPS pulse.
The AFD2 does not enter the ‘Lock’ state until the VCXO lock condition is met.
In the unlocked state, the chassis in the unlocked chain are not accurately time-
synchronized to the rest of the chain.
In operation, once a chassis chain is constructed and the chassis are

synchronized, you can clear the timestamps to provide a baseline time for all
chassis in the chain. The chain operations are then locked until such time that the
IRIG-B lock is lost by a member of the chain. Data sent from one port in the
chain to another provides one-way latency measurements by subtraction of the
transmit time stamp from the receive time stamp.
For large or very remote chassis chains, the chassis chain properties provide an
offset delay. This delay is defaulted to 5 seconds. For chassis chains where the
communication delays are significant, as in worldwide or large chains, a longer
delay should be selected to allow for setup communication delays. The delay is
the time of a particular chassis operation (for example, start transmit, stop
transmit) plus the configured delay for any synchronous operation. When an
operation for the entire chain is executed, this delay is added to the operation. A
dialog opens indicating that the operation is in process when the delays are
significant.
The chassis time is taken from any chassis with a IRIG-B interface attached. The
setup for the chassis chain requires that all chassis in the chain be locked. This is
indicated in the IxExplorer GUI.
The critical operation for a virtual chain is the reset of the System Time Stamps.
All other actions are dependent on the synchronous execution of this operation.

To reset time stamps for a IRIG-B-connected system, the reset operation needs to
be executed for the chassis chain, and not for the individual chassis.
Figure 20-3. Chassis Properties AFD2 - Time Source
If set to Synchronous time source, a chassis

connected to IRIG-B does not operate properly
unless the sync cable is disconnected.
.
Table 20-1. Chassis Properties, Time Source Tab
Section Field/Control Description
Time Source Synchronous
IRIG-B (AFD2)
IRIG-B Mode B000 B000 is straight TTL serial output (from

the IRIG-B receiver)
B120 B120 is amplitude modulation (AM) (from

the IRIG-B receiver)
IRIG-B Status Lock Status Locked = locked to IRIG-B 1PPS input

(from IRIG-B receiver)
UTC Time UTC Time (display only) in HH:MM:SS

comes from the IRIG-B receiver
Day Increments from 1 to 366
Control Flags These are vendor-specific flags that are

passed-through from the IRIG-B receiver

20 AFD2 Setup
Table 20-1. Chassis Properties, Time Source Tab
Section Field/Control Description
SBS Straight Binary Seconds from 1 to xxx

each day, starting at midnight. Resets to 0
each midnight.
FPGA Version FPGA version
AFD2 Setup
The AFD2 Kit: The AFD2 kit comes with cables and items required to install and connect the
AFD2 in a lab. The AFD2 kit does not include the IRIG receiver and antenna for
permanent installation at a particular site.
The kit contains these items:

• AFD2 chassis
• AFD2 chassis rack mount ears
• 3-foot sync cable
• 6-foot USB cable
The AFD2 installation uses the USB cable for communication and power. The
Ixia chassis automatically detects the connections.
Successful IRIG-B In the Chassis Properties dialog of IxExplorer, after selection of IRIG-B as the
Synchronization in timer source, the IRIG-B status is displayed. In Figure 20-3 on page 20-3, the
IxExplorer status is ‘locked’ to the 1PPS signal coming from the IRIG-B receiver. In the
chassis tree view of IxExplorer (Figure 20-4), the chassis status is shown as
‘IRIG-B Ready’ if it has successfully locked onto the 1PPS signal.
Figure 20-4. Chassis Tree View in IxExplorer
Enabling/Installing IRIG-B Based Synchronization
This procedure to set the time source needs to be followed only for the initial
installation of the AFD2 IRIG-B unit. Thereafter, upon subsequent restarts, the
chassis and AFD2 unit starts up fully operational.
1. Set up the antenna and IRIG-B receiver (not supplied by Ixia).

AFD2 Setup
2. Connect the 1PPS and IRIG-B outputs from the IRIG-B receiver to the
AFD2.
3. Connect the sync and USB cables between AFD2 and the Ixia chassis. On the
front panel of the AFD2,
• the Pwr OK indicator lights solid,
• the 1PPS indicator blinks to indicate the signal from the IRIG-B receiveris
good, and
• the Lock indicator lights solid.
4. Start the chassis. After starting completely, the IxExplorer resource tree is
displayed as shown in Figure 20-4 on page 20-4.
5. Note the message regarding timing source, as shown in Figure 20-5.
Figure 20-5. IxServer Start Log Before Attaching AFD2
Changing Time Any time the clock source is switched, IxServer must be restarted. When the
Source chassis is switched from Synchronous time source to IRIG-B, or vice-versa, the
following message is displayed as shown in Figure 20-6.
Figure 20-6. Time Source Change Detection Prompt
You are prompted to restart the IxServer. In this example, the time source was
changed from synchronous to IRIG-B.
1. Click OK and then manually restart IxServer.
IxServer restarts, then detects IRIG-B as the timing source and configure the
chassis as a subordinate, since the chassis is receiving its timing through sync
cable from the AFD2 IRIG-B source. The expected IxServer log messages
are shown in Figure 20-7 and Figure 20-8.
Figure 20-7. IxServer Log - IRIG-B AFD2 Detected
IRIG-B AFD2 is detected and COM6 port is indicated as the communication

channel between chassis and AFD2.

20 AFD2 Setup
Figure 20-8. IxServer Log - Chassis Configured as Slave to AFD2
The chassis is configured as a subordinate to AFD2.
Troubleshooting— If, after completing installation by following the steps above, there is no IRIG-B
IRIG-B Unit ‘Not information and the status is ‘Unlocked’ in the Time Sources tab of Chassis
Ready’ Properties in IxExplorer (Figure 20-3 on page 20-3), then one of the following
conditions needs to be corrected.
1PPS signal is not connected: check cabling between AFD2 and the IRIG-B
receiver.
IRIG-B Mode B000 has been selected, but the IRIG-B receiver is sending
B120 signal (or vice versa): change the selection in the Time Sources tab of
Chassis Properties in IxExplorer (Figure 20-3 on page 20-3), and see if the
status is corrected (‘Locked’) after a short interval.

Two or more Ixia chassis connected to a time reference may be distributed
worldwide forming a virtual chassis chain based on IRIG-B and/or CDMA
timing. One possible configuration is shown in Figure 20-9 on page 20-7.
Figure 20-9. Worldwide Deployment of Synchronized Chassis
The ports on all of the chassis may be shared by one or more Ixia software users
located likewise anywhere in the world. Where IRIG-B and CDMA sources are
used, all of the sources must have good quality time values in order for the trigger
to be transmitted.
Once the timing features of the chassis is configured, operating a worldwide set
of Ixia chassis is the same as local operation. The Ixia hardware and software
program the clocks such that they all send a master trigger pulse to all Ixia
chassis, within a tolerance of ±150 ns with IRIG-B and ±100 us for CDMA.
Ixia chassis timing operates by resetting at a fixed time-of-day on all chassis

from one source, and then maintaining the time accuracy through various

20 Worldwide Synchronization
different means. Table 20-2 on page 20-8 describes the full set of options
available and their approximate relative accuracies.
Table 20-2. Summary of Timing Options
Available on Timing Option Time of Day Frequency Frequency Accuracy

Devices Accuracy Source
All Chassis IRIG-B/GPS 150 nanoseconds Ixia AFD2 Stratum 1

from GMT
Ixia 100, 400T, Synchronous N/A Internal PC clock 1 microsecond/second

1600T

from GMT
Ixia 100 CDMA in-built 100 microseconds CDMA Stratum 2

from GMT
Ixia 100 GPS in-built 150 nanoseconds GPS Stratum 1

from GMT
Calculating Latency Use the following calculation for latency accuracy for AFD2 ( IRIG-B ) setups.
Accuracy for AFD2 Latency A to B = Lab
(IRIG-B) Latency B to A = Lba
Transmit path A to B = T1
Transmit path B to A = T2
Time at A = Ta
Time at B = Tb
Time Absolute = T
Time Error at any site = Terr
Lab=Ta+T1-Tb
Lba=Tb+T2-Ta
Delta L = Lab – Lba

Delta L = Ta+T1-Tb – ( Tb+T2-Ta )
Delta L = T1-T2+2( Ta-Tb )
Delta L = 2(Ta – Tb)
If Ta = T+/-Terr and Tb = T+/-Terr

Then
Delta L= 2(T+/-Terr – T+/-Terr)

Delta L= 2( |Terr|+|Terr|)
Delta L = 4Terr

Front Panel LEDs
Front Panel LEDs

The AFD2 has the following front panel LEDs:
Table 20-3. AFD2 LEDs
USB Green Indicates that the connection is enabled, and glows

solid with USB activity.
1PPS Green Indicates that the ‘1 Pulse Per Second’ heartbeat is

being generated by the IRIG-B hardware.
Pwr OK Green The AFD2 power has been validated.
Lock Green Indicates that the internal PLL has locked to the
1PPS signal. Testing is invalidated if the IRIG-B
Lock signal is not illuminated.
IXIA AFD2 Specifications

The IXIA AFD2 specifications are contained in Table 20-4 on page 20-9.
General
Physical
Size 9.6"x7"x2.9" ( with feet, 2.70" without feet)
Weight 3.15 lb
Avg. Shipping Wt. 6 lbs
Environmental
Temperature
Power Worst case power = 2.5W
5V regulated source
Humidity

20 IXIA AFD2 Specifications
IRIG-B Functionality Bit rate is 100 pps and frame rate is 1fps for both
code formats. 1pps pulse provides the precise time
refrence.
IRIGB000 DC level shift, pulse width coded with BCD,

CF(control functions), SBS
IRIGB120 1kHz carrier sine wave amplitude modulated with

BCD, CF (control functions), SBS
Clock 12.5 Mhz GPS System clock
Pulse Width 80 ns
Rear Panel Switches Reset switch
Front Panel Indicators USB, 1PPS, Pwr OK, Lock
USB Port Type B
Sync Out RJ14
IRIG-in BNC, IRIG-B code in
1PPS-in BNC, 1PPS pulse in
Power (not used) 2.0mm Power jack

Chapter 21: IXIA 10/100/1000 Load
21 Modules
This chapter provides details about Ixia 10/100/1000 family of load modules—
the specifications and features.
The 10/100/1000 family of load modules implements Ethernet interfaces that run
at 10 Mbps, 100 Mbps, or Gigabit (1000 Mbps) speeds. Different numbers of
ports and interfaces are available for the different board types. The specifications
for these load modules are listed in Table 21-2 on page 21-7. A representative
selection of these load modules are pictured on the pages that follow.
A member of the 10/100/1000 family used on the Optixia XM12 and XM2
chassis, the LSM1000XMV16-01, is shown in Figure 21-1 on page 21-1.
Figure 21-1. LSM1000XMV16-01 Load Module
Another member of the 10/100/1000 family used on the Optixia XM12 and XM2
chassis, the LSM1000XMS12-01, is shown in Figure 21-2 on page 21-2.

IXIA 10/100/1000 Load Modules
21
Figure 21-2. LSM1000XMS12-01 Load Module
Another of the modules in the 10/100/1000 family, the LM1000STXS4, is shown

in Figure 21-3.
Figure 21-3. LM1000STXS4 Load Module
The application load module ALM1000T8 is an 8-port 10/100/1000 Mbps Base

T Ethernet copper module which supports the Real World Traffic Suite (includes
IxVPN, IxChariot, and IxLoad). This module also supports ARP, PING, and
independent Linux SDK applications. The ALM1000T8 load module is shown in
Figure 21-4.

Figure 21-4. ALM1000T8 Application Load Module
A member of the 10/100/1000 family used on the Optixia XL10 chassis, the
OLM1000STX24, is shown in Figure 21-5 on page 21-3.
Figure 21-5. OLM1000STX24 Load Module

21 Part Numbers
Part Numbers
The part numbers are shown in Table 21-1. Items without a Price List
Names entry are no longer available.
Table 21-1. Part Numbers for 10/100/1000 Modules
Load Module Price List Names Description
LSM1000XMV16-01 LSM1000XMV16-01 16-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps

Ethernet load module, 800MHz PowerPC Processor. 1 GB of
processor memory per port. Does not include SFP
transceivers.
Note: In order to meet the emissions requirements of FCC
part 15 Class A the RJ45 cables attached to this module’s
Ethernet ports must have ferrite beads (Fair-Rite 0431164281
or equivalent) present at both ends of the cable.
LSM1000XMVR16-01 LSM1000XMVR16-01 16-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps

Ethernet load module, reduced performance, 400MHz
PowerPC Processor. 256MB of processor memory per port.
LSM1000XMV12-01 LSM1000XMV12-01 12-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps

Ethernet load module, 800MHz PowerPC Processor. 1 GB of
processor memory per port. Does not include SFP
transceivers.
LSM1000XMVR12-01 LSM1000XMVR12-01 12-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps

Ethernet load module, reduced performance, 400MHz
PowerPC Processor. 256MB of processor memory per port.
LSM1000XMV8-01 LSM1000XMV8-01 8-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
load module, 800MHz PowerPC Processor. 1 GB of processor
memory per port. Does not include SFP transceivers.
LSM1000XMVR8-01 LSM1000XMVR8-01 8-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
load module, reduced performance, 400MHz PowerPC
Processor. 256MB of processor memory per port.
LSM1000XMV4-01 LSM1000XMV4-01 4-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
load module, 800MHz PowerPC Processor. 1 GB of processor
memory per port. Does not include SFP transceivers.
LSM1000XMVR4-01 LSM1000XMVR4-01 4-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
load module, reduced performance, 400MHz PowerPC
Processor. 256MB of processor memory per port.

Part Numbers
LSM1000XMS12-01 LSM1000XMS12-01 12-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps

Ethernet load module. 256MB of processor memory per port.
Does not include SFP transceivers.
LSM1000XMSR12-01 LSM1000XMSR12-01 12-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps

Ethernet load module, reduced performance. 256MB of
processor memory per port.
LSM1000XMSP12-01 LSM1000XMSP12-01 12-port Dual-PHY RJ45 10/100/1000 Mbps Gigabit Ethernet

and SFP fiber. A 750FL or 750GL PowerPC Processor with a
minimum of 256MB per port of CPU memory and 256KB of
layer 2 cache running at 600MHz.
LSM1000XMVDC4-01 LSM1000XMVDC4- 4-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps. 1GB
01 port CPU memory, full-featured L2-L7 with FCoE enabled;
Fiber ports require SFP transceivers, options include SFP-LX,
SFP-SX, and SFP-CU.
LSM1000XMVDC4- LSM1000XMVDC4- 4-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps. 1GB
NG NG port CPU memory, full-featured L2-L7 with FCoE enabled;
SFP-SX, and SFP-CU.
LSM1000XMVDC8-01 LSM1000XMVDC8- 8-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps. 1GB
01 port CPU memory, full-featured L2-L7 with FCoE enabled;
SFP-SX, and SFP-CU.
01 01 port CPU memory, full-featured L2-L7 with FCoE enabled;
SFP-SX, and SFP-CU.
01 01 port CPU memory, full-featured L2-L7 with FCoE enabled;
SFP-SX, and SFP-CU.
LSM10/100/ LSM10/100/ 16-port XMVDC16NG load module is Ixia’s Fusion-enabled

1000XMVDC16NG 1000XMVDC16NG version of the existing LSM XMVDC16 load module. These
The Part Number of two load modules are physically similar. The hardware
this load module is components and application specifications remain
944-1072-01. unchanged. The key difference is the IxN2X capability to run
the load module in IxN2X mode.
LM1000STXS2 LM1000STXS2 2-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
load module. Does not include SFP transceivers.

21 Part Numbers
LM1000STXS4 LM1000STXS4 4-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
LM1000STXS4-256 load module. -256 version has 256MB of processor memory
per port. Does not include SFP transceivers.
LM1000STX2 LM1000STX2 2-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
Load Module. Supports Layer 2-3 stream generation only. No
support for routing, Layer 4-7 applications and the Linux SDK.
Does not include any SFP transceivers.
LM1000STX4 LM1000STX4 4-port Dual-PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
Load Module. Supports Layer2-3 stream generation only. No
support for routing, Layer 4-7 applications and the Linux SDK.
Does not include any SFP transceivers.
LM1000TX4 LM1000TX4 4-port 10/100/1000 Mbps Base-T Ethernet copper, reduced

features. No support for routing protocols, Linux SDK, or L4-
L7 applications.
LM1000TXS4 LM1000TXS4 4-port 10/100/1000 Mbps Base-T Ethernet copper. -256

LM1000TXS4-256 version has 256MB of processor memory per port.
LM1000T-5 2-port multilayer 10/100/1000 Mbps Base-T Ethernet.
ALM1000T8 ALM1000T8 8-port 10/100/1000 Mbps Base T Ethernet copper.

Supports Real World Traffic Suite (includes IxVPN, IxChariot
and IxLoad), and independent Linux-based SDK applications.
CPM1000T8 CPM1000T8 8-port 10/100/1000 Mbps Base T Ethernet copper.

Supports Real World Traffic Suite (includes IxVPN, IxChariot
and IxLoad), and independent Linux-based SDK applications,
with 2GB of memory.
ELM1000ST2 ELM1000ST2 2-port Dual PHY (RJ45 and SFP) 10/100/1000 Mbps Ethernet
Load Module featuring hardware-based high-speed IPSec
encryption for use with IxVPN.
OLM1000STX24 OLM1000STX24 24-port 10/100/1000Mbps Dual-Phy (Copper/Fiber) for Optixia

XL10, reduced features. No support for routing protocols,
Linux SDK, or L4-L7 applications.
OLM1000STXS24 OLM1000STXS24 24-port 10/100/1000 Mbps Dual-Phy (Copper/Fiber) for

Optixia XL10.
SFP-LX 1310 nm LX SFP transceiver used with LM1000STX2,

LM1000STX4, LM1000STXS2, LM1000STXS4,
LM1000STXS4-256, OLM1000STX24, and
OLM1000STXS24.

Specifications
SFP-SX 850 nm SX SFP transceiver used with LM1000STX2,

LM1000STX4, LM1000STXS2, LM1000STXS4,
LM1000STXS4-256, OLM1000STX24, OLM1000STXS24,
LSM1000XMV(R)4-01, LSM1000XMV(R)8-01,
LSM1000XMV(R)12-01, and LSM1000XMV(R)16-01.
LSM1000XMVDC4- 4-port LSM1000XMVDC4NG-01,GIGABIT ETHERNET LOAD

NG MODULE
Specifications
The load module specifications are contained in Table 21-2 on page 21-7 and
Table 21-3 on page 21-8. The limitations of -3, Layer 2/3, and Layer 7 cards are
discussed in the Ixia Load Modules on page 1-5.
Table 21-2. 10/100/1000 Load Module Specifications—Part 1
ALM1000T8, ELM1000ST2 LM1000T-5

CPM1000T81
# ports 8 2 2
-3 Card Available N N N
Layer2/Layer3 Card? N N N
Data Rate 10/100/1000 Mbps 10/100/1000 Mbps 10/100/1000 Mbps2
Connector RJ-45 (copper) RJ-45 (copper) and RJ-45 (copper)

SFP (fiber)
Interfaces 1000Base-T 1000Base-X 1000Base-T

100Base-TX 1000Base-T 100Base-TX
10Base-T 100Base-TX 10Base-T
10Base-T
Capture buffer size N/A N/A 4MB
Captured packet size N/A N/A 12-13k
Streams per port N/A N/A 255
Advanced scheduler N/A N/A N/A

streams per port
Flows per port N/A N/A 15872
Preamble size: min-max N/A N/A 2-254 bytes (10/100)

6-254 bytes (1000)
Frame size: min-max N/A N/A 12-9k bytes (10/100)

40-13k bytes (1000)
Inter-frame gap: N/A N/A 10: 6400ns-1717s in 400ns steps

min-max 100: 640ns-171s in 40ns steps
1000:64ns-68sec in 16ns steps

21 Specifications
ALM1000T8, ELM1000ST2 LM1000T-5

CPM1000T81
Inter-burst gap: min-max N/A N/A 10: 6400ns-1717s in 400ns steps

100: 640ns-171s in 40ns steps
Inter-stream gap: N/A N/A 10: 6400ns-1717s in 400ns steps

min-max 100: 640ns-171s in 40ns steps
Latency N/A N/A 20ns resolution
1. Due to power requirements, only one CPM1000T8 module can be used in a 250 or 400T chassis. Oth-
er modules can be used with the CPM1000T8 in the same chassis, but only one CPM1000T8 at a time
(except MSM family of modules, which has the same limitation).
2. Odd frame sizes can cause diminishment in the actual data rate on this modules.
LM1000STX2 LM1000STXS2 LM1000TX4 LM1000TXS4

LM1000STX4 LM1000STXS4 LM1000TXS4-256
OLM1000STX24 LM1000STXS4-256
LSM1000XMS12-01
LSM1000XMSR12-01
LSM1000XMSP12-01
LSM1000XMV4/8/12/
16-01
LSM1000XMVR4/8/
12/16-01
LSM1000XMVDC4/8/
12/16-01
OLM1000STXS24
# ports 2 (STX2) 2 (STXS2) 4 4

4 (STX4) 4 (STXS4)
24 (STX24) 4 (XMV(R)4)
4 (XMVDC4)
8 (XMV(R)8)
8 (XMVDC8)
12 (XMV(R)12)
12 (XMS12/XMSR12)
12 (XMSP12)
12 (XMVDC12)
16 (XMV16/XMVR16)
16 (XMVDC16)
16 (XMVDC16NG)
24 (STXS24)
-3 Card Available N N N N
Layer2/Layer3 Card? Y Y Y Y
Data Rate 10/100/1000 Mbps 10/100/1000 Mbps 10/100/1000 Mbps 10/100/1000 Mbps

Specifications

LSM1000XMS12-01
LSM1000XMSR12-01
LSM1000XMSP12-01
LSM1000XMV4/8/12/
16-01
LSM1000XMVR4/8/
12/16-01
LSM1000XMVDC4/8/
12/16-01
OLM1000STXS24
Connector Dual: RJ-45 (copper) Dual: RJ-45 (copper) RJ-45 (copper) RJ-45 (copper)
and SFP (fiber) and SFP (fiber) (1000
Mbps only)
Interfaces 1000Base-X 1000Base-X 1000Base-T 1000Base-T

1000Base-T 1000Base-T 100Base-TX 100Base-TX
100Base-TX 100Base-TX 10Base-T 10Base-T
10Base-T 10Base-T
LSM1000XMV(R)4/8/
12/16-01 and
LSM1000XMVDC4/8/
12/16-01 also have
100Base-FX
Ambient Operating LSM1000XMV16-01

Temperature Range and
LSM1000XMVR16-01
41°F to 86°F (5°C to
30°C)
Note: Using these
load modules in the
XM2 or XM12 chassis
lowers the chassis
maximum operating
temperature.
Capture buffer size 8MB LSM1000XMV4/8/12/ 8MB 8MB

16-01 and
LSM1000XMVDC4/8/
12/16-01
32MB (Packet Group
Engine Enabled)
64MB (Packet Group
Engine Disabled)
Others:8MB
Captured packet size 12-13k bytes 12-13k bytes 12-13k bytes 12-13k bytes

21 Specifications

LSM1000XMS12-01
LSM1000XMSR12-01
LSM1000XMSP12-01
LSM1000XMV4/8/12/
16-01
LSM1000XMVR4/8/
12/16-01
LSM1000XMVDC4/8/
12/16-01
OLM1000STXS24
Number of stream in 256 LSM1000XMV4/8/12/ 256 256

Packet Stream Mode 16-01 and
LSM1000XMVDC4/8/
12/16-01
4096
Others:
256
Number of streams in Fast: 16 LSM1000XMV4/8/12/ Fast: 16 Fast: 16

Advanced Scheduler Slow: 240 16-01 and Slow: 240 Slow: 240
Mode (Non Data LSM1000XMVDC4/8/
Center Mode) 12/16-01
• Fast: 16
• Medium: 240
• Slow: 3584
All others:
• Fast: 16
• Slow: 240
Number of streams in N (For N N

Advanced Scheduler LSM1000XMVDC4/8/
Mode (Data Center 12/16-01 card)
Mode) Fast: 16
Medium: 240
Flows per port N/A N/A N/A N/A
Preamble size: 2-61 (10/100) 2-61 (10/100) 2-61 (10/100) 2-61 (10/100)
min-max (bytes) 8-61 (1000 fiber) 8-61 (1000 fiber) 8-61 (1000 fiber) 8-61 (1000 fiber)
6-61 (1000 copper) 6-61 (1000 copper) 6-61 (1000 copper) 6-61 (1000 copper)
Frame size: min-max 12-13k bytes 12-13k bytes 12-13k bytes 12-13k bytes
For XMVDC:
Minimum Frame Size
at Line Rate: 48
Minimum Frame Size
- may not be at Line
Rate: 12
Maximum Frame Size:
2500B

Specifications

LSM1000XMS12-01
LSM1000XMSR12-01
LSM1000XMSP12-01
LSM1000XMV4/8/12/
16-01
LSM1000XMVR4/8/
12/16-01
LSM1000XMVDC4/8/
12/16-01
OLM1000STXS24
Inter-frame gap: Basic Scheduler: Basic Scheduler: Basic Scheduler: Basic Scheduler:
min-max 10: 6400ns-429s in 10: 6400ns-429s in 10: 6400ns-429s in 10: 6400ns-429s in
800ns steps 800ns steps 800ns steps 800ns steps
100: 640ns-42.9s in 100: 640ns-42.9s in 100: 640ns-42.9s in 100: 640ns-42.9s in
Advanced Advanced Advanced Advanced
Scheduler: Scheduler: Scheduler: Scheduler:
10: 6400ns-1717.99s 10: 6400ns-1717.99s 10: 6400ns- 10: 6400ns-
in 800ns steps in 800ns steps 1717.99s in 800ns 1717.99s in 800ns
100: 640ns-171.799s 100: 640ns-171.799s steps steps
in 80ns steps in 80ns steps 100: 640ns- 100: 640ns-
1000: 64ns-68.719 in 1000: 64ns-68.719 in 171.799s in 80ns 171.799s in 80ns
16ns steps 16ns steps steps steps
1000: 64ns-68.719 1000: 64ns-68.719
in 16ns steps in 16ns steps
Inter-burst gap: min- 10: 6400ns-429s in 10: 6400ns-429s in 10: 6400ns-429s in 10: 6400ns-429s in
max 800ns steps 800ns steps 800ns steps 800ns steps
1000: 64ns-16.7ms 1000: 64ns-16.7ms in 1000: 64ns-16.7ms 1000: 64ns-16.7ms
in 16ns steps 16ns steps in 16ns steps in 16ns steps
Advanced Advanced Advanced Advanced
Scheduler: Scheduler: Scheduler: Scheduler:
10: 0.419s 10: 0.419s 10: 0.419s 10: 0.419s
100: 0.0419s 100: 0.0419s 100: 0.0419s 100: 0.0419s
1000: 0.0167s 1000: 0.0167s 1000: 0.0167s 1000: 0.0167s
Inter-stream gap: 10: 6400ns-429s in 10: 6400ns-429s in 10: 6400ns-429s in 10: 6400ns-429s in
min-max 800ns steps 800ns steps 800ns steps 800ns steps
Normal stream min 10: 0.00238fps 10: 0.00238fps 10: 0.00238fps 10: 0.00238fps
frame rate 100: 0.0238fps 100: 0.0238fps 100: 0.0238fps 100: 0.0238fps
1000: 0.238fps 1000: 0.238fps 1000: 0.238fps 1000: 0.238fps

21 ALM1000T8 and CPM1000T8

LSM1000XMS12-01
LSM1000XMSR12-01
LSM1000XMSP12-01
LSM1000XMV4/8/12/
16-01
LSM1000XMVR4/8/
12/16-01
LSM1000XMVDC4/8/
12/16-01
OLM1000STXS24
Advanced stream min 10: 0.000582fps 10: 0.000582fps 10: 0.000582fps 10: 0.000582fps
frame rate 100: 0.00582fps 100: 0.00582fps 100: 0.00582fps 100: 0.00582fps
1000: 0.0146fps 1000: 0.0146fps 1000: 0.0146fps 1000: 0.0146fps
Latency 20ns resolution 20ns resolution 20ns resolution 20ns resolution
Table UDF feature 96K (full) 786K (LSM1000XMV) 96K 96K

(based on minimum 32K (reduced) 96K others (full)
packet size 64K) 32K others (reduced)
Max Value List 48K 48K N/A 48K

Entries
Max Range List 6K 6K N/A 6K

Entries1
1. 192k memory is shared between value list entries (at 4 bytes per entry) and range list entries (at 32 bytes
per entry).
ALM1000T8 and CPM1000T8

The ALM100T8 and CPM1000T8 has a feature that is non-conformant with the
IEEE 802.3 specification. According to the specification, all 4 pairs of signals
must be connected in gigabit copper mode for auto-negotiation to function. On
the ALM100T8 and CPM1000T8, if auto-negotiation fails using all 4 pairs, auto-
negotiation is attempted using only the two pairs used in 10/100 modes. This
allows auto-negotiation to succeed even if gigabit mode is enabled for auto-
negotiation and a 10/100 only cable is used.

Card LEDs
Card LEDs
Each OLM1000STXS24 card incorporates a set of 8 LEDs, as described in Table
21-4.
Table 21-4. 10/100/1000 Card LEDs for OLM1000STXS24, OLM1000STX24
LED Label Usage
48V Green if 48V power is available to the board. Red if not available.
3.3V Green if 3.3V power is available to the board. Red if not

available.

available.

available.
Ready The card is ready for operation.
Aux1 Not currently used.
Aux2 Not currently used.
Fault Red if a fault is present on the board.
Each ELM1000ST2, LM1000STX2/4 and LM1000STXS2/4 card incorporates a

single LED, as described in Table 21-5.
Table 21-5. 10/100/1000 Card LEDs for ELM1000ST2, LM1000STX2/4 and
LM1000STXS2/4
LED Label Usage
Trig The value of the ‘OR’ function of all of the trigger out ports on the
board. The LED’s color is orange.
The ALM1000T8 has a card-level ‘mgmt’ LED next to Port 8. This LED is not
currently used.

21 Port LEDs
Port LEDs
Each port on the ALM1000T8 module incorporates a set of 2 LEDs, as described
in Table 21-6. The ALM1000T8 also has a card-level ‘mgmt’ LED next to Port
8; this LED is not currently used.
Table 21-6. ALM100T8 and CPM1000T8 Port LEDs
LED Label Usage
Link/Tx (Upper Color is used to indicate the link speed:

LED) • 1000Mbps–Green
• 100Mbps–Orange
• 10Mbps–Yellow
Flashing indicates transmit activity.
Off if link is down.
Rx/Error (Lower Three conditions apply:

LED) • Full duplex or master (in 1000 Mbps case): Green with
extended pulses off to indicate receive activity.
• Half duplex or subordinate (in 1000 Mbps case): Off
with extended green pulses to indicate receive activity.
• Error: Overrides the other two modes, with extended
orange pulses.
• No link: Off.
Each LM1000T-5 port incorporates a set of 8 LEDs, as described in Table 21-7

on page 21-14.
Table 21-7. LM1000T-5
LED Label Usage
Mstr Green if the port is the master in a Gigabit connection.
Half Green for half duplex operation.
1000 Green if the port is configured for Gigabit operation.
100 Green if the port is configured for 100 Mbps operation.
10 Green if the port is configured for 10 Mbps operation.
Tx/Col Green during data transmission. Red during collisions.
Rx/Err Green during error free reception. Red if errors are received.
Trig Follows the state of the Trigger Out pin, which is programmed
through User Defined Statistic 1.

Port LEDs
Each LM1000TXS4 port incorporates a set of 6 LEDs, as described in Table 21-

8.
Table 21-8. Port LEDS for LM1000TXS4 and LM1000TX4
LED Label Usage
Slave On for subordinate mode in a Gigabit connection.
Link Green for 1000 Mbps link, orange for 100 Mbps link, yellow for 10
Mbps link, and off for no link.
Rx/Err Green during error free reception. Red if errors are received.
Trigger Follows the state of the Trigger Out pin, which is programmed
Each OLM1000STXS24 port incorporates a set of 2 LEDs, as described in Table

21-9.
Table 21-9. Port LEDs for OLM1000STXS24, OLM1000STX24,
LSM1000XMV4/8/12/16-01, and LSM1000XMS12-01
LED Label Copper Fiber
Link/Tx Color is used to indicate the link speed: Green indicates

(Upper LED) • 1000Mbps–Green link has been
established and
flashes during
• 10Mbps–Yellow transmit activity.
Rx/Error Three conditions apply: Green indicates

(Lower LED) • Full duplex or master (in 1000 Mbps link has been
case): Green with extended pulses off established and
to indicate receive activity. flashes during
receive activity.
• Half duplex or subordinate (in 1000
Mbps case): Off with extended pulses to Continuous red
indicate receive activity. indicates a receive
• Error: Overrides the other two modes error.
and pulses red.
• No link: Off.
Each ELM1000ST2, LM1000STX2, LM1000STX4, LM1000STXS2,

LM1000STXS4, and LM1000STXS4-256 port incorporates a set of 6 LEDs, as
described in Table 21-10 on page 21-16. The LEDs are arranged next to the two
connectors associated with each port: Speed, Slave, and RJ45 Link/Tx/Coll are
next to the RJ45 connector and Rx/Err, Half, and SFP Link/Tx/Coll are next to
the SFP connector.

21 Port LEDs
Table 21-10. Port LEDs for ELM1000ST2, LM1000STX2, LM1000STX4,

LM1000STXS2, LM1000STXS4, and LM1000STXS4-256
LED Label Usage
Speed • Off for 10Mbps.

• Orange for 100Mbps.
• Green for 1000Mbps.
Slave • On in slave or subordinate mode.

• Off otherwise.
RJ45 Link/Tx • Off if SFP is the active connector.

• Steady Orange for no link.
• Flashing Orange for link with collision.
• Steady Green for link with no transmit.
• Flashing green during transmit.
Rx/Err • Flashes green on data receive.

• Steady Red for error.
Half • Green for half-duplex mode.

• Off for full-duplex mode.
SFP Link/Tx/Coll • Off if RJ45 is the active connector.

• Steady Orange for no link.
• Flashing Orange for link with collision.
• Steady Green for link with no transmit.
• Flashing green during transmit.

Trigger Out Values
Trigger Out Values

The signals available on the trigger out pins for the LM1000T5 card is described
in Table 21-11.
Table 21-11. LM1000T-5 Trigger Out Signals
Pin Signal
1 Port 1: 10 ns high pulse for each packet matching User Defined Statistic 1
3 Port 1: Low during transmit of frame, otherwise high
5 Ground
6 Reserved
There is no trigger connector on the ALM100T8 and CPM1000T8.
The ELM1000ST2’s triggers are not currently used.
The signals available on the trigger out pins for the LM1000TXS4, LM1000TX4,
LM1000STXS4, LM1000STX4, LM1000STXS4-256, LM1000STXS2, and
LM1000STX2 cards is described in Table 21-12.
Table 21-12. LM1000TXS4, LM1000TX4, LM1000STXS4, LM1000STX4,
LM1000STXS4-256, LM1000STXS2, and LM1000STX2 Trigger Out
Signals
Pin Signal
1 660ns negative pulse when User Defined Statistic 1 is true.
5 Ground
6 Ground

21 Statistics
Statistics
Statistics for 10/100/1000 cards, under various modes of operation may be found
in the Appendix B, Available Statistics.

Chapter 22: IXIA 1GbE and 10GbE
22 Aggregation Load
Modules
Ixia's Gigabit and 10 Gigabit Ethernet application and streams modules
ASM1000XMV12X is an Ethernet module with additional aggregation
capability. It features 12 ports of 10/100/1000Mbps Ethernet configurable in
either aggregation mode, stream mode, or as 1 port of 10GE aggregation. It can
provide 144 GigE ports in the Optixia XM12 or 24 GigE ports in the Optixia
XM2. The ASM1000XMV12X-01 module is shown in Figure 22-1.
Figure 22-1. ASM1000XMV12X-01 Application Load Module
The ASM1000XMV12X module offers complete Layer 2-7 network and

application testing functionality in a single Optixia XM load module. The twelve
Gig Ethernet ports may either be used individually or aggregated through a 10
Gigabit Ethernet port. This architecture allows the processing power and
resources of up to twelve per-port CPUs to be combined into one physical port,
providing the highest Layer 4-7 line-rate performance, unmatched in any other
Layer 4-7 test solution. Each test port supports wire-speed Layer 2-3 traffic
generation and analysis, high-performance routing/bridging protocol emulation,
and true Layer 4-7 application traffic generation and subscriber emulation. Using
12 GbE ports per module, ultra-high density test environments can be created for

IXIA 1GbE and 10GbE Aggregation Load Modules
22
auto-negotiable 10/100/1000 Mbps Ethernet over copper as well as fiber. With
12 slots per Optixia XM12 chassis, up to 144 Gigabit Ethernet and 12 10GbE test
ports are available in a single test system.
Application Layer The Gigabit Ethernet ASM1000XMV12X module supports high performance
Performance testing of content-aware devices and networks through the Aptixia IxLoad
Testing application. IxLoad creates real-world traffic scenarios at the TCP/UDP (Layer
4) and Application (Layer 7) layers, emulating clients and servers for Web
(HTTP, SSL), FTP, Email (SMTP, POP3, IMAP), Streaming (RTP, RTSP),
Video (MPEG2, MPEG4, IGMP), Voice (SIP, MGCP), and services such as
DNS, DHCP, LDAP and Telnet. Each GE XMV port can be independently
configured to run different protocols and client/server scenarios.
Modes of Operation The ASM1000XMV12X module can operate in three different modes providing
a flexible, scalable and powerful layer 4-7 performance.
Non-Aggregated Mode
In this mode, the twelve 10/100/1000Mbps ports provide L2-L7 XMV

functionality. Each port is capable of providing high performance packet
generation and application layer testing by employing its own port CPU
resources as well as the dedicated hardware stream engine. In this mode the
10GE Aggregation Port is disabled.
Gigabit Aggregated Mode
Gigabit Aggregated Mode allows the twelve PCPUs to be assigned to any of 12

GbE test ports through the switch fabric. Aggregation of the processing power
allows application layer testing at line rate regardless of the test objective. A
cluster of PCPU's can be assigned to any of the physical ports. Multiple clusters
and their assigned physical ports can exist on the same module. Aptixia
applications transparently configure the available PCPU resources and make the
assignment to the physical port(s) to achieve the test objectives. This mode is
exclusive to L4-7 testing and there is no support for hardware stream engine. In
this mode the 10GE Aggregation Port is disabled.
10GE Aggregated Mode
In 10GE Aggregated Mode, all of the twelve PCPUs are assigned to the 10GE
Aggregation Port through the switch fabric. Aggregation of the processing power
allows application layer testing at line rate (10 Gbps). Aptixia applications
transparently configure the PCPU resources to achieve the test objectives. This
mode is exclusive to L4-7 testing and there is no support for hardware stream
engine. In this mode the twelve Gigabit ports are disabled.
Flexible Packet Each ASM1000XMV12X test port is capable of generating precisely controlled
Generation network traffic at up to wire speed of the network interface using Ixia's
IxExplorer test application. Up to millions of packet flows can be configured on

each port with fully customizable packet header fields. Flexible header control is
available for Ethernet, IPv4/v6, IPX, ARP, TCP, UDP, VLANs, QinQ, MPLS,
GRE, and many others. Payload contents can also be customized with
incrementing/decrementing, fixed, random, or user-defined information. Frame
sizes can be fixed, varied according to a pattern, or randomly assigned across a
weighted range. Rate control can be flexibly defined in frames per second, bits
per second, percentage of line rate, or inter-packet gap time.
Real-Time Latency Packets representing different traffic profiles can be associated with Packet
Group Identifiers (PGIDs). The receiving port measures the minimum,
maximum, and average latency in real time for each packet belonging to different
groups. Measurable latencies include:
• Instantaneous latency and inter-arrival time where each packet is associated
with one group ID
• Latency bins, where PGIDs can be associated with a latency range
• Latency over time, where multiple PGIDs can be placed in ‘time buckets’
with fixed durations
• First and last time stamps, where each PGID can store the timestamps of first
and last received packets
Transmit Scheduler There are two modes of transmission are available - Packet Stream and Advanced
Stream Scheduler:
Packet Stream Scheduler
In Packet Stream Scheduler mode, the transmit engine allows configuration of up

to 4096 unique sequential stream groupings on each port. Multiple streams can
be defined in sequence, each containing multiple packet flows defined by unique
characteristics. After transmission of all packets in the first stream, control is
passed to the next defined stream in the sequence. After reaching the last stream
in the sequence, transmission may either cease, or control may be passed on to
any other stream in the sequence. Therefore, multiple streams are cycled through,
representing different traffic profiles to simulate real network traffic.
Advanced Stream Scheduler
In Advanced Stream Scheduler mode, the transmission of stream groupings is

interleaved per port. For example, assume a port is configured with three streams.
If Stream 1 is defined with IP packets at 20% of line rate, Stream 2 is defined
with TCP packets at 50% of line rate, and Stream 3 is defined with MPLS
packets at 30% of line rate, data on the port is transmitted at an aggregate
utilization of 100% with interleaved IP, TCP, and MPLS packets.
Extensive Statistics • Real-time 64-bit frame counts and rates

• Spreadsheet presentation format for convenient manipulation of statistics
counters

22
• Eight Quality of Service counters (supporting 802.1p, DSCP, and IPv4 TOS
measurements)
• Six user-defined statistics that use a trigger condition
• Extended statistics for ARP, ICMP, and DHCP
• Transmit stream statistics for frame counts and rate
• External logging to file for statistics and alerts
• Audible and visual alerts with user-definable thresholds
Data Capture Each port is equipped with 64 MB of capture memory, capable of storing tens of
thousands of packets in real time. The capture buffer can be configured to store
packets based on user-defined trigger and filter conditions. Decodes for IPv4,
IPv6, UDP, ARP, BGP-4, IS-IS, OSPF, TCP, DHCP, IPX, RIP, IGMP, CISCO
ISL, VLAN, and MPLS are provided.
Data Integrity As packets traverse through networks, IP header contents may change, resulting
in the recalculation of packet CRC values. To validate device performance, the
data integrity function of the Gigabit Ethernet ASM1000XMV12X module
allows packet payload contents to be verified with a unique CRC that is
independent of the packet CRC. This ensures that the payload is not disturbed as
the device changes header fields.
Sequence and Sequence numbers can be inserted at a user-defined offset in the payload of each
Duplicate Packet transmitted packet. Upon receipt of the packets by the Device Under Test (DUT),
Checking out-of sequence errors or duplicated packets are reported in real time at wire-
speed rates. You can define a sequence error threshold to distinguish between
small versus big errors, and the receive port can measure the amount of small,
big, reversed, and total errors. Alternatively, you can use the duplicate packet
detection mode to observe that multiple packets with the same sequence number
are received and analyzed.
Routing/Bridging Ixia's Gigabit Ethernet ASM1000XMV12X module supports performance and

Protocol Emulation functionality testing using routing/bridging protocol emulation through the
Aptixia IxNetwork and Aptixia IxAutomate applications. Protocols supported
include IPv4/IPv6 routing (BGP-4, OSPF, IS-IS, and RIP), MPLS (RSVP-TE,
LDP, L2 MPLS VPNs, L3 MPLS VPNs, and VPLS), multicast (IGMP, MLD,
and PIM-SM), and bridging (STP, RSTP, MSTP). Highly scalable scenarios can
be created emulating up to thousands of routers advertising millions of routes per
test port. Up to wire-speed Layer 2/3 traffic can be automatically created to target
routes and MPLS tunnels.

Part Numbers
Part Numbers
ASM1000XMV12X-01 ASM1000XMV12X-01 10 Gigabit Ethernet, Application and Stream Load

Module, 1-10G or 12-Port Dual-PHY (RJ45 and SFP)
10/100/1000 Mbps, for OPTIXIA XM2 or OPTIXIA
XM12 chassis; CPU with 1Gigabyte of memory per
GbE port; On-Board Port Aggregation; GbE Fiber Ports
REQUIRE SFP transceivers, options include SFP-LX
or SFP-SX; and 10GbE port requires a XFP
transceiver, options are either 948-0003 (XFP-850),
XFP-1310, or XFP-1550
SFP-SX 850nm SX SFP transceiver
SFP-LX SFP Transceiver - 1310nm LX
XFP-850 XFP 850nm Transceiver

(948-0003-01)
Specifications
The load module specifications are contained in Table 22-2 on page 22-5. The
Table 22-2. Load Module Specifications
ASM1000XMV12X-01
Number of ports 12 GbE (10/100/1000) + 10GbE
Maximum Ports per Chassis 144 GbE + 12 10GbE
Connector RJ-45 and SFP for GbE ports; XFP for

10GbE port
Interfaces Port 1 to port 12:

1000Base-X
100Base-FX
1000Base-T
100Base-TX
10Base-T
Port 13: 10GBase-X
Port CPU PowerPC 750GL x12

Port CPU Speed: 800 MHz
Port CPU Memory: 1GB

22 Specifications
ASM1000XMV12X-01
Ambient Operating 41°F to 86°F (5°C to 30°C)

Temperature Range Note: Using this load module in the XM2 or
XM12 chassis lowers the chassis maximum
operating temperature.
Connection rate (cps) 200K (in aggregated mode)
Layer 2-3 Routing Protocol and Yes

Emulation
Layer 4-7 Application Traffic Yes

Testing
Capture Buffer per Port 32MB (Packet Group Engine Enabled)

64MB (Packet Group Engine Disabled)
Number of Transmit Flows per Bilions

Port (sequential values)
Number of Transmit Flows per 98K

Port (arbitrary values)
Number of Trackable Receive 128K

Flows per Port (PGIDs)
Number of Stream Definitions Up to 4K in Packet Stream Mode (sequential)

per Port or Advanced Stream (interleaved) modes.
Each Stream Definition can generate millions
of unique traffic flows.
Transmit Engine Wire-speed packet generation with

timestamps, sequence numbers, data
integrity signature, and packet group
signatures.
Receive Engine Wire-speed packet filtering, capturing, real-

time latency for each packet group, data
integrity, and sequence checking.
User Defined Field (UDF) Fixed, increment or decrement by user-

Features defined step, value lists, range lists, cascade,
random, and chained.
Value list = 48K; Range list = 6K.
Table UDF Feature Comprehensive packet editing function for

emulating large numbers of sophisticated
flows. Up to 786K table UDF entries are
supported on the XMV12X.
Filters 48-bit source/destination address, 2x128-bit

user-definable pattern and offset, frame
length range, CRC error, data integrity error,
sequence checking error (small, big,
reverse).

Specifications
ASM1000XMV12X-01
Data Field (per stream) Fixed, increment (Byte/Word), decrement

(Byte/Word), random, repeating, user-
specified up to 13K bytes.
Statistics and Rates: Counter Link State, Line Speed, Frames Sent, Valid
Size: 64-Bit Frames Received, Bytes Sent/Received,
Fragments, Undersize, Oversize, CRC
Errors, VLAN Tagged Frames, User-Defined
Stat 1, User- Defined Stat 2, Capture Trigger
(UDS 3), Capture filter (UDS 4), User-Defined
Stat 5, User-Defined Stat 6, 8 QoS counters,
Data Integrity Frames, Data Integrity Errors,
Sequence Checking Frames, Sequence
Checking Errors, ARP, and Ping requests and
replies.
Error Generation CRC (Good/Bad/None), Undersize, Oversize.
Packet Flow Statistics Real-time statistics to track up to 128K packet

flows on the XMV12X with throughput and
latency measurements.
Latency Measurements 20 ns resolution.
IPv4, IPV6, UDP, TCP Hardware checksum generation.
Frame Length Controls Fixed, random, weighted random, or

increment by user-defined step, random,
weighted random.
Applications Aptixia IxLoad: Layer 4-7 performance testing

of content-aware devices and networks.
Aptixia IxNetwork: Integrated Layer 2-3 data/
control plane performance and functional
testing, supporting routing, bridging, MPLS,
and multicast protocols.
Aptixia IxAutomate: Automation environment
providing pre-built tests for Layer 2-7 data
and control plane testing.
IxExplorer: Layer 2-3 wire-speed traffic
generation and analysis.
IxChariot®: Emulated application
performance testing over Layer 4.
IxAccess: Broadband access performance
testing, including PPPoX and L2TPv2/v3.
IxVPN: Performance verification of IPSec
devices and networks.
Tcl API: Custom user script development for
Layer 2-7 testing.
Linux Software Development Kit (SDK):
Custom user application development. Full
TCP/IP connectivity through management
interface (Telnet, FTP, and so on.)

22 Port LEDs
Port LEDs
Each ASM1000XMV12X port incorporates a set of two LEDs, as described in
Table 22-3. The 1GbE LEDs are used in Normal and 1GbE Aggregate modes.
They behave identically in both modes, except that due to switch limitations, the
‘CRC Error’ LED is non-operational in 1GE Aggregate mode (that is, it never
indicates error). The 1GE LEDs are disabled (always off) in 10GE Aggregate
mode.
Table 22-3. 1GE Port LEDs for ASM1000XMV12X
1GE Link/Tx Color is used to indicate the link speed: Green indicates
(Upper LED) • 1000Mbps–Green link has been
established and
flashes during
• 10Mbps–Yellow transmit activity.
Flashing indicates transmit activity. No link = off.
1GE Rx/ Three conditions apply: Green indicates

Error (Lower • Full duplex or master (in 1000 Mbps link has been
LED) case): Green with extended pulses off established and
receive activity.
Mbps case): Off with extended pulses to Continuous red
indicate receive activity. indicates a receive
• Error: Overrides the other two modes error (supported
and pulses red (supported only in Nor- only in Normal
mal mode). mode).
• No link: Off.
10GE LEDs are disabled (always off) in Normal and 1GE Aggregate modes. In
10GE Aggregate mode, the two LEDs behave as described in Table 22-4.
Table 22-4. 10GE Port LEDS for ASM1000XMV12X
LED Label Usage
10GE Link/ Green indicates link has been established. Flashes during
Tx (Upper transmit activity.
LED) No link = off.
10GE Rx/ Green indicates link has been established. Flashes during
Error (Lower receive activity.
LED) No link = off.

Statistics
Statistics
Statistics for 10/100/1000 cards, under various modes of operation may be found
in the Appendix B, Available Statistics.

22 Statistics

Chapter 23: IXIA Network
23 Processor Load
Modules
This chapter provides details about Ixia’s Xcellon-Ultra XP and Xcellon-Ultra
NP load modules—the specificatons, features, and functionality. It also provides
details on Xcellon-Ultra load module when it operates in IxN2X mode.
Ixia's Gigabit and 10 Gigabit Ethernet Network Processor load modules Xcellon-
Ultra XP and Xcellon-Ultra NP. These are Ethernet modules with additional
aggregation capability. Each features 12 ports of 10/100/1000Mbps Ethernet
configurable in either aggregation mode, stream mode, or as 1 port of 10GE
aggregation. The Xcellon-Ultra module can provide 144 GigE ports in the
Optixia XM12 or 24 GigE ports in the Optixia XM2. The Xcellon-Ultra XP-01
module is shown in Figure 23-1.
IxN2X capability is added to the regular Xcellon-Ultra load module to use it in

IxN2X mode. Xcellon-Ultra XP and NP and Xcellon-Ultra NG load modules
share similar physical properties. In addition to the physical properties, Xcellon-
Ultra NG supports IxN2X mode.
Figure 23-1. Xcellon-Ultra XP-01 Application Load Module

IXIA Network Processor Load Modules
23
The Xcellon-Ultra module offers complete Layer 2-7 network and application
testing functionality in a single Optixia XM load module. The twelve Gig
Ethernet ports may either be used individually or aggregated through a 10
Gigabit Ethernet port. This architecture allows the processing power and
resources of up to twelve per-port CPUs to be combined into one physical port,
providing the highest Layer 4-7 line-rate performance, unmatched in any other
Layer 4-7 test solution. Each test port supports wire-speed Layer 2-3 traffic
generation and analysis, high-performance routing/bridging protocol emulation,
and true Layer 4-7 application traffic generation and subscriber emulation. Using
12 GbE ports per module, ultra-high density test environments can be created for
auto-negotiable 10/100/1000 Mbps Ethernet over copper as well as fiber. With
12 slots per Optixia XM12 chassis, up to 144 Gigabit Ethernet and 12 10GbE test
ports are available in a single test system.
Application Layer The Gigabit Ethernet Xcellon-Ultra module supports high performance testing of
Performance content-aware devices and networks through the Aptixia IxLoad application.
Testing IxLoad creates real-world traffic scenarios at the TCP/UDP (Layer 4) and
Application (Layer 7) layers, emulating clients and servers for Web (HTTP,
SSL), FTP, Email (SMTP, POP3, IMAP), Streaming (RTP, RTSP), Video
(MPEG2, MPEG4, IGMP), Voice (SIP, MGCP), and services such as DNS,
DHCP, LDAP and Telnet. Each GE XMV port can be independently configured
to run different protocols and client/server scenarios.
Real-time Transport Protocol (RTP) Feature
For the Xcellon-Ultra XP and NP modules, the RTP engine built into the FPGA
can generate and terminate audio streams (video and data traffic is an option,
too). The RTP engine works together with the VoIP Peer signaling protocols
present in IxLoad. On a physical port the traffic is a mixture of signaling traffic
generated and analyzed by PCPU, RTP traffic generated by CPCU, and RTP
traffic generated by hardware.
The RTP feature is selectable from the Port Properties—Operation Mode tab in
IxExplorer. For details, see the IxExplorer User Guide, Chapter 18, topic Port
Properties for Xcellon-Ultra and ASM1000XMV12X Modules.
Modes of Operation The Xcellon-Ultra modules can operate in three different modes providing a
flexible, scalable and powerful layer 4-7 performance.
Non-Aggregated (Normal) Mode
In this mode, the twelve 10/100/1000Mbps ports provide L2-L7 XMV

functionality. Each port is capable of providing high performance packet
generation and application layer testing by employing its own port CPU
resources as well as the dedicated hardware stream engine. In this mode the
10GE Aggregation Port is disabled.

Gigabit Aggregated Mode
Gigabit Aggregated Mode allows the twelve PCPUs to be assigned to any of 12

GbE test ports through the switch fabric. Aggregation of the processing power
allows application layer testing at line rate regardless of the test objective. A
cluster of PCPU's can be assigned to any of the physical ports. Multiple clusters
and their assigned physical ports can exist on the same module. Aptixia
applications transparently configures the available PCPU resources and make the
assignment to the physical port(s) to achieve the test objectives. This mode is
exclusive to L4-7 testing and there is no support for hardware stream engine. In
this mode the 10GE Aggregation Port is disabled.
10GE Aggregated Mode
In 10GE Aggregated Mode, all of the twelve PCPUs are assigned to the 10GE
Aggregation Port through the switch fabric. Aggregation of the processing power
allows application layer testing at line rate (10 Gbps). Aptixia applications
transparently configure the PCPU resources to achieve the test objectives. This
mode is exclusive to L4-7 testing and there is no support for hardware stream
engine. In this mode the twelve Gigabit ports are disabled.
Flexible Packet Each Xcellon-Ultra test port is capable of generating precisely controlled
Generation network traffic at up to wire speed of the network interface using Ixia's
IxExplorer test application. Up to millions of packet flows can be configured on
each port with fully customizable packet header fields. Flexible header control is
available for Ethernet, IPv4/v6, IPX, ARP, TCP, UDP, VLANs, QinQ, MPLS,
GRE, and many others. Payload contents can also be customized with
incrementing/decrementing, fixed, random, or user-defined information. Frame
sizes can be fixed, varied according to a pattern, or randomly assigned across a
weighted range. Rate control can be flexibly defined in frames per second, bits
per second, percentage of line rate, or inter-packet gap time.
Real-Time Latency Packets representing different traffic profiles can be associated with Packet
Group Identifiers (PGIDs). The receiving port measures the minimum,
maximum, and average latency in real time for each packet belonging to different
groups. Measurable latencies include:
• Instantaneous latency and inter-arrival time where each packet is associated
with one group ID
• Latency bins, where PGIDs can be associated with a latency range
• Latency over time, where multiple PGIDs can be placed in ‘time buckets’
with fixed durations
• First and last time stamps, where each PGID can store the timestamps of first
and last received packets
Transmit Scheduler There are two modes of transmission are available - Packet Stream and Advanced
Stream Scheduler:

23
Packet Stream Scheduler
In Packet Stream Scheduler mode, the transmit engine allows configuration of up

to 4096 unique sequential stream groupings on each port. Multiple streams can
be defined in sequence, each containing multiple packet flows defined by unique
characteristics. After transmission of all packets in the first stream, control is
passed to the next defined stream in the sequence. After reaching the last stream
in the sequence, transmission may either cease, or control may be passed on to
any other stream in the sequence. Therefore, multiple streams are cycled through,
representing different traffic profiles to simulate real network traffic.
Advanced Stream Scheduler
In Advanced Stream Scheduler mode, the transmission of stream groupings is

interleaved per port. For example, assume a port is configured with three streams.
If Stream 1 is defined with IP packets at 20% of line rate, Stream 2 is defined
with TCP packets at 50% of line rate, and Stream 3 is defined with MPLS
packets at 30% of line rate, data on the port is transmitted at an aggregate
utilization of 100% with interleaved IP, TCP, and MPLS packets.
Extensive Statistics • Real-time 64-bit frame counts and rates

• Spreadsheet presentation format for convenient manipulation of statistics
counters
• Eight Quality of Service counters (supporting 802.1p, DSCP, and IPv4 TOS
measurements)
• Six user-defined statistics that use a trigger condition
• Extended statistics for ARP, ICMP, and DHCP
• Transmit stream statistics for frame counts and rate
• External logging to file for statistics and alerts
• Audible and visual alerts with user-definable thresholds
Data Capture Each port is equipped with 64 MB of capture memory, capable of storing tens of
thousands of packets in real time. The capture buffer can be configured to store
packets based on user-defined trigger and filter conditions. Decodes for IPv4,
IPv6, UDP, ARP, BGP-4, IS-IS, OSPF, TCP, DHCP, IPX, RIP, IGMP, CISCO
ISL, VLAN, and MPLS are provided.
Data Integrity As packets traverse through networks, IP header contents may change, resulting
in the recalculation of packet CRC values. To validate device performance, the
data integrity function of Gigabit Ethernet Xcellon-Ultra modules allows packet
payload contents to be verified with a unique CRC that is independent of the
packet CRC. This ensures that the payload is not disturbed as the device changes
header fields.

Part Numbers
Sequence and Sequence numbers can be inserted at a user-defined offset in the payload of each
Duplicate Packet transmitted packet. Upon receipt of the packets by the Device Under Test (DUT),
Checking out-of sequence errors or duplicated packets are reported in real time at wire-
speed rates. You can define a sequence error threshold to distinguish between
small versus big errors, and the receive port can measure the amount of small,
big, reversed, and total errors. Alternatively, you can use the duplicate packet
detection mode to observe that multiple packets with the same sequence number
are received and analyzed.
Routing/Bridging Ixia's Gigabit Ethernet Xcellon-Ultra modules support performance and

Protocol Emulation functionality testing using routing/bridging protocol emulation through the
Aptixia IxNetwork and Aptixia IxAutomate applications. Protocols supported
include IPv4/IPv6 routing (BGP-4, OSPF, IS-IS, and RIP), MPLS (RSVP-TE,
LDP, L2 MPLS VPNs, L3 MPLS VPNs, and VPLS), multicast (IGMP, MLD,
and PIM-SM), and bridging (STP, RSTP, MSTP). Highly scalable scenarios can
be created emulating up to thousands of routers advertising millions of routes per
test port. Up to wire-speed Layer 2/3 traffic can be automatically created to target
routes and MPLS tunnels.
Part Numbers
Table 23-1. Part Numbers for Network Processor Modules
Xcellon-Ultra XP-01 Xcellon-Ultra XP-01 10 Gigabit Ethernet, Application and Stream Load
Module, 1-10G or 12-Port Dual-PHY (RJ45 and SFP)
10/100/1000 Mbps, for OPTIXIA XM2 or OPTIXIA
XM12 chassis; 800MHz CPU with 1GB of memory per
GbE port; On-Board Port Aggregation; GbE Fiber Ports
REQUIRE SFP transceivers, options include SFP-LX
or SFP-SX; and 10GbE port requires a XFP
transceiver, options are either 948-0003 (XFP-850),
XFP-1310, or XFP-1550
Xcellon-Ultra NP-01 Xcellon-Ultra NP-01 Same as version above but 1GHz CPU and 2GB of
memory.
Xcellon-Ultra NG-01 Xcellon-Ultra NG-01 Same as above.
SFP-SX 850nm SX SFP transceiver
SFP-LX SFP Transceiver - 1310nm LX

(948-0003-01)

23 Specifications
Specifications
Xcellon-Ultra XP-01
Xcellon-Ultra NP-01
Xcellon-Ultra NG-01
Number of ports 12 GbE (10/100/1000) + 10GbE
Maximum Ports per 144 GbE + 12 10GbE

Chassis
Connector RJ-45 and SFP for GbE ports; XFP for 10GbE port
Interfaces Port 1 to port 12:

1000Base-X
100Base-FX
1000Base-T (Aggregate, Copper mode)
10/100/1000Base-T (Aggregate, Copper mode)
100Base-TX
10Base-T
Port 13:
10GBase-X
10G LAN XFP
Port CPU Xcellon-Ultra XP

PowerPC 750GL x12
Port CPU Speed: 800 MHz
Xcellon-Ultra NP
PowerPC 750GX x12
Port CPU Speed: 1 GHz
Xcellon-Ultra NG
PowerPC 750GX x12
Port CPU Speed: 1 GHz
Ambient Operating 41°F to 86°F (5°C to 30°C)

Temperature Range Note: Using this load module in the XM2 or XM12
chassis lowers the chassis maximum operating
temperature.
Connection rate 200K (in aggregated mode)

(cps)

Specifications
Xcellon-Ultra XP-01
Xcellon-Ultra NP-01
Xcellon-Ultra NG-01
Layer 2-3 Routing Yes

Protocol and
Emulation
Layer 4-7 Yes

Application Traffic
Testing
Capture Buffer per 32MB (Packet Group Engine Enabled)

Port 64MB (Packet Group Engine Disabled)
Number of Transmit Bilions

Flows per Port
(sequential values)
Number of Transmit 98K

Flows per Port
(arbitrary values)
Number of 128K
Trackable Receive
Flows per Port
(PGIDs)
Number of Stream Up to 4K in Packet Stream Mode (sequential) or

Definitions per Port Advanced Stream (interleaved) modes. Each Stream
Definition can generate millions of unique traffic flows.
Transmit Engine Wire-speed packet generation with timestamps,

sequence numbers, data integrity signature, and packet
group signatures.
Receive Engine Wire-speed packet filtering, capturing, real-time latency

for each packet group, data integrity, and sequence
checking.
User Defined Field Fixed, increment or decrement by user-defined step,

(UDF) Features value lists, range lists, cascade, random, and chained.
Value list = 48K; Range list = 6K.
Table UDF Feature Comprehensive packet editing function for emulating

large numbers of sophisticated flows. Up to 786K table
UDF entries are supported on the XMV12X.
Filters 48-bit source/destination address, 2x128-bit user-

definable pattern and offset, frame length range, CRC
error, data integrity error, sequence checking error
(small, big, reverse)
Data Field (per Fixed, increment (Byte/Word), decrement (Byte/Word),

stream) random, repeating, user-specified up to 13K bytes.

23 Specifications
Xcellon-Ultra XP-01
Xcellon-Ultra NP-01
Xcellon-Ultra NG-01
Statistics and Link State, Line Speed, Frames Sent, Valid Frames
Rates: Counter Received, Bytes Sent/Received, Fragments, Undersize,
Size: 64-Bit Oversize, CRC Errors, VLAN Tagged Frames, User-
Defined Stat 1, User- Defined Stat 2, Capture Trigger
(UDS 3), Capture filter (UDS 4), User-Defined Stat 5,
User-Defined Stat 6, 8 QoS counters, Data Integrity
Frames, Data Integrity Errors, Sequence Checking
Frames, Sequence Checking Errors, ARP, and Ping
requests and replies.
Error Generation CRC (Good/Bad/None), Undersize, Oversize
Packet Flow Real-time statistics to track up to 128K packet flows on

Statistics the XMV12X with throughput and latency
measurements.
Latency 20 ns resolution.
Measurements
IPv4, IPV6, UDP, Hardware checksum generation.

TCP
Frame Length Fixed, random, weighted random, or increment by user-

Controls defined step, random, weighted random.
Applications Aptixia IxLoad: Layer 4-7 performance testing of content-

aware devices and networks.
Aptixia IxNetwork: Integrated Layer 2-3 data/control
plane performance and functional testing, supporting
routing, bridging, MPLS, and multicast protocols.
Aptixia IxAutomate: Automation environment providing
pre-built tests for Layer 2-7 data and control plane
testing.
IxExplorer: Layer 2-3 wire-speed traffic generation and
analysis.
IxChariot®: Emulated application performance testing
over Layer 4.
IxAccess: Broadband access performance testing,
including PPPoX and L2TPv2/v3.
IxVPN: Performance verification of IPSec devices and
networks.
Tcl API: Custom user script development for Layer 2-7
testing.
Linux Software Development Kit (SDK): Custom user
application development. Full TCP/IP connectivity
through management interface (Telnet, FTP, and so on.)

Port LEDs
Port LEDs
Each Xcellon-Ultra port incorporates a set of two LEDs, as described in Table
23-3. The 1GbE LEDs are used in Normal and 1GbE Aggregate modes. They
behave identically in both modes, except that due to switch limitations, the ‘CRC
Error’ LED is non-operational in 1GE Aggregate mode (that is, it never indicates
error). The 1GE LEDs are disabled (always off) in 10GE Aggregate mode.
Table 23-3. 1GE Port LEDs for Xcellon-Ultra Modules
1GE Link/Tx Color is used to indicate the link speed: Green indicates
(Upper LED) • 1000Mbps-Green link has been
established and
• 100Mbps-Orange
flashes during
• 10Mbps-Yellow transmit activity.
Flashing indicates transmit activity. No link = off.
1GE Rx/ Three conditions apply: Green indicates

Error (Lower • Full duplex or master (in 1000 Mbps link has been
LED) case)—green with extended pulses off established and
receive activity.
Mbps case)—off with extended pulses Continuous red
to indicate receive activity. indicates a receive
• Error—overrides the other two modes error (supported
and pulses red (supported only in Nor- only in Normal
mal mode). mode).
• No link—off.
10GE LEDs are disabled (always off) in Normal and 1GE Aggregate modes. In
10GE Aggregate mode, the two LEDs behave as described in Table 23-4.
Table 23-4. 10GE Port LEDS for Xcellon-Ultra Modules
LED Label Usage
10GE Link/ Green indicates link has been established. Flashes during
Tx (Upper transmit activity.
LED) No link = off.
10GE Rx/ Green indicates link has been established. Flashes during
Error (Lower receive activity.
LED) No link = off.

23 Statistics
Statistics
Statistics for Xcellon-Ultra cards, under various modes of operation may be
found in the Appendix B, Available Statistics.

Chapter 24: IXIA 40/100 Gigabit
This chapter provides details about Ixia's K2 40-Gigabit and 100-Gigabit

Ethernet test modules—the specifications and features.
Ixia's K2 40-Gigabit and 100-Gigabit Ethernet test modules are the world’s first
IP network traffic generation and layer 2-7 measurement and analysis test
solution. K2 load modules are engineered to meet the needs of product teams
developing 40 Gb/s and 100 Gb/s network devices such as routers, switches, and
communications devices. K2 modules can measure and analyze the performance
of Higher Speed Ethernet (HSE) standard-compliant devices at line rate, and are
compatible with Ixia’s chassis and broad range of 10 Mbps, 100 Mbps, 1 Gbps,
and 10 Gbps interfaces, allowing real-world, full product testing in a single box.
Ixia's 40 Gb/s and 100 Gb/s load modules provide network device developers the
ability to test 40 GE and 100 GE hardware electronics at full line-rate operation.
Early adopters of the HSE technology can use the Ixia test system to validate
their compliance with the new PCS lane operation of the IEEE P802.3ba draft
standard.
Ixia's K2 load modules are valuable to developers who are integrating firmware
and software into new electronics hardware, or integrating optical transceivers
into their network devices and systems. Ixia's HSE modules can be used to
validate and benchmark the performance limits of these network devices by
employing layer 2 and 3 stress testing, virtual scalability testing, and negative
testing. Ixia's HSE load modules ensure that a network device is ready to
interoperate with other manufacturers’ devices that claim compliance to the IEEE
P802.3ba draft standard, and facilitate interoperability testing between different
vendors of network devices and equipment.

IXIA 40/100 Gigabit Ethernet Load Modules
24
Figure 24-1. 100GE and 40GE LSM XMV Load Modules
Figure 24-2. 40GE LSM XMV QSFP Load Module
Key Features Industry's first 40 Gb/s and 100 Gb/s Layer 2 through 7 IP test solutions:
• 6 ports per XM12 chassis (10 rack mount units)
Compatible with XM12 (941-0002) and XM12 High Performance chassis
(941-0009)
• 1 port per XM2 (941-0003) desktop chassis
Industry's first commercially available 100 Gb/s Physical Coding Sublayer (PCS)
test system:
Provides the ability to check compliance to the IEEE P802.3ba draft standard
for both Transmit and Receive sides
Generates and analyzes full 40 Gb/s and 100 Gb/s line rate traffic:
• Tracks and analyzes up to 1 million flows per port for;

• Real-time latency
• Inter-arrival time
• Packet loss
• Data integrity
• Sequence checking
• Packet capture
Ixia's 40 Gb/s and 100 Gb/s load modules are designed for comprehensive layer
2-7 testing with integrated data plane and control plane traffic generation and
analysis.
Nomenclature The LSM HSE family identifying numbers are shown in Table 24-1.
Table 24-1. LSM HSE Modules
Load Module Model Number Description
40GE LSM XMV1 HSE40GETSP1-01 1-port 40GE, 2-slot, full-

featured load module.
Supports routing protocols,
Linux SDK, and L4-7
applications (requires 40GE
CFP MSA transceiver).
100GE LSM XMV1 HSE100GETSP1-01 1-port 100GE, 2-slot, full-

featured load module. Supports
routing protocols, Linux SDK,
and L4-7 applications (requires
100GE CFP MSA transceiver).
40/100GE LSM XMV HSE40/ 1-port, 2-slot, dual-speed, full-

100GETSP1-01 featured load module with CFP
interface
40GE LSM XMV HSE40GEQSFP1-01 1-port, 1-slot, full-featured load

QSFP module with QSFP interface
Specification are given in Table 24-2..

Table 24-2. HSE Module Specifications
HSE40GETSP1 HSE40GEQSFP1
HSE100GETSP1
HSE40/100GETSP1
Number of ports per module 1 1

module
Maximum ports per chassis XM12: 6

XM12 High Performance: 6
XM2: 1
Supported transceivers CFP MSA Pluggable QSFP Pluggable

24
HSE100GETSP1
HSE40/100GETSP1
Data Rate 40 Gbps 40 Gbps

100 Gbps
Port CPU Speed and memory 1GHz/2 GB 1GHz/2 GB
Per-port Capture buffer 1.4 GB 700 MB
Interface protocol 40 Gigabit Ethernet per IEEE 40 Gigabit Ethernet per IEEE
P802.3ba, Draft 2.0, 100GBASE-R P802.3ba, Draft 2.0, 100GBASE-R
100 Gigabit Ethernet per IEEE
P802.3ba, Draft 2.0,
40GBASE-R
Ambient Operating Temp. Range 41°F to 95°F (5°C to 35°C) 41°F to 95°F (5°C to 35°C)
Note: Ambient air temperature at Note: Ambient air temperature at
the installation site for the system the installation site for the system
should not exceed 95°F (35°C). should not exceed 95°F (35°C).
Layer 2/3 routing protocol Yes

emulation
Layer 4-7 application traffic testing Yes
Number of transmit flows per port Billions

(sequential)
Number of transmit flows per port 1 million

(arbitrary values)
Number of trackable receive flows 1 million
Captured packet size 49-14,000 bytes 49-14,000 bytes
Number of stream definitions per 256 256

port In packet stream (sequential) or
advanced stream (interleaved)
mode, each stream definition can
generate millions of unique traffic
flows.
Note: In the Data Center mode, the
number of transmit streams is 256.
Preamble size 8 bytes 8 bytes
Frame size: min-max (bytes) 49-14,000 49-14,000
Inter-frame gap: 1.8ns - 21.99sec 1.8ns - 21.99sec

min-max
Inter-burst gap: min-max 1.8ns - 21.99sec 1.8ns - 21.99sec
Inter-stream gap: 1.8ns - 21.99sec 1.8ns - 21.99sec

min-max
Normal stream frame rate 0.045 fps - full line rate 0.045 fps - full line rate

HSE100GETSP1
HSE40/100GETSP1
Advanced stream min frame rate 0.091fps 0.091fps
Latency measurements standard resolution as 20ns 20 nanosecond resolution

user selectable high resolution as user selectable high resolution as
2.5ns 2.5ns
Table UDF Entries 1million 1 million

Comprehensive packet editing
function for emulating large
numbers of sophisticated flows.
Entries of up to 256 bytes, using
lists of values, can be specified and
placed at designated offsets within
a stream. Each list consists of an
offset, a size, and a list of values in
a table format.
Max Value List UDF entries 1 million entries for 32-bit and 24- 1 million entries for 32-bit and 24-
bit, 2 million entries for 8 and 16-bit. bit, 2 million entries for 8 and 16-bit.
Max Range List UDF entries N/A N/A
Packet flow statistics Track over 1 million flows
Transmit Engine Wire-speed packet generation with

timestamps, sequence numbers,
data integrity signature, and packet
group signatures
Receive Engine Wire-speed packet filtering,

capturing, real-time latency and
inter-arrival time for each packet
group, data integrity, and sequence
checking
User defined field features Fixed, increment, or decrement by

user-defined step, value lists, range
lists, cascade, random, and chained
Filters 48-bit source/destination address,

2x128-bit user definable pattern and
offset, frame length range, CRC
error, data integrity error, sequence
checking error (small, big, reverse)
Data field per stream Fixed, increment or decrement by

user-defined step, value lists, range
lists, cascade, random, and chained

24
HSE100GETSP1
HSE40/100GETSP1
Statistics and rates Link state, line speed, frames sent,

(counter size: 64 bits) valid frames received, bytes sent/
received, fragments, undersize,
oversize, CRC errors, VLAN tagged
frames, 6 user-defined stats,
capture trigger (UDS 3), capture
filter (UDS 4), user-defined stat 5,
user-defined stat 6, 8 QoS counters,
data integrity frames, data integrity
errors, sequence checking frames,
sequence checking errors, ARP,
and ping requests and replies
Error generation CRC (good/bad/none), undersize,

oversize
MDIO Ability to calibrate and remove

inherent latency from any
MSAcompliant 40 Gb/s or 100Gb/s
CFP transceiver
Transmit line clock adjustment Ability to adjust the parts per million
(ppm) line frequency over a range
of LAN mode: - 100 to +100 ppm
Clock In/Out The load module provides two

female SMA coaxial connectors—
one for clock input and one for clock
output—to allow the device under
test (DUT) to frequency-lock with
the load module interface. See
Clock In/Out on page 24-8.

HSE100GETSP1
HSE40/100GETSP1
Layer 1 BERT capability The load module supports the

following BERT features on both 40
Gb/s and 100 Gb/s speeds:
• User selected PRBS pattern for
each PCS Lane
• User selects from a wide range
of PRBS data patterns to be
transmitted (true and comple-
ment)
• Send single, continuous, and
exponentially controlled amounts
of error injection
• Wide range of statistics, includ-
ing: Pattern Lock, Pattern Trans-
mitted, Pattern Received, Total
Number of Bits Sent and
Received, Total Number of
Errors Sent and Received, Bit
Error Ratio (BER), Number of
Mismatched 1’s and 0’s.
• Lane Stats Grouping per lambda
for SMF and MMF 40 Gb/s and
100 Gb/s based on IEEE802.3ba
defined physical medium depen-
dent (PMD).
Physical Coding Sublayer (PCS) IEEE P802.3ba compliant PCS

test features transmit and receive side test
capabilities.
Per PCS lane, transmit lane Supports all combination of PCS

mapping lane mapping: Default, Increment,
Decrement, Random, and Custom.
Per PCS lane, skew insertion and User selectable from zero up to 3
deskew capability microseconds of skew insertion on
transmit side. Ability to measure
deskew up to 6 microseconds on
receive side.
IPv4, IPv6, UDP, TCP Hardware checksum generation,

and verification.
Frame length controls Fixed, random, weighted random,

or increment by user-defined step,
random, weighted random.
Preamble view Allows to select to view the

preamble in Packet View.
Link Fault Signaling Ability to select the option to have

the transmit port ignore link faults
from a remote link partner.

24
Port LEDs Each 40/100GE port incorporates a set of LEDs, as described in the following
tables.
Table 24-3. 40/100GE LSM Port LEDs
LED Label Usage

forced Link Up state, red if link is down. Link may be down
due to no signal or no PCS lock.
Tx Active Green indicates that Tx is active and frames being sent; red
indicates Tx is paused; off indicates Tx is not active.
Rx Active Green indicates that Rx is active and frames being

received; red indicates Rx is paused; off indicates Rx is not
active.
Rx/Error Green indicates valid Rx frames are being received; red

indicates error frames being received; off indicates no
frames being received.
Attention (Reserved for future use)
Pwr Good Green when power is on, red if power fault occurs.
Clock In/Out The load module provides coaxial connectors for clock input and clock output to
allow the DUT to frequency-lock with the interface. When running off an
external clock, the clock input signal must meet the requirements listed in Table
24-4 to ensure proper performance of the load module.
The clock in/out electrical interface parameters are also defined in Table 24-4.
Table 24-4. Clock In/Out Electrical Interface Parameters
Parameter Characteristic
Clock Frequency 161.13 MHz ±100ppm

Input
Duty cycle 50%
Jitter ±150ps max. cycle to cycle, >1kHz
Amplitude Vpp = 4.0
Impedance 50 ohm ± 5%, DC coupled
Connector Female SMA
Clock Frequency 161.13 MHz +/-100ppm (Programmable ppm

Output in Internal Clock Mode)
Duty cycle 40 to 60%
Jitter 20ps max cycle to cycle, >1kHz
Amplitude 0.7Vpp min into 50 ohms, AC coupled output
Edge rates 200ps to 340ps (20% to 80%) into 50 ohms

Impedance 50 ohms +/-5%, AC coupled
The load module contains a phase-locked loop (PLL) that reduces the jitter of the
input clock, either from the internal or external clock source. The bandwidth of
the PLL is approximately 1kHz.
Statistics Statistics for 40/100GE LSM cards, under various modes of operation may be
found in Table B-36 on page B-165.
Intrinsic Latency This option, when present and enabled, reduces the measured latency by the
Adjustment amount of latency that is induced by the test equipment itself (not the DUT). For
a specific transceiver, the system retrieves its pre-determined latency value and
subtracts this from the measured overall latency. For an ‘unknown’ transceiver
(not previously measured), it calculates and stores the intrinsic latency value.
On the General tab in Port Properties, the Latency Calibration option is only
enabled for cards with transceivers that have not been pre-measured for intrinisic
latency by Ixia. The Latency Calibration option is grayed-out if any one of the
following conditions are present:
• there is no transceiver
• the transceiver is CFP and a value is found for it in the list of precalibrated
values
The Latency Calibration option is enabled if the transceiver is CFP but no pre-
calibrated value is found in the stored list. The Latency Calibration option is
also enabled for transceivers that you have previously calibrated, so that the
calibration measurement may be repeated (if desired).
Clicking the Latency Calibration option runs a Tcl script that measures intrinsic
latency and stores the value in an .xml file. The .xml file contains the values that
you have produced and saved. Each value is identified for a specific transceiver
(per manufacturer, model, and serial number). You can run the calibrate process
repeatedly with the same transceiver (if desired). Each new measurement
overwrites the previous one for that transceiver.
Running the calibration measurement puts the port into a special loopback mode
to measure intrinsic latency. When done, the port is put back into default normal
mode. Any port configuration you have set before calibrating intrinsic latency, is
lost as the port reverts to a default configuration.
The Enable check box is grayed out when no value exists in the system for the
specific transceiver. If a value exists in the .xml file, then the Enable check box
is available. Select the check box to enable the intrinsic latency adjustment.

24 Multilane Distribution Configuration
After the intrinsic latency adjustment has been done, you may want to refresh the
chassis or close and reopen the Port Properties dialog.
Multilane Distribution
Configuration
The Tx Lane tab allows to control the PCS (Physical Coding Sublayer) lane
configuration and skew. It is part of the Port Properties for the module.
Note: The other tabs in the Port Properties page are described in the IxExplorer
User Guide, as are the rest of the controls for the module.
To open the Tx Lane tab:

1. Select the 40 or 100GE LSM XMV1 module in the left pane of the IxExplorer
window as shown in Figure 24-3.
Figure 24-3. Select Module
2. Expand the node, and select the Port object. In the right window pane,
double-click the Port Properties object as shown in Figure 24-4.
Figure 24-4. Port and Port Properties
3. In the Port Properties dialog, select the Tx Lane tab. Use this tab to control the
PCS lane order and the skew for each lane.

Multilane Distribution Configuration
The Tx Lane tab is shown in Figure 24-5.
Figure 24-5. Tx Lane Tab
Table 24-5 explains the options in the Tx Lane tab page.

Table 24-5. Tx Lane Tab Configuration
Field Description
Lane Mapping Allows you to select a PCS lane ordering method. There
are four options:
• Default: The default ordering method. The default order
is each physical port corresponds to 2 PCS lanes that
are n and n+10, where n = physical lane number.
• Increment: Orders the lanes from 0 to 19, straight down
the list.
• Decrement: Orders the lanes from 19 to 0, straight down
the list.
• Custom: Allows to put the lanes in any order by manually
entering the numbers in the fields. The starting order is
the last selected mapping.
Physical Lane The physical lane identifier. The physical lane is paired with
a corresponding PCS lane.

Table 24-5. Tx Lane Tab Configuration
Field Description
PCS Lane A number identifier for the PCS lane. The PCS lane is
paired with a corresponding physical lane.
Skew The skew slider is used to set a skew value for the PCS
lane, in nanoseconds, on the transmit side. Lane Skew is
the ability to independently delay one or more of the 20
PCS lanes.
When the slider is moved, the nanoseconds field is
correspondingly adjusted. You can also enter a nano
second value directly into this field.
When the slider is fully pushed to the right, the skew
injected into the transmit stream is 0 (minimum). When the
slider is pushed all the way to the left. the skew injected into
the transmit stream is 3 uS (maximum).
PCS Lane Statistics The PCS lane statistics table allows to view the statistics for the configured PCS
lanes.
To open the PCS lane statistics table:

1. Select the 40 or 100GE LSM XMV1 module in the left pane of the IxExplorer
window as shown in Figure 24-3.
2. Expand the node, and select the Port object. In the right window pane,
double-click the PCS lane statistics object as shown in Figure 24-6.
Figure 24-6. Port and PCS Lane Statistics
3. The PCS lane statistics table opens. Use this table to view the PCS lane
statistics for each lane. The statistics are for the receive side.

Multilane Distribution Configuration
The PCS lane statistics table is shown in Figure 24-7.
Figure 24-7. PCS Lane Statistics Table
Table 24-6 explains the entries in the PCS lane statistics table.
Table 24-6. PCS Lane Statistics Data
Field Description
Physical Lane The identifier for the Receive physical lane. This is a tag/
fixed label to ID each lane.
Sync Header Indicates if the received PCS lane achieved sync-bit lock.
Lock Green indicates success, red failure.
PCS Lane Marker Indicates if the received PCS lane has achieved alignment
Lock marker lock.
Green indicates success, red failure.
PCS Lane Marker The PCS lane number identified by the alignment marker.
Map This is only valid when PCS Lane Marker Lock is green.
Relative Lane Shows the actual skew in nanoseconds.

Skew (ns) Skew measurements are valid only when all lanes are
locked with 20 unique lane markers.
The first PCS Lane markers to arrive have skew of 0. All
other lane skews are relative to them.
Sync Header The number of synchronization bit errors received.

Error Count
PCS Lane Marker The number of incorrect PCS lane markers received while
Error Count in PCS lane lock state.
BIP-8 Error Count Bit interleaved parity error count. It detects the number of
BIP-8 errors for a PCS lane.

Table 24-6. PCS Lane Statistics Data
Field Description
Lost Sync Header When lit, indicates the loss of sync header lock since the
Lock last statistic was read. If colored gray, there is no error. If
colored red, an error has occurred.
Lost PCS Lane When lit, indicates the loss of PCS lane marker lock since
Marker Lock the last statistic was read. If colored gray, there is no error.
If colored red, an error has occurred.

Chapter 25: IXIA 10 Gigabit
This chapter provides details about 10 Gigabit Ethernet (10GE) family of load
modules—the specifications and features.
The 10 Gigabit Ethernet (10GE) family of load modules implements five of the
seven IEEE 8.2.3ae compliant interfaces that run at 10Gbit/second. Cards are
available which offer the following interfaces:
• 10GE LAN
• 10GE WAN
• XAUI
• XENPAK - with options for XPAK or X2 transceiver use.
Figure 25-1 on page 25-2 shows an LM10GEXENPAK module.

IXIA 10 Gigabit Ethernet Load Modules
25 LSM 10GE Family
Figure 25-1. LM10GEXENPAK
In addition, two families of multimode card are available which offers combined
10GE LAN/WAN, OC192 POS, BERT, and FEC functionality. The features
available for these load modules are described in Chapter 26, IXIA 10GE LAN/
WAN and OC 192 POS Load Modules.
The full details for these families may be found at:

• LSM 10GE Family on page 25-2
• 10GE LAN Family on page 25-22.
• XAUI Family on page 25-25
• XENPAK Family on page 25-30
LSM 10GE Family

The Ixia 10 Gigabit Ethernet LAN Service Module (LSM) offers unprecedented
scalability, performance, and service testing flexibility. The Ixia 10GE LSM is
Ixia's third-generation 10 Gigabit Ethernet solution. It is the industry's first six-
port solution, and it offers a broad portfolio of edge/core testing solutions for the
most demanding test environments including performance, scalability, and
conformance testing of Layer 2-3, Routing Protocols, and high performance
Layer 4-7 testing. It supports IPv4 and IPv6 wire-speed traffic generation,
advanced analysis and IPv4 and IPv6 routing protocol emulation.
The Ixia 10GE LSM supports a comprehensive portfolio of service testing

solutions for the next-generation service provider networks including Metro

LSM 10GE Family
Ethernet E-LAN and E-LINE services; and MPLS VPNs such as Layer 2 VPNs,
Layer 3 RFC 2547 VPNs, and VPLS.
Figure 25-2. LSM10GXM8-01 NGY Load Module
Figure 25-3. LSM10GXL6-01 Load Module

25 LSM 10GE Family
Figure 25-4. LSM10GXM3-01 Load Module
Figure 25-5. LSM10GL1-01(XENPAK Carrier Card)

LSM 10GE Family
Figure 25-6. LSM10GMS-01(MACsec Carrier Card)
Figure 25-7. LSM10GL1-01 (XFP Carrier Card)

25 LSM 10GE Family
Part Numbers The LSM family part numbers are shown in Table 25-1.
Table 25-1. 10GE LSM modules
Load Module Part Number Description
10GE LSM LSM10G1-01 1-port 10GE, single slot, full-featured load

module. Supports routing protocols, Linux
SDK, and L4-7 applications (requires
XENPAK or XFP adapter and matching
transceiver).
10GE LSM LAN XFP LSM10GL1-01 1-port, single slot, L2/L3 only, does not
support routing protocols and L4-7
applications (requires XENPAK or XFP
adapter and matching transceiver).
10GE LSM MACSec LSM10GMS-01 1-port 10GE, single slot, full-featured load
SDK, and L4-7 applications. Supports
MACSec functionality for stream
generated traffic.
XFP LAN/WAN carrier card is integrated.
10GE LSM XL6 LSM10GXL6-01, -02 6-port 10GE, single slot, full featured LAN
load module for Optixia XL10. Supports
routing protocols, Linux SDK, and L4-7
applications (does not include XFP
transceivers).
10GE LSM XM3 LSM10GXM3-01 3-Port 10GE, single slot, full-featured load
10GE LSM XMR3 LSM10GXMR3-01 3-Port 10GE, single slot, reduced-featured

load module. Supports Linux SDK and L4-
7 applications.
10GE LSM XM8 LSM10GXM8-01 NGY 8-port 10GE, single slot, full-featured
load module 800MHz, 512MB. Full L2/7
support. Linux SDK, and L4-7 applications.
10GE LSM XMR8 LSM10GXMR8-01 NGY 8-port 10GE, 400MHz, 128MB single
10GE LSM XMR8 10GBASE-T LSM10GXMR8GBT-01 slot, reduced L2/3 support with limited L3
routing, Linux SDK, and L4-7 applications.
Includes 10GBASE-T version.
10GE LSM XM8XP LSM10GXM8XP-01 NGY 8-port 10GE, 800MHz, 1GB, Extra
10GE LSM XM8 10GBASE-T LSM10GXM8GBT-01 Performance.
10GE LSM XM8S LSM10GXM8S-01 NGY 8-port 10GE, LAN/WAN, SFP+

interface with 1GB RAM per port; for
OPTIXIA XM12-02 and OPTIXIA XM2-02
chassis; full L2/7 support. Requires one or
more SFP+ transceiver options:
10GBASE-SR, 10GBASE-LR, 10GBASE-
LRM, or 10GSFP+Cu.

LSM 10GE Family
10GE LSM XMR8S LSM10GXMR8S-01 Same as 10GE LSM XM8S but reduced
L2/3 support with limited L3 routing.
NGY-NP8-01 NGY-NP8-01 10 Gigabit Application Network Processor

Load Module, 8-Port LAN/WAN, SFP+
interface.
10GE LSM XM4 LSM10GXM4-01 NGY 4-port 10GE, single slot, full-featured
load module 800MHz, 512MB. Full L2/7
support. Linux SDK, and L4-7 applications.
10GE LSM XMR4 LSM10GXMR4-01 NGY 4-port 10GE, 400MHz, 128MB,

10GE LSM XMR4 10GBASE-T LSM10GXMR4GBT-01 single slot, reduced L2/3 support with
limited L3 routing, Linux SDK, and L4-7
applications.
10GE LSM XM4XP LSM10GXM4XP-01 NGY 4-port 10GE, 1GHz, 1GB, Extra

more SFP+ transceiver options:
10GBASE-SR, 10GBASE-LR, 10GBASE-
LRM, or 10GSFP+Cu.

interface.
10GE LSM XM2XP LSM10GXM2XP-01 NGY 2-port 10GE, 1GHz, 1GB, Extra
10GE LSM XMR2 LSM10GXMR2-01 NGY 2-port 10GE, 400MHz, 128MB,

10GE LSM XMR2 10GBASE-T LSM10GXMR2GBT-01 single slot, reduced L2/3 support with
limited L3 routing, Linux SDK, and L4-7
applications.

more SFP+ transceivers: 10GBASE-SR,
10GBASE-LR, 10GBASE-LRM, or
10GSFP+Cu.

25 LSM 10GE Family

interface.
XENPAK-ADAP-01 948-0007 XENPAK LAN Adapter for LSM10Gx1-xx.
XFP-ADAP-02 948-0002 LAN/WAN Adapter for LSM10Gx1-xx
X2-ADAP-01 948-0008 X2 Carrier
10GBASET-ADAP-01 948-0009 10GBase-T Adapter for LSM10Gx1-xx
SFP-ADAP-01 948-0012 SFP+ Adapter for LSM10G1 and

LSMGL1, must be used with an SFP+
transceiver.
SFP+ transceiver 10GBASE- 948-0013 10GBASE-SR Accessory, SFP+

SR Transceiver for 10GE LAN/WAN load
modules with pluggable SFP interface,
850nm.
SFP+ transceiver 10GBASE- 948-0014 10GBASE-LR Accessory, SFP+

LR Transceiver for 10GE LAN/WAN load
modules with pluggable SFP interface,
1310nm.
SFP+ transceiver 10GBASE- 948-0015 10GBASE-LRM Accessory, SFP+

LRM Transceiver for 10GE LAN load modules
with pluggable SFP+ interface, 1300nm,
MMF. Note: LAN mode is not supported.
SFP+ transceiver 10GSFP+Cu 948-0016 10GSFP+Cu Accessory, Direct Attach

Cable Transceiver for 10GE LAN/WAN
load modules with pluggable SFP+
interface, Copper Wire, 3 meter length.
10GE LSM XM8NGY 944-1070-01 LSM10GXM8NG-01 10 Gigabit Ethernet

Load Module, 8-Port LAN/WAN, XFP
interface
10GE LSM XM4NGY 944-1071-01 LSM10GXM4NG-01 10 Gigabit Ethernet

Load Module, 4-Port LAN/WAN, XFP
10GE LSM XM2NGY 944-1096-01 LSM10GXM2NG 10 GIGABIT ETHERNET

LOAD MODULE, 2-Port LAN/WAN, XFP
.
Table 25-2. 10GE LSM Load Module Specifications (except NGY)
LSM10G1-01 LSM10GMS-01 LSM10GXL6-01, LSM10GXM3-01

LSM10GL1-011 -02 LSM10GXMR3-
012
# ports 1 1 6 3
Data Rate 10GB 10GB 10GB 10GB

LSM 10GE Family

012
Port CPU Speed 1GHz (G1) 1GHz 1GHz

500MHz (GL1)
Port CPU Memory 512MB (G1) 512MB 512MB 512 MB (GXM)

128MB (GL1) 128 MB (GXMR)
Connector/ XFP or XENPAK/ Integrated XFP XFP XFP

Frequency-Mode X2. See LAN/WAN carrier XFP-CX4
XENPAK card
Connectors on Also XFP-CX4
page 25-34
10GBase-T
Adapter, see
Removable
Carrier Cards on
page 25-16
Also XFP-CX4
and SFP-CX4
Ambient Operating 41°F to 95°F 41°F to 95°F 41°F to 95°F 41°F to 95°F
Temp. Range (5°C to 35°C) (5°C to 35°C) (5°C to 35°C) (5°C to 35°C)
Capture buffer size Up to 384 MB Up to 384 MB Up to 384 MB GXM3: 350 MB

GXMR3: 32 MB
Captured packet size 17-65,535 bytes 17-65,535 bytes 17-65,535 bytes 17-65,535 bytes
Streams per port 256 256 256 256
Advanced streams 256 256 256 256
Preamble size: 8 8 8 8
min-max
Frame size: min-max 17-65,535 17-65,535 17-65,535 17-65,535

(bytes)
Inter-frame gap: 4.0ns - 42sec in 4.0ns - 42sec in 4.0ns - 42sec in 4.0ns - 42sec in
min-max3 3.2ns steps 3.2ns steps 3.2ns steps 3.2ns steps
Inter-burst gap: min- 4.0ns - 42sec in 4.0ns - 42sec in 4.0ns - 42sec in 4.0ns - 42sec in
max 10.0ns steps 10.0ns steps 10.0ns steps 10.0ns steps
Inter-stream gap: 4.0ns - 42sec in 4.0ns - 42sec in 4.0ns - 42sec in 4.0ns - 42sec in
min-max 10.0ns steps 10.0ns steps 10.0ns steps 10.0ns steps
Normal stream frame 0.023fps - full line 0.023fps - full line 0.023fps - full line 0.023fps - full line
rate rate rate rate rate
Advanced stream min Slow: 0.023fps Slow: 0.023fps Slow: 0.023fps Slow: 0.023fps
frame rate4 Fast: 1525fps Fast: 1525fps Fast: 1525fps Fast: 1525fps

25 LSM 10GE Family

012
Latency5 20ns resolution 20ns resolution 20ns resolution 20ns resolution

The ‘No CRC’
option is not
supported.
Table UDF Entries 1M (full) 1M 1M 1M (GXM3)

32K (reduced) 32K (GXMR3)
Max Value List UDF G1: 512K entries 512K entries GXM3-01:
entries 512K entries 512K entries
GL1: GXMR3-01:
8K entries 8K entries
Max Range List UDF G1: GXM3-01:

entries 256 entries GL1: 256 entries
16 entries GXMR3-01:
16 entries
1. Applications are not supported on LSM10GL1-01 (no Layer 4-5 support).
2. The LSM10GMXR3-01 only supports IxNetwork, IxAutomate, and IxExplorer.
3. Packet gap size also depends on the stream mode selected—Fixed or Average.
4. Streams are divided up into two categories: 224 slow speed streams and 32 fast streams.
5. Cancel Intrinsic Latency feature measures and/or removes the latency induced by the test
equipment (not the DUT). See Intrinsic Latency Adjustment on page 25-21.
.
Table 25-3. NGY Load Module Specifications
Feature Extra Performance Full Performance Reduced

Performance
Load Modules LSM10GXM8XP LSM10GXM8 LSM10GXMR8

LSM10GXM4XP LSM10GXM4 LSM10GXMR4
LSM10GXM2XP LSM10GXMR2
LSM10GXM8S LSM10GXMR8S
LSM10GXM8GBT LSM10GXMR8GBT
Number of ports per module 8/4/2 8/4 8/4/2
Line rate 10 Gb/s 10 Gb/s 10 Gb/s
Number of chassis slots per 1 1 1

module
Maximum ports per chassis

LSM 10GE Family

Performance
XM12 High Performance 96/48/241 96/481 96/48/241
XM2 Desktop 16/121/8/4 16/8 16/8/4
Supported transceivers XFP, SFP+, RJ-45 XFP XFP, SFP+, RJ-45

(optical and copper) 10GBASE-T 10GBASE-T
Note: The NGY family of
load modules can support
transceivers that use up to
2.5W of power. Do not use
transceivers beyond 2.5W.
Per-port CPU speed and 1 GHz, 1 GB2 800 MHz/512 MB 400 MHz/128 MB
memory
Per-port capture buffer 512 MB 512 MB 64 MB
Captured packet size 17 bytes—absolute minimum frame size

64 bytes—minimum frame size at line rate
Frame size Minimum: 48 bytes For LSM10GXM8, For LSM10GXMR8,

Maximum: 16,000 LSM10GXM4 LSM10GXMR4
bytes LSM10GXM2 LSM10GXMR2
Minimum Frame Size Minimum Frame Size
at Line Rate: 48 at Line Rate: 48
Minimum Frame Size Minimum Frame Size
- may not be at Line - may not be at Line
Rate: 48 Rate: 48
Maximum Frame Maximum Frame
Size: 4Q: 9216 Size: 4Q: 9216
8 + 1Q: P0: 9216B 8 + 1Q: P0: 9216B
others 2500B others 2500B
Interface protocols 10 GE LAN/WAN 10 GE LAN/WAN 10 GE LAN/WAN
Layer 2/3 routing protocol Yes Yes Yes

emulation
Layer 4-7 application traffic Yes Yes No

testing
Number of transmit flows Billions Billions Billions

per port (sequential values)
Number of transmit flow per 1 million 1 million 32 K

port (arbitrary values)
Number of trackable receive 1 million 1 million 64K

flows
Number of stream 512 512 512

definitions per port

25 LSM 10GE Family

Performance
In packet stream (sequential) or advanced stream (interleaved)

mode, each stream definition can generate millions of unique traffic
flows.
Preamble size: 8 8 8
min-max
Inter-frame gap: 3.2ns - 27.48sec in 3.2ns - 27.48sec in 3.2ns - 27.48sec in

min-max 3.2ns steps 3.2ns steps 3.2ns steps
Inter-burst gap: min-max 3.2ns - 27.48sec in 3.2ns - 27.48sec in 3.2ns - 27.48sec in

3.2ns steps 3.2ns steps 3.2ns steps
Inter-stream gap: 3.2ns - 27.48sec in 3.2ns - 27.48sec in 3.2ns - 27.48sec in

min-max 3.2ns steps 3.2ns steps 3.2ns steps
Normal stream frame rate 0.023fps - full line 0.023fps - full line 0.023fps - full line
rate rate rate
Advanced stream min. Slow: 0.023fps Slow: 0.023fps Slow: 0.023fps

frame rate Fast: 1525fps Fast: 1525fps Fast: 1525fps
Number of streams in 512 512 512

Packet Stream Mode (Non
Data Center Mode)
Number of streams in Fast: 32 Fast: 32 Fast: 32

Advanced Scheduler Mode Slow: 480 Slow: 480 Slow: 480
(Non Data Center Mode)
Number of streams in Fast: 32 Fast: 32 Fast: 32

Advanced Scheduler Mode Slow: 224 Slow: 224 Slow: 224
(Data Center Mode)
Table UDF 1 million entries 1 million entries 32 K
Comprehensive packet editing function for emulating large numbers

of sophisticated flows. Entries of up to 256 bytes, using lists of values
can be specified and placed at designated offsets within a stream.
Each list consists of an offset, a size and a list of values in a table
format.
Max Value List UDF entries 512K entries for 32- 512K entries for 32- 256K entries for 32-
bit and 24-bit, 1M bit and 24-bit, 1M bit and 24-bit, 512K
entries for 8 and 16- entries for 8 and 16- entries for 8 and 16-
bit. bit. bit.
Max Range List UDF entries 512 entries 512 entries 256 entries
Packet flow statistics Track 1 million flows Track 1 million flows Track 64 K flows
Transmit engine Wire-speed packet generation with timestamps, sequence numbers,

data integrity signature, and packet group signatures
Receive engine Wire-speed packet filtering, capturing, real-time latency and inter-
arrival time for each packet group, data integrity, and sequence
checking

LSM 10GE Family

Performance
User defined field features Fixed, increment or decrement by user-defined step, value lists,
range lists, cascade, random, and chained
Filters 48-bit source/destination address, 2x128-bit user-definable pattern

and offset, frame length range, CRC error, data integrity error,
sequence checking error (small, big, reverse)
Data field per stream Fixed, increment (byte/word), decrement (byte/word), random,
repeating, user-specified
Statistics and rates Link state, line speed, frames sent, valid frames received, bytes sent/
(counter size: 64 bits) received, fragments, undersize, oversize, CRC errors, VLAN tagged
frames, 6 user-defined stats, capture trigger (UDS 3), capture filter
(UDS 4), user-defined stat 5, user-defined stat 6, 8 QoS counters,
data integrity frames, data integrity errors, sequence checking
frames, sequence checking errors, ARP, and ping requests and
replies
Error generation CRC (good/bad/none), undersize, oversize
Latency measurements 20 ns standard

10 ns user-selectable
Latency self-calibration Ability to calibrate and remove inherent latency from any MSA-
compliant 10GbE XFP transceivers, including unsupported
transceivers
Transmit line clock Ability to adjust the parts per million (ppm) line frequency over a
adjustment range of:
• LAN mode: -105 to +105 ppm3
• WAN mode: -30 to +30 ppm
IPv4, IPv6, UDP, TCP Hardware checksum generation and verification
Frame length controls Fixed, random, weighted random, or increment by user-defined step,
random, weighted random
Operating temp. range 41°F to 95°F (5°C to 35°C), ambient air4
1. XM12 High Performance chassis (941-0009) is required for 80 or more ports of 10 GbE
NGY XFP or SFP+ 8-port, load modules to be installed in a single chassis. A field re-
placeable power supply upgrade kit (943-0005) is available for the XM12 chassis (941-
0002) to convert it to the high-performance version. Up to ten 8-port NGY 10GBASE-
T full performance load modules are supported in an XM12 High Performance chassis,
and up to eight 8-port NGY 10GBASE-T full performance load modules are supported
in a standard XM12 chassis). The XM2 chassis (941-0003) supports up to twelve ports
of 10GBASE-T full performance load modules.
2. The LSM10GXM8XP, LSM10GXM8S, and LSM10GXM8GBT use a high perfor-
mance 800MHz processor with additional layer 2 cache.
3. For 10GBASE-T interfaces on NGY the ppm does change the data rate, but does not
change the bit period due to phy chip limitations.

25 LSM 10GE Family
4. When an NGY load module is installed in an XM12 or XM2 chassis, the maximum op-
erating temperature of the chassis is 35°C (ambient air).
Port LEDs
Note: The NGY 10GBASE-T load module has only 2 port LEDs:
• Rx/Error: Same as Rx/Error in the following table
• Tx/Link: Combines the Link and Tx/Pause functions. Solid green = link;
blinking green = transmit; red = flow control.
Each 10GB port incorporates a set of LEDs, as described in the following figure.
Table 25-4. 10GE LSM Port LEDs
LED Label Usage

forced Link Up state, red if link is down. Link may be down
due to no signal or no PCS lock.
Tx/Pause Green while data is transmitted. Red while flow control

frames are received. Off if no traffic is passing in either
direction.
Note: For NGY load modules LSM10GXM(R)8 and
LSM10GXM(R)4: green indicates that Tx is active and
frames being sent; red indicates Tx is paused; off indicates
Tx is not active.
Rx/Error Green while data is received. Red on any Ethernet error.

Off if no frames are received.
Note: For NGY load modules LSM10GXM(R)8 and
LSM10GXM(R)4: green indicates valid Rx frames are
being received; red indicates error frames being received;
off indicates no frames being received..
LASER ON Green when the port’s laser is turned on. Off otherwise.
Detect Green when valid plug in module is detected, red

otherwise.
Power Green when power is on, red if power fault occurs.
Option1/2 N/A
Trigger See Trigger Out Values on page 25-15.
allow the DUT to phase-lock with the interface. When running off an external

LSM 10GE Family
clock, the clock input signal must meet the requirements listed in the following
figure to ensure proper performance of the load module.
The clock in/out electrical interface parameters are also defined in the following
figure.
Clock Frequency 156.25 MHz ±100ppm

Input
Duty cycle 50%
Amplitude Vpp = 4.0
Clock Frequency 156.25MHz +/-105PPM (Programmable

Output PPM in Internal Clock Mode)
LSM10GXM8-01 and variations: 156.25MHz
(LAN) or 155.52MHz (WAN) +/-30PPM
(Programmable PPM in Internal Clock Mode)
Amplitude 0.7Vpp min into 50 ohms, AC coupled output
Edge rates 200ps to 340ps (20% to 80%) into 50 Ohms
Impedance 50 ohms +/-5%, AC coupled
the PLL is approximately 1 kHz.
Trigger Out Values The signals and LEDs available on the trigger out pins for these cards are
described in the following table.
Table 25-6. 10GE LAN Trigger Out Signals
Pin/LED Value
Trigger Out Single ended output that pulses high for

approximately 1.18s shortly after the Central
FPGA is loaded, and following an event defined
by UDS1.
Voltage output = 3.3V for high, 0V for low.
Trigger LED Pulses following an event defined by UDS1.

25 LSM 10GE Family
Removable Carrier The 10GE10G1-01 and the LSM10GL1-01 load modules have removable carrier
Cards cards available for use:
• The XENPAK-ADAP-01 carrier card for XENPAK transceivers, shown in
• The XFP-ADAP-01 LAN only carrier card for XFP transceivers (not
shown).
• The XFP-ADAP-02 LAN/WAN carrier card for XFP transceivers (shown
being inserted into the LSM load module in Figure 25-10 on page 25-18.
• X2 carrier card for X2 Transceiver (shown with transceiver installed in
Figure 25-9 on page 25-17).
• 10GBase-T-ADAP-01 10 Gigabit Ethernet adapter module (shown in
Figure 25-11 on page 25-19).
Figure 25-8. XENPAK-ADAP-01 Carrier Card

LSM 10GE Family
Figure 25-9. X2 Carrier Card with X2 Transceiver

25 LSM 10GE Family
Figure 25-10.XFP-ADAP-02 Carrier Card

LSM 10GE Family
Figure 25-11. 10GBase-T Adapter Module
Carrier Card Installation
To install the carrier card, do the following:

1. Insert the card into the opening in the 10GE LSM module.
2. Slide the card along the guide rails until it connects to the load module.
3. Tighten the screws so that the carrier card is firmly in place. Do not over
tighten the screws (no more than a quarter turn once flush with the card
front).
The carrier card can be installed either before or after the load module is
connected to the chassis. It is best not to attach the transceiver to the carrier card
until the card is installed in the load module. Load modules should be screwed
down in the chassis before removing or installing a carrier card, to prevent from
accidentally dislodging a load module from the chassis backplane.
Note: The carrier cards do not come with the required transceivers. They must
be purchased separately.
XENPAK/XAUI The LSM10G1-01 and LSM10GL1-01 load modules have XAUI and XENPAK
Connectors connectors available. See XAUI Connectors on page 25-28 and XENPAK
Connectors on page 25-34 above for more information on XENPAK connectors.
These connectors are only applicable when the XENPAK carrier is being used.

25 LSM 10GE Family
Statistics Statistics for 10GE LSM cards (except NGY), under various modes of operation
may be found in Table B-23 on page B-118. Statistics for NGY load modules
may be found in Table B-24 on page B-127.
NGY Fault Handling IEEE Requirements
IEEE 802.3ae, section 46.3.4 defines how a Reconciliation Sublayer (RS) shall
respond to Local and Remote Faults. Response to a Local Fault is to immediately
cease sending traffic on the transmit data path (even if doing so truncates a
frame) and to send continual Remote Faults. Response to a Remote Fault is to
stop sending MAC data (completing any frame that is being transmitted) and to
send continual idles.
NGY Operation
NGY load modules have a single statistic for Faults called Link Fault State. This
statistic is real-time and indicates the current state of the port’s Reconciliation
Sublayer (RS) state machine. The possible statistics values are:
• No Fault
• Local Fault
• Remote Fault
Features that force deviation from IEEE spec
Note: In general, if a NGY port appears to be transmitting according to the

Frames Sent statistic, be aware that Link Fault State may override this.
Tx Ignores Rx Link Faults
This feature is enabled through the Link Fault Signaling tab of Port Properties.
When the feature is enabled, the Fault statistic continues to indicate the RS state
of the port; however, the transmit-side response behaves as if no fault was
received. That is to say, Remote Faults are not sent as a response to Local Fault
and Idles are not forced as a response to Remote Fault, even though Link Fault
State indicates the board is in a Fault state.
Transmit Ignores Link Status
This feature is enabled through the Transmit Modes tab of Port Properties. When
the feature is enabled, a port is permitted to transmit under conditions that would
normally inhibit transmit. For instance, a port that has no link and is not in
diagnostic loopback appears in IxExplorer as red color, and is normally not
permitted to transmit. Enabling this feature allows transmit. When the feature is
enabled, the statistic called Link State indicates ‘Ignore Link’.
Note that if the port is in Fault, enabling this feature and forcing transmit may
result in misleading results. The port shown in the following stat view (Figure
25-12) is ignoring link (see Link State statistic), is in Remote Fault (see Link

LSM 10GE Family
Fault State statistic), yet appears to be transmitting (see Frames Sent Rate
statistic). The reality is that no frames are actually leaving the port because the
port is in Remote Fault. This is because the block that maintains the transmit
statistics is located before the block that forces idles as a response to Remote
Fault.
Figure 25-12. Statistic View for NGY, Ignore Link Status
Intrinsic Latency This option, when present and enabled, reduces the measured latency by the
Adjustment amount of latency that is induced by the test equipment itself (not the DUT). For
a specific transceiver, the system retrieves its pre-determined latency value and
subtracts this from the measured overall latency. For an ‘unknown’ transceiver
(not previously measured), it calculates and stores the intrinsic latency value.
On the General tab in Port Properties, the Latency Calibration option is only
enabled for cards with transceivers that have not been pre-measured for intrinisic
latency by Ixia. The Latency Calibration option is grayed-out if any one of the
following conditions are present:
• There is no carrier.
• There is no transceiver.
• The transceiver is XFP or XAUI (which do not need to be calibrated).

25 10GE LAN Family
• The transceiver is XENPAK or X2 and a value is found for it in the list of

pre-calibrated values.
The Latency Calibration option is enabled if the transceiver is XENPAK or X2

but no pre-calibrated value is found in the stored list. The Latency Calibration
option is also enabled for transceivers that you have previously calibrated, so that
the calibration measurement may be repeated (if desired).
Clicking the Latency Calibration option runs a Tcl script that measures intrinsic
latency and stores the value in an .xml file. The .xml file contains the values that
you have produced and saved. Each value is identified for a specific transceiver
(per manufacturer, model, and serial number). You can run the calibrate process
repeatedly with the same transceiver (if desired). Each new measurement
overwrites the previous one for that transceiver.
Running the calibration measurement puts the port into a special loopback mode
to measure intrinsic latency. When done, the port is put back into default normal
mode. Any port configuration you have set before calibrating intrinsic latency, is
lost as the port reverts to a default configuration.
The Enable check box is grayed out when no value exists in the system for the
specific transceiver. If a value exists (in the .xml file) then the Enable check box
is available. Select the check box to enable the intrinsic latency adjustment.
After the intrinsic latency adjustment has been done, you may want to refresh the
chassis or close and reopen the Port Properties dialog.
Note: The LSM10GMS-01 load module always compensates for intrinsic

latency—it is not optional. Also, this load module does not support the’No CRC’
option. Any imported stream with No CRC enabled is Forced Valid to ‘Bad
CRC’.
10GE LAN Family

Part Numbers The currently available LAN family part numbers are shown in the following
table. Items without a Price List Names entry are no longer available.
Table 25-7. 10GE LAN Load Modules
LM10GELAN LM10GE223F 10GBASE-LR (LAN), 1-port, 1310nm,

singlemode
LM10GE224F 10GBASE-ER, (LAN) 1-port, 1550nm,

singlemode
LM10GELAN-M LM10GE223M 10GBASE-LR (LAN), 1-port, 1310nm,

singlemode, manufacturing mode
LM10GE224M 10GBASE-ER (LAN), 1-port, 1550nm,

singlemode, manufacturing mode

10GE LAN Family
Specifications The limitations of -M, Layer 2/3 and Layer 7 cards are discussed in Ixia Load
Table 25-8. 10GB LAN Load Module Specifications
10GBASE-R (LAN)
# ports 1
-M Card Available Y
Layer2/Layer3 Card Available? N
Layer 7 Card Available N
Data Rate 10GB
Connector/Wavelength-Mode SC/850 multimode, 1310nm /1550nm

singlemode
Capture buffer size 32MB
Captured packet size 24-65,000 bytes
Streams per port 255, 32 (-M version)
Advanced streams 160, 16 (-M version)
Preamble size: min-max 8
Frame size: min-max 24-65,000
Inter-frame gap: min-max 4.0ns - 42sec in 3.2ns steps
Inter-burst gap: min-max 4.0ns - 42sec in 10.0ns steps
Inter-stream gap: min-max 4.0ns - 42sec in 10.0ns steps
Normal stream frame rate 0.023fps - full line rate
Advanced stream min frame rate1 Slow: 0.023fps

Med: 95fps
Fast: 1525fps
Latency 20ns resolution
1. Streams are divided up into three categories: 144 slow speed streams,
8 medium streams and 8 fast streams.
The LAN-M boards includes all of the features of the LAN board with the
following exceptions:
• No support for routing protocols
• No real-time latency, but timestamps are included
• 32 streams in packet stream mode
• 16 streams in advanced scheduler mode
• No configurable preamble
When performing sequence checking, no more than 8192 packet group IDs
should be used.

25 10GE LAN Family
Port LEDs Each 10GB LAN port incorporates a set of LEDs, as described in the Table 25-9.
Table 25-9. 10GE LAN Port LEDs
LED Label Usage
Link Green if Ethernet link has been established, red otherwise.

Link may be down due to no signal or no PCS lock.

direction.

Trigger See below.
Option Reserved for future use.
Table 25-10. 10GE LAN Trigger Out Signals
Pin/LED Value
Trigger Out A Low (0V) on Rx Pause Request, high (+5V)

otherwise.
Trigger Out B Low (0V) on User Defined Statistic 1 true, high

(+5v) otherwise.
Trigger LED Pulses each time a Pause Request is detected.
Optical The optical characteristics for the 10GE LAN cards is described in Table 25-11.
Specifications Table 25-11. 10GE Optical Specifications
Specification 10GBASE-SR 10GBASE-LR 10GBASE-ER

(LAN) 850nm (LAN) 1310nm (LAN) 1550nm
Tx Power (dBm) -5 to -1 -6 to 2 -4 to 0
Rx Sensitivity -7 to -1 -11 to -1 -5 to 2
(dBm)
Safety Class 1 Laser Class 1 Laser Class 1 Laser
Statistics Statistics for 10GB cards, under various modes of operation may be found in
Table B-21 on page B-104 and Table B-22 on page B-111.

XAUI Family
XAUI Family
Part Numbers The XAUI family part numbers are shown in the following table.
Table 25-12. 10GE XAUI Load Modules
LM10GEXAUI LM10GE500F1 10GBASE (XAUI), 1 port
LM10GEXAUI+ LM10GE500F1B 10GBASE (XAUI), Ethernet/BERT, 1 port

BERT
LM10GEXAUI LM10GE500M1B 10GBASE (XAUI), BERT, 1 port

BERT only
Cables CAB10GE500S1 XAUI cable, 20 inch, standard pinout
CAB10GE500S2 XAUI cable, 40 inch, standard pinout
BOB10GE500 XAUI SMA break-out box
CON10GE500 XAUI Fujitsu MicroGiGa connector
LPG10GE500 XAUI front panel loopback connector
Table 25-13. 10GB XAUI Load Module Specifications
10GBASE (XAUI) 10GBASE (XAUI/

BERT)
# ports 1 1
-M Card Available N N
Layer2/Layer3 Card N N
Available?
Layer 7 Card Available N N
Data Rate 10GB N/A
Connector/Frequency- See XAUI Connectors See XAUI Connectors

Mode on page 25-28 on page 25-28
Capture buffer size 32MB N/A
Captured packet size 24-65,000 bytes N/A
Streams per port 255 N/A
Advanced streams 160 N/A
Preamble size: min-max 8 N/A
Frame size: min-max 24-65,000 N/A

25 XAUI Family
Table 25-13. 10GB XAUI Load Module Specifications
10GBASE (XAUI) 10GBASE (XAUI/

BERT)
Inter-frame gap: min-max 4.0ns - 42sec in 3.2ns N/A

steps
Inter-burst gap: min-max 4.0ns - 42sec in 10.0ns N/A

steps
Inter-stream gap: min-max 4.0ns - 42sec in 10.0ns N/A

steps
Advanced stream min Slow: 0.023fps

frame rate1 Med: 95fps
Fast: 1525fps
Latency 20ns resolution N/A
1. Streams are divided up into three categories: 144 slow speed

streams, 8 medium streams and 8 fast streams.
XAUI accessories are discussed in Appendix A, XAUI Connector Specifications.
Port LEDs Each 10GB XAUI port incorporates a set of LEDs, as described in the following
table.
Table 25-14. 10GE XAUI Port LEDs
LED Label Usage


direction.

Trigger See below.

XAUI Family
described in the following figure.
Table 25-15. 10GE XAUI Trigger Out Signals
Pin/LED Value

otherwise.

(+5v) otherwise.
Clock In/Out The XAUI load module provides SMA coaxial connectors for clock input and
clock output to allow the DUT to phase-lock with the XAUI interface. When
running off an external clock, the clock input signal must meet the requirements
listed in Table 25-16 to ensure proper performance of the load module.
Table 25-16. XAUI Reference Clock Input Requirements
Frequency 156.25 MHz ±100ppm
Amplitude 0.9 Vpp minimum, into 50 Ω
Edge rates (20% to 80%) 600ps maximum, into 50 Ω
The clock in/out electrical interface parameters are defined in Table 25-17.
Table 25-17. XAUI Clock In/Out Electrical Interface Parameters
Clock Connector Female SMA

Input
Absolute max input 6V (DC plus half AC peak-to-peak
Impedance 50 ohm ± 5%, AC coupled

Clock
Output Amplitude 0.9 Vpp minimum, into 50 Ω. (1.5 Vpp
typical)
Edge rates 200ps to 340ps (20% to 80%) into 50Ω
Duty cycle 45% to 55%
Frequency 156.25 MHz ±20ppm (internal clock mode)

25 XAUI Family
XAUI Connectors The following connectors and adapters are available for the XAUI Load Modules
and are discussed in Appendix A, XAUI Connector Specifications.
• Standard Connector Specifications: the signals carried on the Load Module’s
XAUI connector.
• Front Panel Loopback Connector: a connector used to loopback XAUI
signals at the external connector.
• Standard Cable Specification: the CAB10GE500S1 (20 inch) and
CAB10GE500S2 (40 inch) cables.
• SMA Break-Out Box: the BOB10GE500 SMA break-out box.
MDIO
A Management Data Input/Output (MDIO) interface is provided to you. The Ixia

Load Module acts as the Station Management entity (STA), and can control one
or more MDIO Manageable Devices (MMD) in the users system. Multiple
MMDs can be attached to the interface. You can set/read the MDIO control/
status registers inside a MMD through a graphical user interface.
The connector used for the MDIO interface is a 15-pin female D-sub and
provides with the ability to add up to two external Mii interfaces compliant to
either 802.3 clause 22 or 802.3ae clause 45. The connector pin assignments, Mii
Interface, signal names, and functional descriptions are listed in Table 25-18.
Table 25-18. MDC/MDIO Connector Pin Assignments
Pin No. Mii Interface Signal Name Functional Description
1 External 2 DIR Data direction control.
2 External 2 MDC Clock.
3 External 2 MDIO Bi-directional data.
4 External 2 +5V +5Vdc supply.
5 External 1 +5V +5Vdc supply.
6 External 1 MDIO Bi-directional data.
7 External 1 MDC Clock.
8 External 1 DIR Data direction control.
9-15 GND GND Ground

XAUI Family
Figure 25-13.MDC/MDIO D-sub Connector Pin Assignments
WARNING: The MDIO on the Ixia XAUI Load Module is 3.3V while the Ixia
XENPAK Load Module, when used with the adapter for XAUI, is 1.2V. The
reason for the difference is that the XENPAK MSA requires 1.2V for MDIO
whereas most XAUI SerDes chips require 3.3V (LVTTL). Therefore, when using
the XAUI Load Module to test a XENPAK transceiver or SerDes, which require
1.2V, a level shifter is needed to convert 3.3V to 1.2V.
The MDIO/MDC interface has a clock line (MDC) and bi-directional data line
(MDIO) as defined in IEEE 802.3ae. In addition to these, a +5Vdc supply, and
data direction control line (DIR) are provided to make interfacing easier for you.
The +5Vdc output is intended to power buffers and/or optocouplers at the user-
end of the cable. This supply can be turned ON or OFF under software control
through the GUI.
The +5Vdc supply is OFF when the chassis is initially powered-up, or following
a reset.
For more information on XAUI connectors, see Appendix A, XAUI Connector

Specifications.

25 XENPAK Family
XENPAK Family
The LM10GE700P3 family is referred to as the XENPAK load modules. Each
card accepts a XENPAK transceiver, or with an appropriate carrier card accepts
an XPAK or X2 transceiver. Five variants are available, which feature Ethernet
and/or BERT modes and full or manufacturing mode.
Part Numbers The XENPAK family part numbers are shown in Table 25-19.
Table 25-19. 10GE XENPAK Modules
LM10GEXENPAK LM10GE700F1 10GE (XENPAK), Ethernet, 1-

port
LM10GE700F1-P 10GE (XENPAK), Ethernet, 1-

port, PowerPC with 256MB of
processor memory.
LM10GEXENPAK-M LM10GE700M1 10GE (XENPAK), Ethernet, 1-

port, manufacturing mode
LM10GEXENPAK+ LM10GE700F1B 10GE (XENBAK), Ethernet/

BERT Bert, 1-port
LM10GEXENPAK LM10GE700M1B 10GE (XENPAK), BERT only, 1-

BERT only port, manufacturing mode
LM10GEXENPAK- LM10GE700M2B 10GE (XENPAK),

MA+BERT Ethernet+BERT, 1-port,
manufacturing mode
Transceivers XENPAK-LR XENPAK Transceiver - 1310nm

LAN, 10GBASE-LR
XENPAK-SR XENPAK Transceiver - 850nm

LAN, 10GBASE-SR
XENPAK-ER XENPAK Transceiver - 1550nm

LAN, 10GBASE-ER
XENPAK-CX4 XENPAK Transceiver - CX4

Interface (10GBASE-CX4)
Cables CAB10GE-CX4 CX4-to-CX4 cable, 1 meter
CX410GE500 CX4 to XENPAK adapter
FXN10GE500 XAUI Fujitsu to XENPAK

Adapter

XENPAK Family
Table 25-20. 10GB Load Module Specifications—Part 3
10GBASE (XENPAK)
# ports 1
-M Card Available Y
Layer2/Layer3 Card Available? N
Data Rate 10GB
Connector/ See XENPAK

Frequency-Mode Connectors on page
25-34
Captured packet size 24-65,000 bytes
Streams per port 255, 32 (-M version)
Advanced streams 160
Frame size: min-max 24-65,000
Inter-frame gap: 4.0ns - 42sec in 3.2ns

min-max steps
Inter-burst gap: min-max 4.0ns - 42sec in

10.0ns steps
Inter-stream gap: 4.0ns - 42sec in

min-max 10.0ns steps

Med: 95fps
Fast: 1525fps
Latency 20ns resolution
1. Streams are divided up into three categories:

144 slow speed streams, 8 medium streams and
8 fast streams.
The -M load modules includes all of the features of the non-M board with the
following exceptions:
• No support for routing protocols
• No real-time latency, but timestamps are included
• 32 streams in packet stream mode
• 16 streams in advanced scheduler mode

25 XENPAK Family
• No configurable preamble
When performing sequence checking, no more than 8192 packet group IDs
should be used.
Port LEDs Each 10GB port incorporates a set of LEDs, as described in the following tables.
Table 25-21. 10GE XENPAK Port LEDs
LED Label Usage


direction.

Trigger See below.
Trigger Out Values Trigger out values depend on the particular board type.
XENPAK Load Modules
The signals and LEDs available on the trigger out pins for these cards are
described in Table 25-22.
Table 25-22. 10GE XENPAK 1-Slot Trigger Out Signals
Pin/LED Value

otherwise.

(+5v) otherwise.

XENPAK Family
Clock In/Out The load module provides SMA coaxial connectors for clock input and clock
output to allow the DUT to phase-lock with the interface. When running off an
external clock, the clock input signal must meet the requirements listed in Table
25-23 to ensure proper performance of the load module.
Table 25-23. Reference Clock Input Requirements
Frequency 156.25 MHz ±100ppm
Amplitude 0.9 Vpp minimum, into 50 Ω
Edge rates (20% to 80%) 600ps maximum, into 50 Ω
Clock Connector Female SMA

Input
Absolute max input 6V (DC plus half AC peak-to-peak

Clock
Output Amplitude 0.9 Vpp minimum, into 50 Ω. (1.5 Vpp
typical)
Frequency 156.25 MHz ±20ppm (internal clock mode)

25 XENPAK Family
XENPAK Power Sequencing Specification

Connectors
The Xenpak 2.1 MSA does not specify any particular power sequencing for the
various Xenpak power supply rails (3.3V, 5V, and APS).
When Xenpak Power is enabled, power sequencing is as follows:

• The 5V rail comes up first, with a ramp-up time of approximately 2.25 ms.
• The 3.3V and APS rails both start to come up about 500 us after 5V rail is up.
• The 3.3V supply has a ramp-up time of approximately two milliseconds.
• The APS supply ramp-up time varies, according to level required by APS
Set resistor, but will be no more than two milliseconds. When no Xenpak
module is inserted into the Load Module, APS voltage is less than 150 mV.
Reset
Hardware asserts a Reset by bringing Xenpak connector pin 10 low whenever

either of the following conditions is true:
• The Xenpak module is not inserted into the load module; that is, Xenpak pin
14 is high.
• Xenpak power is turned off.
The hardware continues to assert Reset until both of these items are false. Once
Xenpak Power is asserted, or if a Xenpak is hot-plugged, the system waits 5
seconds for Xenpak initialization (per MSA 2.1). Reset is then de-asserted, and
the system waits an additional 500 ms for any vendor-based reset management to
complete initialization. After this final 500 ms delay, the load module assumes
the Xenpak module is ready for MII access or to transmit and receive.

XENPAK Family
XAUI Fujitsu to XENPAK Adapter
The XAUI Fujitsu to XENPAK Adapter (P/N FXN10GE500) is shown in Figure

25-14.
Figure 25-14.XAUI Fujitsu to XENPAK Adapter
70-pin XENPAK Connector
MDIO Pins
Fujitsu Connector
The MDIO pins are pictured and described in Figure 25-15 and Table 25-25.
Figure 25-15.MDIO Pins for XAUI Fujitsu to XENPAK Adapter
Table 25-25. MDIO Pin Assignments for XAUI Fujitsu to XENPAK Adapter
Pin Signal
1 PU-5V
2 PU-3.3V
3 PU-APS
4 LASI (GND)
5 RESET
6 TX ON/OFF

25 XENPAK Family
Table 25-25. MDIO Pin Assignments for XAUI Fujitsu to XENPAK Adapter
Pin Signal
7 MDIO
8 MDC
9 GND
This MDIO pinout is the same for the CX4 to XENPAK adapter (P/N
CX410GE500).

Specifications.
CX4 to XENPAK Adapter
The CX4 to XENPAK Adapter (P/N CX410GE500) is shown in Figure 25-16.
Figure 25-16.CX4 to XENPAK Adapter
70-pin XENPAK Connector
CX4
MDIO Pins
Fujitsu Connector
The MDIO pins are pictured and described in Figure 25-15 and Table 25-25.

Specifications.

Chapter 26: IXIA 10GE LAN/WAN
26 and OC 192 POS
Load Modules
Overview
Ixia offers two families of load modules that operate in multiple modes, as
specified in Table 26-1.
Table 26-1.Operating Modes Available for Multimode Cards
Family OC-192 BERT 10GE 10GE FEC VCAT/

POS WAN LAN Channel
ized
10G MSM X X X X
OC-192 Triple Mode X X X
UNIPHY X X X X X
Full specifications for each family may be found at:

• 10G MSM Family on page 26-1
• OC-192c Triple Mode Family on page 26-6
• UNIPHY Family on page 26-12
10G MSM Family

The 10G MSM load module family consists of a UNIPHY LM Load module
which supports SONET and Ethernet at 10G rates. Modes supported on this
board include POS, WAN, and LAN. For POS there is additional feature support
such as DCC, RPR, and SRP.
Figure 26-1 on page 26-2 displays the 10G MSM module.

IXIA 10GE LAN/WAN and OC 192 POS Load Modules
26 10G MSM Family
Figure 26-1. MSM10G1-02 Load Module
Note: Due to power requirements, only one MSM module can be used in a 250
or 400T chassis. Other modules can be used with the MSM in the same
chassis, but only one CPM1000T8 at a time (except the CMP1000T8 module,
which has the same limitation).

10G MSM Family
Part Numbers The MSM family part numbers are shown in Table 26-2.
Table 26-2. 10G MSM Modules
MSM10G1-02 944-0012 10GE OC192 load module, 1-

port Multi Services Module,
supports 10GE LAN/WAN and
optional OC-192c POS (order
OPTOC192POS). Full features:
supports routing and Linux-
based applications. Requires
an XFP transceiver. Purchase
options include XFP-1310 and
XFP-1550. Note: Maximum one
(1) MSM10G1-02 load module
permitted per IXIA 400T
chassis .
945-0005 SW-VCAT-SONET
configuration option, SONET
Virtual Concatenation (VCAT)
Option license per port.
Includes support for LCAS and
GFP-F protocols. Requires
purchase of a supported load
module (see 945-0003
MSM2.5G1-01 or 944-0012
MSM10G1-02)
945-0002 SW-RPRSRP-SONET, OC-48/

OC-192 configuration option,
SONET RPR and SRP stream
generation and protocol
support, license per port.
Requires purchase of a
supported load module (see
LMOC192xx, LM10GUxF,
LMOC48xx, 945-0003
MSM2.5G1-01, or 944-0012
MSM10G1-02)
OPTOC192POS 10 Gigabit Ethernet OC-102

POS configuration option for
944-0012 (MSM10G1-02) and
LM10GUxx load modules.
Specifications .
Table 26-3. 10G MSM Load Module Specifications
MSM10G1-02
# ports 1
-M Card Available No
Layer2/Layer3 Card Available? Yes

26 10G MSM Family
Table 26-3. 10G MSM Load Module Specifications

MSM10G1-02
Layer 7 Card Available No
Data Rate 10GB
Connector/ XFP 1310nm or 1550nm

Wavelength-Mode Single or pluggable
Capture buffer size Up to 384 MB
Captured packet size 17-65,535bytes
Streams per port 256
Advanced streams 256
Frame size: min-max (bytes) 17-65,535
Inter-frame gap: 4.0ns - 42sec in 3.2ns steps

min-max1
Inter-burst gap: min-max 4.0ns - 42sec in 10.0ns steps
Inter-stream gap: 4.0ns - 42sec in 10.0ns steps

min-max

Fast: 1525fps
Latency3 20ns resolution
1. Packet gap size also depends on the stream mode selected, Fixed or
Average.
2. Streams are divided up into two categories: 224 slow speed streams
and 32 fast streams.

10G MSM Family
3. When performing latency measurements in POS mode, the follow-

ing restrictions apply:
The minimum frame size should be 80 bytes for latency measurements to
be supported at line rate. On the MSM10G, there is only one packet group
mode (wide packet groups) . Two different scenarios apply:
a: If sequence checking is enabled, then the number of packet group IDs is
limited in this way:
i: When Wide Bin Mode (on the Wide Packet Groups page) is not
enabled = 65536.
ii: When Wide Bin Mode is enabled = 524288.
b: If sequence checking is not enabled, then the number of packet group IDs
is limited in this way:
i: When Wide Bin Mode (on the Wide Packet Groups page) is not
enabled = 65536.
ii: When Wide Bin Mode is enabled = 2097152.
Port LEDs Each 10G MSM port incorporates a set of LEDs, as described in the following
table.
Table 26-4. 10G MSM Port LEDs
LED Label Usage
LASER ON Green when the port’s laser is turned on. Blank otherwise.
Pause Green when transmit is paused, blank when powered off.
PPP/Link Green in link up condition, Red in link down condition, blank

indicates loopback mode enabled.
Tx Green if transmit is active and frames are being sent, blank

otherwise.
LOS Green when signal level is good, Red when loss of signal
occurs, blank if no transceiver detected.
Option N/A
Trigger Green when Trigger A condition occurs, Red for

Temperature Fault, blank otherwise.
Error Red when module in error state (fault condition), blank

otherwise.
Rx Green indicates valid receive frames, Red indicates errored

frames received, blank when no frames received.
LOF Green when valid framing occurs, Red when Loss of Frame
occurs.
allow the DUT to phase-lock with the interface. When running off an external

26 OC-192c Triple Mode Family
clock, the clock input signal must meet the requirements listed in Table 26-5 to
ensure proper performance of the load module.
Table 26-5. Clock Input Specifications
Connector SMA
Frequency SONET: 155.52 MHz ±20ppm

10GE: 161.132 MHz ±-100ppm
Amplitude 1.1 Vpp minimum, into 50 Ω, AC coupled
Table 26-6. Clock Output Specifications
Connector SMA
Frequency SONET: 155.52 MHz ±20ppm

10GE: 161.132 MHz ±-100ppm
Amplitude 500m Vpp minimum, 600 Vpp typical into 50 Ω
Trigger Out The signals and LEDs available on the trigger out pins for these cards are
Table 26-7. 10G MSM Trigger Out Signals
Pin/LED Value
Trigger Out 10nS active high pulse on trigger
Trigger LED Indicates Trigger, Pause Frame received in

10GE mode.
Statistics Statistics for 10G MSM cards, under various modes of operation may be found in
Table B-25 on page B-135.
OC-192c Triple Mode Family

The OC-192c Triple Mode family of load modules implements Optical Carrier
interfaces that run at OC192 speeds. The interface operates in concatenated

mode, as opposed to channelized mode. One of the modules in this family (the
LMOC192cPOS) is shown in Figure 26-2.
Figure 26-2. LMOC192c Load Module
Part Numbering The OC192 cards come with a number of options. All part numbers are of the
form:
LMOC192HTOS or
LMFOC192HTOS
where H is the hundreds designator, T is the tens designator, O is the ones

designator, and S is the suffix.
LMF boards have no fiber optic interface. It allows for quick validation of
serializer and deserializer designs for WAN Packet over SONET/SDH products
operating at the STS-192c/STM-64 level. The LMF interface is a 300 pin
MegaArray BERG connector, which is an industry standard MSA interface and
is compliant per OIF1999.102.8, SFI-4 specification. A reference clock can be
supplied through this interface ranging in frequency from 25 MHz to 622 MHz.
The part numbers for these load modules are shown in Table 26-8. Items without
a Price List Names entry are no longer available.
Table 26-8. OC-192c Load Modules
LMOC192cPOS POS, 1-port, intermediate reach

(SR1), 1310nm, singlemode.
POS, 1-port, intermediate reach,

1310nm, singlemode.
POS, 1-port, intermediate reach,

1550nm, singlemode.
POS, 1-port, no optics.
LMOC192cVSRPOS LMOC192168 POS, 1-port, VSR optics, parallel

interface.
LMOC192cBERT BERT, 1-port, intermediate reach,

1310nm, singlemode.
BERT, 1-port, intermediate reach,

1550nm, singlemode.
LMOC192cVSR- BERT, 1-port, VSR optics, parallel

BERT interface.

Table 26-8. OC-192c Load Modules
LMOC192cPOS+ POS with BERT, 1-port, intermediate

BERT reach, 1310nm, singlemode.
POS with BERT, 1-port, intermediate

reach, 1550nm, singlemode.
LMOC192cVSR- LMOC192468 POS with BERT, 1-port, VSR optics.

POS+BERT
LMOC192cPOS+ POS+WAN, 1-port, intermediate

WAN reach, 1310nm, singlemode.
LMOC192cPOS+ POS+BERT+WAN, 1-port,

BERT+WAN intermediate reach, 1310nm,
singlemode.
POS+BERT+WAN, 1-port,
intermediate reach, 1550nm,
singlemode.
LM10GEWAN 10GBASE-LW (WAN), 1-port,

1310nm, singlemode.
10GBASE-EW (WAN), 1-port,

1550nm, singlemode.
Options SW-DCCSONET DCC SONET support.
945-0002 SW-RPRSONET SW-SRPSONET

SRP SONET and RPR SONET
support.

Specifications The load module specifications are contained in Table 26-9. Note that the -M
modules are not included in the table; their limitations versus the non-M version
are discussed in Ixia Load Modules on page 1-5.
Table 26-9. OC192 Load Module Specifications
LMOC192cPOS LMOC192c LMOC192c

LMOC192cPOS+ BERT POS+BERT1
WAN
# ports 1 1 1
-M Card Available N N N
Layer2/Layer3 Card N N N
Available?
Layer 7 Card Available N N N
Data Rate 1-100% of OC192 N/A

speeds
Connector/ SC/1310nm or SC/1310nm or SC/1310nm

Wavelength-Mode 1550nm 1550nm or 1550nm
Singlemode Singlemode Singlemode
Capture buffer size 32MB N/A
Captured packet size 33-64k N/A
Streams per port 255 N/A
Flows per port N/A N/A
Advanced streams 160 N/A
Preamble size: min- N/A N/A

max
Frame size: min-max 54-65535 N/A
Inter-frame gap: min- N/A2 N/A

max
Inter-burst gap: min- 1us - 42sec N/A

max
Inter-stream gap: min- 1us - 42sec N/A

max
Normal stream frame 0.023fps - full line

rate rate
Advanced stream Slow: 0.023 -

frame rate3 2083333 fps
Med: 95fps - full
line rate
Fast: 1525fps - full
line rate
Latency 20ns resolution N/A

1. Refer to the LMOC192cPOS and LMOC192cBERT columns for

the characteristics of this card when its port is in POS or BERT
mode, respectively.
2. The inter-frame gap is indirectly controlled by the frame rate.
3. Streams are divided up into three categories: 144 slow speed

streams, 8 medium streams and 8 fast streams.
The Ixia VSR modules, which were developed in accordance with the OIF
Implementation Agreement VSR-1, use twelve parallel multimode fiber optic
lines operating at 1.25Gbps per channel, instead of existing 1310nm or 1550nm
serial optics. VSR optics are designed to drive signals over distances less than
300 meters, which is sufficient for interconnecting devices within a service
provider's Point-of-Presence (POP). Over these short distances, VSR optics offer
a significant cost savings compared to intermediate and long-reach serial lasers.
When performing latency measurements, the following restrictions apply:

• If latency is measured with packets that are smaller than 80 bytes, then
normal (not wide-packet group) mode should be used and the number of
packet group IDs is limited to 1,024.
• If packets are 80 bytes or larger, then wide-packet group mode may be used.
Two different scenarios apply when using wide-packet group mode:
• If sequence checking is enabled, then the number of packet group IDs is
limited to 8,192.
• If sequence checking is not enabled, then the number of packet group IDs
is limited to 128k.
Port LEDs Each OC192c port incorporates a set of 10 LEDs, as described in Table 26-10.
Table 26-10. LMOC192cPOS Port LEDs
LED Label Usage
LOS Red during Loss of Signal, Green otherwise.
LOF Red during Loss of Frame, Green otherwise.
PPP Green if a PPP link has been established. Red otherwise.
Tx Green while data is transmitted.
Rx Green while data is received.
Error Red on any error.
Option 1 Reserved for future use.
LASER ON Green when the port’s laser is turned on.

Trigger Out Values The signals available on the trigger out pins for all cards in this category are
Table 26-11. OC192 Trigger Out Signals
Pin Signal
A Low (0V) on User Defined Statistic 1 true.

High (+5V) otherwise.
B Low (0V) on User Defined Statistic 2 true

High (+5V) otherwise.
Optical The optical characteristics for the OC192c cards are described in Table 26-12.
Specifications
Table 26-12. LMOC192c Optical Specifications
Specification OC192c 1310nm OC192c 1550nm OC192c VSR-1
Manufacturer GTRAN GTRAN Gore
Average Output Power—Min/Max +1 dBm/+5 dBm -1 dBm/+2 dBm -10 dBm/-5 dBm
Transmit Center Wavelength—Min/Max 1300 nm/1320 nm 1530 nm/1565 nm 830 nm/860 nm
Receive Center Wavelength—Min/Max 1280 nm/1580 nm 1280 nm/1580 nm 830 nm/860 nm
Receive Sensitive—Min/Max -17 dBm/0 dBm -17 dBm/0 dBm -16 dBm/-3 dBm
Safety Class 1 Laser Class 1 Laser Class 1 Laser
Note: An attenuating should be used when looping back to the same port or
when using a short length of cable.
Statistics Statistics for OC192 cards, under various modes of operation may be found in

26 UNIPHY Family
UNIPHY Family
The UNIPHY family of load modules is based on a universal PHY which allows
each port to operate in a number of modes. Figure 26-3 and Figure 26-4 are
pictures of two of the load modules in this family.
Figure 26-3. UNIPHY LM10GUEF-FEC
Figure 26-4. UNIPHY LM10GUPF-XFP

UNIPHY Family
Part Numbers The currently available part numbers are shown in Table 26-13.
Table 26-13. UNIPHY Load Modules
LM10GUEF-FEC LM10GUEF-FEC 10GE Universal Base Load Module with

G.709 FEC capabilities, 1-port, 1550nm,
singlemode. One or more of
OPT10GELWAN, OPTOC192POS, or
OPTOC192BERT must be purchased.
LM10GULF-P LM10GULF-P 10GE Universal Base Load Module, 1-

port, 1310nm, singlemode. -P version
uses a PowerPC with 256MB processor
memory. One or more of OPT10GELWAN,
OPTOC192POS, or OPTOC192BERT
must be purchased.
LM10GUPF-XFP LM10GUPF-XFP 10GE Universal Base Load Module with

pluggable XFP interface, 1-port. One or
more of OPT10GELWAN,
OPTOC192POS, or OPTOC192BERT
must be purchased.
LM10GUVF LM10GUVF 10GE Universal Base Load Module with

VSR parallel optics, 1-port, 1310nm,
singlemode. One or more of
OPT10GELWAN, OPTOC192POS, or
OPTOC192BERT must be purchased.
10G MSM MSM10G1-02 10G Universal Base Load Module, 1-port,

1550nm, singlemode. -P version uses a
PowerPC with 256MB processor memory.
One or more of OPT10GELWAN or
OPTOC192POS must be purchased in
addition.
Transceivers XFP-1550 XFP Transceiver, 1550nm
XFP-1310 XFP Transceiver for LM10GUPF-XFP,

1310nm
Options OPT10GELWAN 10GE LAN/WAN configuration option for

the LM10GU*F.
OPTOC192POS OC-192 POS configuration option for the

LM10GU*F.
OPTOC192BERT OC-192 BERT configuration option for the

LM10GU*F.
SW-DCCSONET DCC SONET support for LM10GU*F.
945-0002 SW-RPRSONET SW-SRPSONET

DCC SONET support for LM10GU*F.

26 UNIPHY Family
Table 26-14. UNIPHY Load Module Specifications
10GUEF/ULF/ 10GUEF/ULF/ 10GUEF/ULF/ 10GUEF/ULF/ 10GUEF-FEC2

UPF/UVF UPF/UVF UPF/UVF UPF/UVF
(10GEWAN (10GE LAN (OC192 mode) (BERT mode)1
mode) mode
# ports 1 1 1 1 1
-M Card Available N N N N N
Layer2/Layer3 Card N N N N N
Available?
Layer 7 Card Available N N N N N
Data Rate 1-100% of 10GB 1-100% of N/A 1-100% of

10Gbps OC192 speeds 10Gbps/
speeds OC192 speeds
Connector/ SC/1310nm or SC/1310nm or SC/1310nm or SC/1310nm or SC/1550nm

Wavelength-Mode 1550nm Single 1550nm 1550nm 1550nm Singlemode
or pluggable Singlemode Singlemode Singlemode
Capture buffer size 32MB 32MB 32MB N/A
Captured packet size 24-65,000 24-65,000 33-64k N/A

bytes bytes
Streams per port 255 255, 32 (-M) 255 N/A
Advanced streams 160 160 160 N/A

16 (-M version)
Preamble size: min- 8 8 N/A N/A

max
Frame size: min-max 24-65,000 24-65,000 54-1600 N/A
Inter-frame gap: 3/4ns - 43sec 3.2ns - 42sec N/A N/A

min-max in 3.4ns steps in 3.2ns steps
Inter-burst gap: min- 3/4ns - 43sec 3.2ns - 42sec N/A N/A

max in 3.4ns steps in 3.2ns steps
Inter-stream gap: 3/4ns - 43sec 3.2ns - 42sec 4ns - 42secs N/A

min-max in 3.4ns steps in 3.2ns steps
Normal stream frame 0.023fps - full 0.023fps - full 0.023fps - full N/A
rate line rate line rate line rate
Advanced stream min Slow: 0.023fps Slow: 0.023fps Slow: 0.023fps N/A
frame rate3 Med: 95fps Med: 95fps Med: 95fps
Fast: 1525fps Fast: 1525fps Fast: 1525fps
Latency 20ns resolution 20ns resolution 20ns resolution N/A
1. Framed BERT only, channelized and unframed BERT are not available.

UNIPHY Family
2. For values not shown, use values from the 10GEWAN/10GELan/OC192 columns according to
mode.
3. Streams are divided up into three speed streams: 144 slow, 8 medium and 8 fast. MSM family
streams are divided into two speed streams: 224 slow and 32 fast.
Port LEDs Each UNIPHY port incorporates a set of LEDs, as described in the following
table.
Table 26-15. UNIPHY Port LEDs
LED Label Usage
LOS Red during Loss of Signal. Green when link has been
established and no Loss of Signal.
LOF Red during Loss of Frame. Green when link has been
established and no Loss of Signal.
PPP/Link Green if Ethernet/PPP link has been established. Red

otherwise.
Error Red on any Ethernet error.
Trigger Green when Trigger is applied.
Pause Indicates flow control frames have been received.
Trigger Out Values The signals and LEDs available on the trigger out pins for UNIPHY family load
modules are described in Table 26-16.
Table 26-16. 10 GE UNIPHY Trigger Out Signals
Pin/LED Value
Trigger Out A Low (0V) on User Defined Statistic 1 true, high

(+5v) otherwise.
Trigger Out B Low (0V) on (POS mode) User Defined Statistic

2 true or (Ethernet mode) pause frame detect,
high (+5V) otherwise.
Pause/Option1 LED Pulses each time a Pause Acknowledge is

granted.
Clock Out Values For -XFP suffix load modules, one coaxial connector is provided to allow phase-
lock to the DUT. The frequency is either 311.0400 MHz or 322.2656 MHz +/-
100ppm.

26 UNIPHY Family
Optical The optical characteristics for the UNIPHY cards are described in Table 26-17.
Specifications Table 26-17. UNIPHY Optical Specifications
Type Specification Wavelength Value
Transmit Output power (dBm) 1310nm -6 to -1
1550nm -1 to 2
Distance (km) 1310nm 10
1550nm 40
Extinction ratio (dB) 1310nm 6
1550nm 8.2
Receive Rx Sensitivity (dBm) 1310nm -12.6
1550nm -14
Overload (dBm) 1310nm -1
1550nm -1
Dispersion (ps/nm) 1310nm 40
1550nm 800
Statistics Statistics for UNIPHY cards, under various modes of operation may be found in

Chapter 27: IXIA OC12 ATM/POS
27 Load Modules
This chapter provides details about OC12 ATM/POS (LM622MR) load module
—specifications and features.
The OC12 ATM/POS (LM622MR) load module enables high performance

testing of routers and broadband aggregation devices such as DSLAMs and PPP
termination systems. The board accommodates pluggable PHYs: The features
available for these load modules are included in the Port Features by Port Type
matrix, which is located on the ixiacom.com website under Support/User Guides/
Spreadsheets.
• 1310 nm multimode optics with dual-SC connectors
• Small Form-factor Pluggable (SFP) socket. Ixia offers 1310 nm singlemode
and multimode transceivers with LC connectors; others may be purchased
independently.
The LM622MR load module is shown in Figure 27-1 on page 27-2.

IXIA OC12 ATM/POS Load Modules
27 Part Numbers
Figure 27-1. LM622MR Load Module with Pluggable PHYs Installed
Part Numbers
The currently available part numbers are shown in Table 27-1 on page 27-2.
Items without a Price List Names entry are no longer available.
Table 27-1. Currently Available ATM/POS Modules
LM622MR LM622MR 2-port ATM/Packet over SONET

Load Module. Supports 622 and
155 Mbps data rates. Requires the
purchase of 2 PHY modules
(OC3OC12PHY or OC3OC12PHY-
SFP) and the OPTATMMR and/or
OPTPOSMR operational mode
option.
LM622MR-512 LM622MR-512 2-port ATM/Packet over SONET

Load Module. Supports 622 and
155 Mbps data rates. Requires the
purchase of 2 PHY modules
(OC3OC12PHY or OC3OC12PHY-
SFP) and the OPTATMMR and/or
OPTPOSMR operational mode
option.
OPTATMMR ATM operational mode option for

LM622MR.

OC12 POS 622 Specifications
Table 27-1. Currently Available ATM/POS Modules
OPTPOSMR OC12c/OC3c Packet over SONET

(POS) operational mode option for
LM622MR.
OC3OC12PHY Single-port OC-3/OC-12 PHY

module for the ATM/Packet over
SONET Load Module. 1310 nm
multimode optics with dual SC
connectors.
OC3OC12PHY-SFP Single-port OC-3/OC-12 PHY

module for the ATM/Packet over
SONET Load Module. Requires one
SFP pluggable transceiver (not
included).
SFP-OC12MM1310D Multirate (OC-3, OC-12) SFP

transceiver. 1310 nm, multimode
with dual LC connectors. Supports
diagnostic features.
SFP-OC12SM1310D Multirate (OC-3, OC-12) SFP

transceiver. 1310 nm, single mode
with dual LC connectors. Supports
diagnostic features.
OC12 POS 622 Specifications

The OC12c POS specifications for the LM622MR load module are contained in
Table 27-2. OC12c POS Specifications for LM622MR Load Module
LM622MR LM622MR-512
# ports 2 2
Data Rate 1-100% of OC12/OC3 speeds 1-100% of OC12/OC3 speeds
Connector Changeable physical interface (PHY) per Changeable physical interface (PHY) per
port: port:
• SC connectors for 1310 nm multimode • SC connectors for 1310 nm multimode
• SFP socket for SFP-LC module • SFP socket for SFP-LC module
PHY clock-in and clock-out: PHY clock-in and clock-out:
• SMA connectors. • SMA connectors.
CPCU RAM 256 512
Capture buffer size 8 MB 8 MB
Captured packet size 34 - 65535 bytes 34 - 65535 bytes
Streams per port 255 Packet Streams 255 Packet Streams
Advanced streams 160 160

27 OC12 POS 622 Specifications
Table 27-2. OC12c POS Specifications for LM622MR Load Module
LM622MR LM622MR-512
Frame size: min-max 35 - 65536 bytes (at full line rate) 35 - 65536 bytes (at full line rate)
12 - 65536 bytes (otherwise) 12 - 65536 bytes (otherwise)
Inter-frame gap: min- 1 μs - 4.294967 secs 1 μs - 4.294967 secs

max
Inter-burst gap: min- 1 μs - 4.294967 secs 1 μs - 4.294967 secs

max
Inter-stream gap: min- 1 μs - 4.294967 secs 1 μs - 4.294967 secs

max
Latency 20 ns resolution 20 ns resolution

Minimum frame size of 33 bytes is Minimum frame size of 33 bytes is
required. required.

ATM Specifications
ATM Specifications
The ATM load module specifications for the LM622MR are contained in Table
27-3 on page 27-5.
Table 27-3. ATM Load Module Specifications
LM622MR/LM622MR-512
# ports 2
Data Rate 0-100% of OC-12/OC-3 speeds
Connector Changeable physical interface (PHY) per port:

• SC connectors for 1310 nm multimode
• SFP socket for SFP-LC module
PHY clock-in and clock-out:
• SMA connectors.
Capture buffer size 8 MB
Captured packet size 49 - 64K bytes (Note 1)
Streams per port 4096 shared by 15 interleaved transmit engines
Frame size: min-max 40 - 65,536 bytes (Note 1)
Latency 20 ns resolution
(Note 1) ATM ports transmits a packet of 65568 bytes, including the header. The
receive buffer, however, is restricted to 65536 bytes. The last 32 bytes of a
maximum size packet is not visible in the capture buffer.
ATM related specifications are detailed in Table 27-4 on page 27-5.

Table 27-4. ATM Specifications
Parameter Specification
Encapsulation • LLC/SNAP Routed Protocol

• LLC/NLPID Routed Protocol
• LLC Bridged Ethernet/802.3
• LLC Bridged Ethernet/802.3 without FCS
• LLC Encapsulated PPP
• VC Mux Routed Protocol
• VC Mux Bridged Ethernet/802.3
• VC Mux Bridged Ethernet/802.3 without FCS
• VC Multiplexed PPP
Virtual Circuits 65,536 VC ids distributed among 4,096 unique

streams
Cell Header Format UNI or NNI per port
ATM Framing AAL5, Constant Bit Rate (CBR) or Unspecified Bit Rate
(UBR)

27 Physical Interfaces
Physical Interfaces
Two pluggable physical interfaces are available for the ATM card:
• OC3OC12PHY: Single OC3/OC12 port module. 1310 nm multimode optics
with dual-SC connectors. This module is shown in Figure 27-2 on page 27-6.
The optical characteristics are expressed in Table 27-5 on page 27-7.
Figure 27-2. OC3OC12PHY Physical Interface

Physical Interfaces
Table 27-5. OC3OC12PHY Optical Specifications
Transmitter/Receiver Specification OC12/OC3 Multimode
Transmitter Fiber 62.5um fiber
Wavelength 1270nm - 1380nm
Mean Launched Power -20dBm to -14dBm
Minimum Extinction Ratio 10dB
Safety LED based
Receiver Fiber 62.5um fiber
Wavelength 1100nm - 1600 nm
Minimum Sensitivity (OC12) -26dBm
Minimum Sensitivity (OC3) -30dBm
Minimum Overload -14dBm
• OC3OC12PHY-SFP: Single OC3/OC12 port module. The PHY

accommodates a SFP transceiver, which is not included with this part. Ixia
offers two transceivers:
• SFP-OC12MM1310D: 1310nm multimode transceiver.
• SFP-OC12SM1310D: 1310nm singlemode transceiver.
Figure 27-3 on page 27-8 shows an OC3OC12PHY-SFP with a transceiver
partially inserted.

27 Physical Interfaces
Figure 27-3. OC3OC12PHY-SFP
The optical characteristics for the two available transceivers are expressed in
Table 27-6. SFP-OC12xx1310 Optical Specifications
Specification SFP-OC12MM1310D SFP-OC12SM1310D

(62.5um fiber) (short reach)
Transmit Center 1270 nm/1380 nm 1260 nm/1360 nm

Wavelength—Min/Max
Mean Launched Power— -20 dBm/-14 dBm -15 dBm/-8 dBm

Min/Max
Minimum Extinction Ratio 10dB 8.2dB
Safety LED based Laser based
Receive Wavelength 1100nm - 1600nm 1100nm - 1600nm
Minimum Sensitivity (OC12) -26dBm -23dBm
Minimum Sensitivity (OC3) -30dBm -8dBm
Minimum Overload -14dBm
Dispersion (OC12) 13ps/nm
Dispersion (OC3) 18ps/nm

Port LEDs
The clock-in/clock-out signal characteristics on both PHYs are described in

Table 27-7 on page 27-9 and Table 27-8 on page 27-9.
Table 27-7. Clock Input Electrical Interface Parameters
Absolute max input 6V (DC plus half AC peak-to-peak)
Frequency (OC12) 77.76 MHz
Frequency tolerance +/- 20ppm
Duty Cycle 40/60% of UI
Jitter limits (12kHz to 5MHz) 12 ps rms
Table 27-8. Clock Output Electrical Interface Parameters
Amplitude 1.3 Vpp minimum, into 50 Ω. (1.5 Vpp

typical)
Frequency (OC12) 77.76 MHz (internal clock mode)
Frequency (OC3) 19.44 MHz (internal clock mode)
Port LEDs
Each OC12c/OC3c port incorporates a set of 6 LEDs, as described in Table 27-9
on page 27-9.
Table 27-9. LMOC12c Port LEDs
LED Label Usage
LOS Red during Loss of Signal and green otherwise.
LOF Red during Loss of Frame and green otherwise.
Tx Green while data is transmitted and blank otherwise.
Rx Green while data is received and blank otherwise.
Err Red on any receive error and blank otherwise.
Trig Blank—reserved for future use.

27 Statistics
Statistics
Statistics for ATM/POS cards, under various modes of operation, may be found
in Table B-26 on page B-145.

Chapter 28: IXIA 10/100 Load
28 Modules
This chapter provides details about 10/100 family of load modules—

The 10/100 family of load modules implements Ethernet interfaces that may run
at 10Mbps or 100Mbps. Different numbers of ports and interfaces are available
for the different board types. The features available for these load modules are
included in the Port Features by Port Type matrix, which is located on the
ixiacom.com website under Support/User Guides/Spreadsheets.
One of the family’s modules (the LM100TXS8) is shown in Figure 28-1 on page
28-2.

IXIA 10/100 Load Modules
28 Part Numbers
Figure 28-1. LM100TXS8 Load Module
Part Numbers
The part numbers are shown in Table 28-1 on page 28-2. Items without a Price
List Names entry are no longer available.
Table 28-1. Part Numbers for 10/100 Modules
Load Module Price List Description

Names
LM100TX LM100TX 4-port multilayer 10/100Mbps Ethernet
LM100TX8 LM100TX8 8-port 10/100Mbps Ethernet, reduced features;

no support for routing protocols, Linux SDK or
L4-L7 applications.
LM100TXS8 LM100TXS8 8-port multilayer 10/100Mbps Ethernet
LM100MII 2-port multilayer 10/100Mbps MII Ethernet
LM100RMII 4-port multilayer 10/100Mbps Reduced MII

Ethernet

Specifications
Specifications
limitations of -3, Layer 2/3 and Layer 7 cards are discussed in Ixia Load Modules
on page 1-5.
Table 28-2. 10/100 Load Module Specifications
LM100TXS8 LM100TX LM100MII LM100RMII

LM100TX8
# ports 8 4 (LM100TX) 2 4
-3 Card Available? N N N N
L2/L3 Card Available? Y (LM100TX8) N N N
Layer 7 Card Available N N N N
Data Rate 10/100 Mbps 10/100 Mbps 10/100 Mbps 10/100 Mbps
Connector RJ-45 RJ-45 MII1 RMII2
Interfaces 100Base-TX 100Base-TX

10Base-T 10Base-T
Capture buffer size 6MB 2MB 2MB 2MB
Captured packet size 12-13k bytes 12-64k bytes 12-64k bytes 12-64k bytes
Flows per port N/A 15872 15872 15872
Advanced Streams 128 N/A N/A N/A
Preamble size: min- 2-63 bytes 2-254 bytes 2-254 bytes 2-254 bytes
max
Frame size: min-max 12-13k bytes 12-64k bytes 12-64k bytes 12-64k bytes
Inter-frame gap: Basic scheduler: 10Mbps: 800ns- 10Mbps: 800ns- 10Mbps: 800ns-
min-max 10Mbps: 8000ns-429s 1717s in 400ns 1717s in 400ns 1717s in 400ns
in 400ns steps steps steps steps
100Mbps: 800ns-42.9s 100Mbps: 160ns- 100Mbps: 160ns- 100Mbps: 160ns-
in 40ns steps 171s in 40ns steps 171s in 40ns steps 171s in 40ns steps
Advanced scheduler:
10Mbps: 8000ns-53s
in 400ns steps
100Mbps: 800ns-5.3s
in 40ns steps
Inter-burst gap: min- 10Mbps: 8000ns-429s 10Mbps: 800ns- 10Mbps: 800ns- 10Mbps: 800ns-
max in 400ns steps 1717s in 400ns 1717s in 400ns 1717s in 400ns
100Mbps: 800ns-42.9s steps steps steps
in 40ns steps 100Mbps: 160ns- 100Mbps: 160ns- 100Mbps: 160ns-
171s in 40ns steps 171s in 40ns steps 171s in 40ns steps

28 Specifications
Table 28-2. 10/100 Load Module Specifications
LM100TXS8 LM100TX LM100MII LM100RMII

LM100TX8
Inter-stream gap: 10Mbps: 8000ns-429s 10Mbps: 800ns- 10Mbps: 800ns- 10Mbps: 800ns-
min-max in 400ns steps 1717s in 400ns 1717s in 400ns 1717s in 400ns
100Mbps: 800ns-42.9s steps steps steps
in 40ns steps 100Mbps: 160ns- 100Mbps: 160ns- 100Mbps: 160ns-
171s in 40ns steps 171s in 40ns steps 171s in 40ns steps
Normal stream min 10: 0.00238fps

frame rate 100: 0.0238fps
Advanced stream min 10 slow: 0.0186fps

frame rate3 10 fast: 9.53 fps
100 slow: 0.186fps
100 fast: 95.3fps
Latency 20ns resolution 20ns resolution 20ns resolution 20ns resolution
1. AMPLIMITE Subminiature D connector 787170-4.

2. AMPLIMITE Subminiature D connector 787170-7.
3. Streams are divided up into tree categories: 112 slow speed streams and 16 fast streams.

Port LEDs
Port LEDs
Each LM100TXS8 port incorporates a set of 2 LEDs, as described in Table 28-4
on page 28-5.
Table 28-3. LM100TXS8 Port LEDs
LED Color Usage
Tx/L Orange 10Mbps link. Pulses on activity.
Green 100Mbps link. Pulses on activity.
RX/E Orange Pulses on error.
Green Full duplex. Pulse on activity.
All other 10/100 card types incorporate a set of 6 LEDs, as described in Table 28-
4 on page 28-5.
Table 28-4. 10/100 Port LEDs
LED Label Usage
Link Green if link established. For Mii and RMii boards, Red if no
transceiver is detected.
100 Green for 100Mbps.
Tx/Coll Green during data transmission. Red during collisions.
Rx/Err Green during error free reception. Red if errors received.
Trigger Out Values

The signals available on the trigger out pins for all cards in this category are
described in Table 28-5 on page 28-5. The LM100TXS8 and LM100TX8 cards
output 60ns pulses and all other cards output 40ns pulses.
Table 28-5. 10/100 Trigger Out Signals
Pin Signal
1 Port 1: High pulse for each packet matching User Defined Statistic 1

28 Statistics
The signals available on the trigger out pins for the LM1000SFPS4 cards is
Table 28-6. LM1000SFPS4 Trigger Out Signals
Pin Signal
5 Ground
6 Ground
Statistics
Statistics for 10/100 cards, for various modes of operation may be found in Table
B-8 on page B-35 and Table B-9 on page B-37.

Chapter 29: IXIA 100 Load Modules
29
This chapter provides details about 100 family of load modules—specifications
and features.
The 100 family of load modules implements Ethernet interfaces that may run at
100Mbps. Different numbers of ports and interfaces are available for the
different board types. The features available for these load modules are included
in the Port Features by Port Type matrix, which is located on the ixiacom.com
website under Support/User Guides/Spreadsheets.
One of the modules in this family (the LM100FX) is shown in Figure 29-1 on
page 29-2. The face plate for the same module is shown in Figure 29-2 on page
29-2.

IXIA 100 Load Modules
29
Figure 29-1. LM100FX Load Module
Figure 29-2. LM100FX Face Plate

Part Numbers
Part Numbers
The part numbers are shown in Table 29-1 on page 29-3. Items without a Price
List Names entry are no longer available.
Table 29-1. Part Numbers for 100Mbps Modules
Load Module Price List Description

Names
LM100FX 4-port multilayer multimode FX Ethernet.
LM100FXSM 4-port multilayer singlemode FX Ethernet.
Specifications
on page 1-5.
Table 29-2. 100 Load Module Specifications
LM100FX LM100FXSM
# ports 4 4
-3 Card Available N N
Available?
Layer 7 Card Available N N
Data Rate 100 Mbps 100 Mbps
Connector MT-RJ (Multimode) MT-RJ (Singlemode)
Interfaces 100Base-X 100Base-X

(multimode) (single mode)
Capture buffer size 2MB 2MB
Captured packet size 12-64k bytes 12-64k bytes
Flows per port 15872 15872
Preamble size: min-max 2-254 bytes 2-254 bytes
Frame size: min-max 12-64k bytes 12-64k bytes
Inter-frame gap: 100Mbps: 160ns-171s 100Mbps: 160ns-171s in

min-max in 40ns steps 40ns steps
Inter-burst gap: min-max 100Mbps: 160ns-171s 100Mbps: 160ns-171s in

in 40ns steps 40ns steps

29 Specifications
Table 29-2. 100 Load Module Specifications
LM100FX LM100FXSM
Inter-stream gap: 100Mbps: 160ns-171s 100Mbps: 160ns-171s in

min-max in 40ns steps 40ns steps
Latency 20ns resolution 20ns resolution

Port LEDs
Port LEDs
Each 100 port incorporates a set of 6 LEDs, as described in Table 29-3 on page
29-5.
Table 29-3. 100 Port LEDs
LED Label Usage
Link Green if link established. For Mii and RMii boards, Red if no
transceiver is detected.
100 Mbps Green for 100Mbps.
Trigger Out Values

described in Table 29-4 on page 29-5.
Table 29-4. 100 Trigger Out Signals
Pin Signal
Statistics
Statistics for 100Mbps cards, under various modes of operation may be found in

29 Statistics

Chapter 30: IXIA Gigabit Load
30 Modules
This chapter provides details about Gigabit family of load modules—

The Gigabit family of load modules implements copper and fiber Ethernet
interfaces that may run at 1000Mbps. Different numbers of ports and interfaces
are available for the different board types. The features available for these
modules are included in the Port Features by Port Type matrix, which is located
on the
One of the modules in this family, the LM1000SFPS4, is shown in Figure 30-1.

IXIA Gigabit Load Modules
30 Part Numbers
Figure 30-1. LM1000SFPS4 Load Module
Part Numbers
The currently available part numbers are shown in Table 30-1. Items without a
Price List Names entry are no longer available.
LM1000GBIC 2-port multilayer Gigabit GBIC

Ethernet; transceivers not included.
2-port multilayer Gigabit GBIC

Ethernet; with 2 multimode GBIC
transceivers.

Ethernet; with 2 singlemode GBIC
transceivers.

Ethernet; with 2 multimode and 2
singlemode GBIC transceivers.

Part Numbers
LM1000SFPS4 LM1000SFPS4 4-port Gigabit Ethernet fiber; SFP

transceiver not included.
SFP-LX 1310nm LX SFP transceiver used

with LM1000SFPS4 .
SFP-SX 850nm SX SFP transceiver used with

LM1000SFPS4

30 Specifications
Specifications
on page 1-5.
Table 30-2. Gigabit Load Module Specifications
LM1000GBIC LM1000SFPS4
# ports 2 4
-3 Card Available N N
Available?
Data Rate 1000 Mbps1 1000 Mbps
Connector SX, SX3: SC Multimode SFP or MT-45.2

LX: SC Singlemode
GBIC: GBIC single and/or
multimode
Interfaces 1000Base-X 1000Base-X
Capture buffer size 4MB 8MB
Captured packet size 12-64k bytes 12-13k
Advanced streams per N/A 256

port
Flows per port 15872 N/A
Preamble size: min-max 6-254 bytes 8-61 bytes
Frame size: min-max 48-64k bytes 12-13k bytes
Inter-frame gap: 64ns-68sec in 16ns steps Basic scheduler:

min-max 64ns-4.29s in 16ns steps
Advanced scheduler:
64ns-0.53s in 16ns steps
Inter-burst gap: min- 96ns-68sec in 16ns steps 64ns-16.7ms in 16ns steps

max
Inter-stream gap: 96ns-68sec in 16ns steps 64ns-4.29ms in 16ns steps

min-max
Normal stream min 0.238fps

frame rate
Advanced stream min slow: 1.86fps

frame rate3 fast 953fps
Latency 20ns resolution 20ns resolution

Port LEDs
Table 30-2. Gigabit Load Module Specifications
LM1000GBIC LM1000SFPS4
Max Value List Entries N/A 48K
Max Range List Entries4 N/A 6K
1. Odd frame sizes can cause diminishment in actual data rates on gigabit modules.
2. LC connector is built-in, SFP connection requires either SFP-SX (850nm SX) or SFP-LX
(1310nm LX) module purchased from Ixia, or separately supplied.
3. Streams are divided up into tree categories: 112 slow speed streams and 16 fast streams.
4. 192k memory is shared between value list entries (at 4 bytes per entry) and range list en-
tries (at 32 bytes per entry).
Note: A special capability of Gigabit modules is the ability to echo all received
packets back out to the network. This feature should never be used in a live
network, as it is likely crash the network.
Port LEDs
Each Gigabit port incorporates a set of LEDs, as described in Table 30-3 on page
30-5.
Table 30-3. Gigabit Port LEDs
LED Label Usage
Link Green if link established.
Line Green if an alignment, disparity, or symbol error has been

detected. (Not available on the LM1000SFPS4.)
Half Green for half duplex operation. (Not available on the

LM1000SFPS4.)
Tx/Coll Green during data transmission. Red during collisions.
Each LM1000SFPS4 port incorporates a set of 6 LEDs, as described in Table 30-

4 on page 30-5.
Table 30-4. 10/100/1000 Port LEDs for LM1000TXS4
LED Label Usage
Link Green for 1000 Mbps link, orange for 100 Mbps link, yellow for 10
Mbps link and off for no link.
Tx/Col Green during data transmission and red during collisions.

30 Port LEDs
Table 30-4. 10/100/1000 Port LEDs for LM1000TXS4
LED Label Usage
Rx/Err Green during error free reception and red if errors are received.

Trigger Out Values
Trigger Out Values

The signals on the trigger out pins for cards in this category are described in
Table 30-5. Gigabit Trigger Out Signals
Pin Signal
1 Port 1-10 ns high pulse for each packet matching User Defined Statistic 1
2 Port 2-10 ns high pulse for each packet matching User Defined Statistic 1
3 Port Z-low during transmit of frame, otherwise high
4 Port 2-low during transmit of frame, otherwise high
The LM1000SFPS4 sends a 660ns negative pulse when user defined statistic 1 is
true.
Statistics
Statistics for Gigabit cards, under various modes of operation may be found in

30 Statistics

Chapter 31: IXIA OC12c/OC3c
31 Load Modules
This chapter provides details about OC12c/OC3c family of load modules—

The OC12c/OC3c family of load modules implements Optical Carrier interfaces

that may run at OC12 or OC3 speeds. Both interfaces operate in concatenated
mode, as opposed to channelized mode. Different numbers of ports and interfaces
are available for the different board types. The features available for these load
modules are included in the Port Features by Port Type matrix, which is located
on the ixiacom.com website under Support/User Guides/Spreadsheets.
One of the modules in this family, the LMOC12c, is shown in the following
figure.

IXIA OC12c/OC3c Load Modules
31 Part Numbers
Part Numbers
The part numbers are shown in the following figure. Items without a Price List
Table 31-1. Part Numbers for OC12c/OC3c Modules
LMOC12c/ LMOC12c 2-port multilayer OC12c/OC3c SR-1

LMOC3c POS/SDH, 1310nm multimode
LMOC12cSM 2-port multilayer OC12c/OC3c SR-1

POS/SDH, 1310nm singlemode

Specifications
Specifications
on page 1-5.
Table 31-2. OC12c/OC3c Load Module Specifications
LMOC12c
LMOC12cSM
# ports 2
-3 Card Available N
Layer2/Layer3 Card N
Available?
Data Rate 1-100% of OC12/OC3 speeds (See note 3)
Connector SC-Singlemode or Multimode
Captured packet size OC3: 49 - 5,120 bytes

OC12: 49 - 15,500 bytes
(See note 1)
Streams per port 255
Flows per port N/A
Preamble Size: min-max N/A
Frame size (transmit): min- 34-65,536 bytes (See note 4)

max
Frame size (receive): min- 12-65,536 bytes (See note 5)

max
Inter-frame gap: min-max N/A
Inter-burst gap: min-max 1μs - 85secs
Inter-stream gap: min-max 1μs - 85secs
Latency 20ns resolution (See note 2)
1. Captured Packet Size Note: At 100% line rate. Smaller values are possible at
lower line rates.
2. Requires that packets be larger than 70 bytes when operating at full line rate.

31 Port LEDs
3. Correct data rates can only be maintained with a minimum number of

packets, depending on packet size. For OC12 operation, the numbers of
packets are required for the indicated ranges of packet sizes:
Table 31-3. OC12 Minimum Number of Packets
Packet Size Minimum Number of

Packets per Stream
45 or less 30
46 - 47 8
48 - 54 7
55 - 63 6
64 - 84 5
85 - 129 4
130 - 199 3
200 - 499 2
500+ 0
For OC3 operation, the numbers of packets are required for the indicated
ranges of packet sizes:
Table 31-4. OC3 Minimum Number of Packets
Packet Size Minimum Number of

Packets per Stream
34 or less 4
35 - 64 3
65 - 274 2
275+ 0
4. The maximum frame size depends on the type of header and PPP negotiation.
The maximum frame size is 64k bytes although beyond 8192 bytes, the data
is repeated.
5. 12 byte frames cannot be received back-to-back. A 34 byte frame is required
to receive back-to-back frames.
Port LEDs
Each OC12c/OC3c port incorporates a set of 4 or 6 LEDs, as described in the
following table.
LED Label Usage
LOS Red during Loss of Signal.
LOF Red during Loss of Frame.

Trigger Out Values
LED Label Usage
Error Red on any POS error.
Trig Follows the state of the Trigger Out pin.
Trigger Out Values

Table 31-6. OC12c/OC3c Trigger Out Signals
Pin Signal
Optical Specifications
The optical characteristics for the OC12c/OC3c cards are described in the
following table.
Specification OC12c/OC3c Multimode OC12c/OC3c Singlemode
Average Output Power–Minimum/ -19 dBM/-14 dBM -15 dBM/-8 dBM

Maximum
Transmit Center Wavelength– 1270 nm/1380 nm 1293 nm/1310 nm

Minimum/Maximum
Receive Center Wavelength– 1270 nm/1380 nm 1200 nm/1550 nm

Minimum/Maximum
Receive Sensitive–Minimum/ -26 dBM/-14 dBM -28 dBM/-5 dBM

Maximum
Safety Led based Class 1 Laser
Statistics
Statistics for OC12c cards, under various modes of operation may be found in

31 Statistics

Chapter 32: IXIA OC48c Load
32 Modules
This chapter provides details about OC48c family of load modules—

The OC48c family of load modules implements Optical Carrier interfaces that
runs at OC48 speeds. The interface operates in concatenated mode, as opposed to
channelized mode. Cards are available that perform Packet Over SONET testing,
Bit Error Rate Testing or both. The features available for these load modules are
included in the Port Features by Port Type matrix, which is located on the
One of the modules in this family, the LMOC48c, is shown in the following
figure.

IXIA OC48c Load Modules
32 Part Numbers
Figure 32-2. MSM2.5G1-01 Load Module
Part Numbers
The part numbers are shown in the following figure. Items without a Price List
Table 32-1. Part Numbers for OC48 Modules
Load Module Part Numbers Description
LMOC48cPOS LMOC48C 1-port multilayer OC48cSR-1 POS/SDH,

1310nm, singlemode
LMOC48cPOS-M LMOC48C3 1-port multilayer OC48cSR-1 POS/SDH,

1310nm, singlemode, manufacturing
version
LMOC48cBERT LMOC48311 1-port multilayer OC48cSR-1 SONET/

BERT, 1310nm, singlemode
LMOC48312 1-port multilayer OC48cIR-2 SONET/

BERT, 1550nm, singlemode

Specifications
Table 32-1. Part Numbers for OC48 Modules
LMOC48cPOS/ LMOC48411 1-port multilayer OC48cSR-1 POS/BERT,

BERT 1310nm, singlemode
LMOC48412 1-port multilayer OC48cIR-2 POS/BERT,

1550nm, singlemode
2.5G MSM POS MSM2.5G1-01 1-port multilayer OC48cSR-1 POS/SDH,

1310nm, singlemode
SW-DCCSONET DCC SONET support for all modules.
SRP SONET support for all modules.
SW-SRPSONET 945-0002 SRP SONET and RPR SONET support

SW-RPRSONET for all modules
SW-VCAT- 945-0005 SONET Virtual Concatenation (VCAT)

SONET option
Specifications
LMOC48c LMOC48cBE LMOC48c 2.5G MSM POS2

RT POS+
LMOC48cBE BERT1
RTRx
# ports 1 1 1 1
-3/-M Card Y N N N
Available
Layer2/Layer3 N N/A N Y
Card Available?
Layer 7 Card N N/A N N

Available
Data Rate 1-100% of OC48 2.488 Gbps 1-100% of OC48

speeds speeds
Connector/ SC/1310nm or SC/1310nm SFP/1310nm or

Wavelength-Mode 1550nm Singlemode 1550nm
Singlemode Singlemode
Capture buffer 32MB N/A Up to 384 MB

size
Captured packet 26-65,535 bytes N/A 17-65,535 bytes

size

32 Specifications
LMOC48c LMOC48cBE LMOC48c 2.5G MSM POS2

RT POS+
LMOC48cBE BERT1
RTRx
Streams per port 255 N/A 256
Flows per port N/A N/A N/A
Advanced 160 256

Streams
Preamble size: N/A N/A N/A

min-max
Frame size: min- 26-65,535 N/A 25-65,535

max
Inter-frame gap: N/A N/A 4.0ns - 42sec in

min-max 3.2ns steps
Inter-burst gap: 1μs - 42secs N/A 4.0ns - 42sec in

Inter-stream gap: 1μs - 42secs N/A 4.0ns - 42sec in

Normal stream 0.023fps - full 0.023fps - full line

frame rate line rate rate
Advanced Slow: 0.023 - Slow: 0.023fps

streams frame 2083333 fps Fast: 1525fps
rate3 Med: 95fps - full
line rate
Fast: 1525fps -
full line rate
Latency 20ns resolution N/A 20ns resolution
1. Refer to the LMOC48cPOS and LMOC48cBERT columns for the characteristics of

this card when its port is in POS or BERT mode, respectively.
2. Due to power requirements, only one 2.5G MSM POS module can be used in a 250
or 400T chassis. Other modules can be used with the 2.5G MSM POS in the same
chassis, but only one 2.5G MSM POS at a time (excepting MSM family of modules
and the CPM1000T8, which have the same limitation).
3. Streams are divided up into three categories: 144 slow speed streams, 8 medium
streams, and 8 fast streams (excluding the 2.5G MSM POS load module).

OC48c VAR Calibration
OC48c VAR Calibration

This procedure allows the OC48 VAR module’s transmission frequency to be
varied to test compliance of devices to the limits of the specification.
Frequency The OC48 VAR allows a variation of +/- 100 parts per million (ppm) from the
Adjustment clock source’s nominal frequency, through a DC voltage input into the BNC jack
marked ‘DC IN’ on the front panel. The variation is from the lowest frequency
when DC IN is 0 V, to highest frequency when DC IN is 3.3 V. The input voltage
should be used only within this range, although the DC IN circuitry is designed to
withstand +/- 30 V in the case of accidental overdrive from a function generator.
The input has a single-pole low pass at 16 Hz to keep injected noise from causing
a violation of OC48 jitter specifications. As a result, the system should be given
50 to 100 milliseconds to settle after a voltage step at DC IN.
Frequency The frequency may be monitored through the BNC marked ‘Freq Monitor.’ This
Monitoring output provides the OC48 line clock divided by 16. The center frequency is
155.52 MHz. The voltage is 70 mV peak-to-peak into 50 ohms, suitable for direct
connection into a frequency counter (such as an HP53181A) through 50 ohm
coaxial cable. The frequency counter should be set for 50 ohm termination in a
suitably sensitive mode.
Port LEDs
There are two sets of LEDs, one for LMOC-48c load modules and one for MSM
OC-48c load modules.
Each OC48c port incorporates a set of LEDs, as described in the following

figure.
LED Label Usage
PPP Green if a PPP link has been established. Red otherwise.
LOS Red during Loss of Signal, Green otherwise.
LOF Red during Loss of Frame, Green otherwise.
Error Red on any POS error.

32 Trigger Out Values
Each 2.5G MSM POS port incorporates a set of LEDs, as described in the
following table.
Table 32-4. MSM2.5G1-01 Port LEDs
LED Label Usage
Trigger Green if a Trigger A condition occurred, Red if a temperature

condition occurred.
Tx Green if transmit is active and frames are being sent, blank

otherwise.
LOS Green if signal level is good, Red if loss of signal condition is

detected, blank if no transceiver is detected.
Error Red if module is in an error state, blank otherwise.
Rx Green if valid frames being received, Red if errored frames being

received, blank otherwise.
LOF Green if valid framing exists, Red if loss of frame condition exists.
Trigger Out Values

The signals available on the trigger out pins for legacy OC-48c load modules in
this category are described in the following table.
Table 32-5. LMOC48c Trigger Out Signals
Pin Signal
1 Always high (no trigger available)
The signals available on the trigger out pins for MSM load modules in this
category are described in the following table.
Table 32-6. 2.5G MSM POS Trigger Out Signals
Pin/LED Value
Trigger Out 10nS active high pulse on trigger.
Trigger LED Indicates Trigger. This triggers on User Defined

Statistic 1.

The optical characteristics for the OC48c cards are described in the following
table.
Specification OC48c Singlemode
Average Output Power–Minimum/ -10 dBM/-3 dBM

Maximum
Transmit Center Wavelength– 1266 nm/1360 nm

Minimum/Maximum
Receive Center Wavelength–Minimum/ 1260 nm/1580 nm

Maximum
Receive Sensitive–Minimum/Maximum -18 dBM/-3 dBM
Safety Class 1 Laser
Statistics
Statistics for OC48 cards, under various modes of operation may be found in

32 Statistics

Chapter 33: IXIA FCMGXM Load
33 Modules
This chapter provides details about FCMGXM family of load modules—

The FCMGXM family of high speed load modules delivers high-density, 2/4/8G
fibre channel test solution. These load modules deliver high-density converged
data center infrastructure for testing end-to-end Fibre Channel and Fibre Channel
over Ethernet (FCoE) testing. The fibre channel load module comes with four or
eight ports and each port can be configured to run at 2, 4, or 8 G speeds.
The 4-port and 8-port FCMGXM load modules deliver complete FC-2 and FCP
data plane capabilities and performance.
One of the modules in this family, the FCMGXM8, is shown in the following
figure.
Figure 33-1. FCMGXM Load Module

IXIA FCMGXM Load Modules
33 Part Numbers
Part Numbers
Table 33-1. Part Numbers for FCMGXM Modules
FCMGXM4 950-0001 FCMGXM4S-01 4-Port Fibre Channel Load

Module, with 2 Gbps, 4 Gbps
and 8 Gbps support and
SFP+ interface. It requires
one or more SFP+
transceiver options.
FCMGXM8 950-0002 FCMGXM8S-01 8-Port Fibre Channel Load

Module, with 2 Gbps, 4 Gbps
and 8 Gbps support and
SFP+ interface. It requires
one or more SFP+
transceiver options.
Specifications
The load module specifications are contained in Table 33-2 on page 33-2.
Table 33-2. FCMGXM Load Module Specifications
Load Modules FCMGXM8/FCMGXM4
Number of ports per module 8/4
Number of chassis slots per 1

module
Maximum ports per chassis Note: XM12 High Performance chassis is

required for 88 ports to be installed in a
single chassis. Up to eleven 8-port load
modules are supported in an XM12 High
Performance chassis, and up to 8 8-port
load modules are supported in a standard
XM12 chassis. The XM2 chassis supports
up to 16 ports.
Supported transceivers SFP+ Tri-rate 2/4/8G duplex LC connector

850nm multimode 1310 single mode.
Per-port CPU speed and memory 800 MHz, 1 GB/1 GHz, 1 GB.
Per-port capture buffer 512 MB
Interface speeds 2/4/8G FC
FC-1 Primitives Yes
FC-2 Protocols Yes

Specifications
FCP Support Yes
Number of transmit flows per port Billions

(sequential values)
Number of transmit flows per port 1 million

(arbitrary values)
Number of trackable receive flows 1 million

per port
Number of stream definitions per 256

port In packet stream (sequential) or advanced
stream (interleaved) mode, each stream
definition can generate millions of unique
traffic flows.
Table UDF 1 million entries.

Comprehensive packet editing function for
emulating large numbers of flows. Entries
of up to 256 bytes, using lists of values can
be specified and placed at designated
offsets within a stream. Each list consists of
an offset, a size, and a list of values in a
table format.
Packet flow statistics Tracks 1 million flows.
Transmit engine Wire-speed packet generation with

timestamps, sequence numbers, data
integrity signature, and packet group
signatures.
Receive engine Wire-speed packet filtering, capturing, real-

time latency, and inter-arrival time for each
packet group, data integrity, and sequence
checking.
User defined field features Fixed, increment, or decrement by user-

defined step, value lists, range lists,
cascade, random, and chained fields.
Filters 2x128-bit user-definable pattern and offset,

frame length range, CRC error, data
integrity error, and sequence checking
error (small, big, reverse).
Data field per stream Fixed, increment (byte/word), decrement

(byte/word), random, repeating, user-
specified, CJPAT, and CRPAT fields.
Error generation CRC (good/bad), oversize frame, parity

error, and R_RDY errors.
Latency measurements 20 nanoseconds resolution in packet

timestamp.

33 Specifications
Statistics The new statistics are as follows:

• Link State and speed
• (Tx) Bytes, Frames, (count and rate)
• (Rx) Bytes, Frames, (count and rate)
• (Rx) CRC errors, Oversize (2112),
Undersize (24) (count and rate)
• Packet group Latency
• Data Integrity
• Capture Trigger/Filter (count and rate)
• User Defined Stats: 6 (count and rate)
• Protocol Server Tx/Rx (count and rate)
• Remote B-B Credit Value
• Remote B-B Credit Count
• R_RDY Tx/Rx (count and rate)
• Disparity errors (count and rate)
• Stats: Port CPU status
• Transmit Duration
• Invalid EOF Count/Rate
• Code Error Count/Rate
• FLOGI Sent
• FLOGI LS_ACC received
• FLOGO Sent
• PLOGI Sent
• PLOGI LS_ACC received
• PLOGI Request received
• PLOGO Sent
• PLOGO Received
• FDISC Sent
• FDISC LS_ACC Received
• NS Registration Sent
• NS Registration Successful
• NxPort Enabled
• NxPort-IDs Acquired
• NS Query Sent
• NS Query Successful
• PRLI Sent
• PRLI Successful
• PRLI Received
• RSCN Received
• RSCN Acc Transmitted
• SCR Transmitted
• SCR Acc Received
Operating temperature range 41°F to 95°F (5°C to 35°C), ambient air.

Chapter 34: IXIA Xcellon-Flex Load
34 Modules
This chapter provides details about Xcellon-Flex family of load modules—

The Xcellon-Flex family of high speed load modules delivers high-density, high-
performance test solutions. Xcellon, the architecture behind these load modules,
features aggregation of multi-core CPUs and high memory to meet testing needs
for high-scale performance.
The Xcellon-Flex family consists of the following load modules:

• 10GbE Accelerated Performance
• 10GbE Full Emulation
• A 10/40 Gigabit Ethernet Accelerated Performance
• A 40 Gigabit Ethernet Full Emulation
The card names are FlexAP10G16S, FlexFE10G16S, FlexAP1040SQ, and

FlexFE40QP.
The Accelerated Performance load module provides architecture for layer 2-7
performance testing, providing ultra-high-scale session and protocol emulation
per port. The Full Emulation load module is for layer 2-3 mid-range protocol
emulation and scale capacity testing for switches and routers. The Xcellon-Flex
Combo 10/40GE Accelerated Performance load module provides both 10GE
SFP+ and/or 40GE QSFP+ ports in a single chassis slot. It uses aggregation
technology to combine CPU power and memory, and provides ultra-high
networking protocol scalability. The 4x40GE Full Emulation load module has a
rich layer 2-7 feature set and is well suited for mid-range protocol emulation and
scale testing. The load module is ideal for manufacturers of large-port-count,
converged data center switches.

IXIA Xcellon-Flex Load Modules
34
The Xcellon-Flex family load module is shown in the following figure:
Figure 34-1. Xcellon-Flex Module-FlexAP10G16S
The Xcellon-Flex family load module is shown in the following figure:
Figure 34-2. Xcellon-Flex Module-FlexFE10G16S
Figure 34-3. Xcellon-Flex Module-FlexAP1040SQ
Figure 34-4. Xcellon-Flex Module-FlexFE40QP

Part Numbers
Part Numbers
Table 34-1. Part Numbers for Xcellon-Flex Modules
FlexAP10G16S 944-1060 10 Gigabit Ethernet

Load Module, 16-Port LAN,
SFP+ interface with full
performance L2-L7 support.
FlexFE10G16S 944-1061 10 Gigabit Ethernet Full

Emulation Load Module, 16-
port LAN, SFP+ interface
with L2-3 support.
FlexAP1040SQ 944-1062 10/40 Gigabit Ethernet

Load Module, 16-Ports of
SFP+ interfaces and 4-ports
of QSFP+ 40GE interfaces
with full performance L2-7
support, for XM12-02 (941-
rackmount chassis and
XM2-02 (941-0003) portable
chassis, requires one or
more SFP+ transceiver
options: 10GBASE-SR/SW
(948-0013), or 10GBASE-
LR/LW (948-0014).
FlexFE40QP 944-1065 40 Gigabit Ethernet Full

Emulation Load Module, 4-
ports of QSFP+ 40GE with
L2-3 support.

34 Specifications
Specifications
The load module specifications are contained in Table 34-2.
Table 34-2. Xcellon-Flex Load Module Specifications
Feature Everest 10GE Everest 10GE Everest Combo Everest 40GE

Full Feature Reduced Feature Only
Load Modules FlexAP10G16S FlexFE10G16S FlexAP1040SQ FlexFE40QP
Number of ports per 16 16 4 4

module
Number of chassis 1 1 1 1
slots per module
Maximum ports per XM12 High XM12 High XM12 High Perfor- XM12 High Perfor-
chassis Performance: 128 Performance: 128
mance: 96-ports mance: 24-ports
XM2Desktop: 16 XM2Desktop: 16
10GE 40GE
SFP+ and 24-ports QSFP+
40GE QSFP XM2Desktop: 4-
ports 40GE QSFP+
XM2Desktop: 16-
ports 10GE SFP+
or 4-
ports 40GE QSFP
Note: XM12 High Performance chassis is required for the simultaneous operation of 128 ports in a single
chassis. If a standard XM12 chassis (941-0002) is used with these load modules, conversion to the High
Performance model is required. A field replaceable power supply upgrade kit (943-0005) is available for this
purpose. When one or more FlexAP10G16S or FlexFE10G16S load modules is installed in an XM12 High
Performance chassis, the maximum total number of load modules that may be installed at one time in a
single chassis is 8. The XM2 portable chassis (941-0003) supports up to 16 ports (1 load module) of the
FlexAP10G16S FlexFE10G16S modules. No other load module is installed in the XM2 chassis when a
FlexAP10G16S or FlexFE10G16S load module is installed.
Supported
transceivers
Per-port CPU
speed and memory
Capture buffer size 256 MB 64 MB 256MB (10GE), 256 MB

1GB(40GE)

Specifications

Frame Size Minimum Frame Minimum Frame Minimum Frame Minimum Frame
Size at Line Rate: Size at Line Rate: Size at Line Rate: Size at Line Rate:
48 - No UDF 48 - No UDF 48 - No UDF 60
60 - UDF enabled 60 - UDF enabled 60 - UDF enabled Minimum Frame
Minimum Frame Minimum Frame Minimum Frame Size - may not be at
Size - may not be at Size - may not be at Size - may not be at Line Rate: 60
Line Rate: 48 Line Rate: 48 Line Rate: 48 Maximum Frame
Maximum Frame Maximum Frame Maximum Frame Size: P0: 9216B
Size: P0: 9216B Size: P0: 9216B Size: P0: 9216B others 2500B
others 2500B others 2500B others 2500B
Table UDF 1 million entries 256 K entries 1 million entries 1 million entries
Advanced 512 256 512 256

scheduler streams
per port
Latency 20 ns resolution 20 ns resolution 20 ns resolution 2.5 ns resolution
Ambient Operating 5-30 5-30 5-30 5-30

Temperature Range
Tranceiver Type SFP+ SFP+ SFP+ QSFP+
Direct Attach Yes Yes No Yes

Copper
LED 2 LED per Port 2 LED per Port 1 LED per Port 4 LED per Port
ppm Adjust range +/-100ppm +/-100ppm +/-100ppm +/-100ppm
ppm Adjust port/ Card Card Card Card

card
10GbE Interface 10GbE LAN 10GbE LAN IEEE802.3ae 10GE IEEE802.3ae 10GE
protocols LAN, IEEE802.3ba LAN, IEEE802.3ba
40GBASE-R LAN 40GBASE-R LAN
Data Center Proto- FCoE, Priority-based Flow Control (IEEE Priority-based Flow
802.1Qbb) and LLDP/DCBX support Control
col Upgrades
(IEEE 802.1Qbb)
(optional feature)
Multi-core Yes Yes Yes Yes

processors
Aggregation Yes Yes Yes No

capability
Layer 2-3 routing Yes Yes Yes Yes

protocol emulation
Layer 4-7 Yes No Yes Yes

application traffic
testing

34 Specifications

Number of transmit Billions Billions Billions Billions

flows per port
(sequential values)
Number of transmit 1 million 32 K

flows per port
(arbitrary values)
Number of transmit 1 million 1 million

flows per port
(PGID)
Trackable receive 1 million 64 K 1 million 64 K

flows
Table UDF 1 million entries 256 K entries 1 million entries 1 million entries
Packet flow Track 1 million flows Track 64 K flows

statistics
Transmit engine Wire-speed packet generation with timestamps, sequence Wire-speed packet
numbers, data integrity signature, and packet group signatures filtering, capturing,
realtime latency
and inter-arrival
time for each
packet group, data
integrity, and
sequence checking
Receive engine Wire-speed packet filtering, capturing, real-time latency and inter-arrival time for each
packet group, data integrity, and sequence checking
User defined field Fixed, increment or decrement by user defined step, value lists, range lists (supported
features in all 10 GE mode), cascade, random, and chained
Filters 48-bit source/destination address, 2x128-

bit user-definable pattern and offset, frame
length range, CRC error, data integrity
error, and sequence checking error (small,
big, reverse)
Data field per Fixed, increment (byte/word), decrement (byte/word), random, repeating, and
stream userspecified
Error generation CRC (good/bad/none), undersize, oversize
Latency self- Ability to calibrate and remove inherent latency

calibration

Specifications

Link Fault Signaling Link state indicator Link state indicator FlexAP1040SQ Generate local and
for No Fault, Local for No Fault, Local (10GE): Link state remote faults with
Fault, and Remote Fault, and Remote indicator for No controls for the
Fault. Fault. Fault, Local Fault, number of faults
and Remote Fault. and order of faults,
FlexAP1040SQ and the ability to
(40GE): Generate select the option to
local and remote have the transmit
faults with controls port ignore link
for the number of faults from a remote
faults and order of link partner.
faults, and the
ability to select the
option to have the
transmit port ignore
link faults from a
remote link partner.
Transmit line clock Ability to adjust the parts per million (ppm)
adjustment line frequency over a range of the
following:
• LAN mode: +/-100 ppm
IPv4, IPv6, UDP, Hardware checksum generation and verification

TCP
Frame length Fixed, random, weighted random, or increment by user-defined step

controls
Operating 41°F to 86°F (5°C to 30°C), ambient air

temperature range Note: When an Xcellon-Flex load module is installed in an XM12 chassis, the
maximum operating temperature of the chassis is 30°C (86°F) ambient air
temperature.
40 GE Physical IEEE 802.3ba

Coding Sublayer compliant PCS
(PCS) test features transmit and
receive side test
capabilities
Per PCS lane, Supports all

transmit lane combinations of
mapping PCS lane mapping:
Default, Increment,
Decrement,
Random, and
Custom

34 Mechanical Specification of FlexAP10G16S/FlexFE10G16S Load Modules

Per PCS lane, lane Ability to inject

marker, or lane errors into the PCS
marker and payload Lane Marker and
error injections simultaneously into
PCS Lane Marker
and Payload fields
by the user. This
includes the ability
to inject sync bit
errors into the Lane
Marker and
Payload. User can
control the PCS
lane, number or
errors, period count
and manage the
repetition of the
injected errors.
Per PCS lane, PCS Sync Header

receive lanes and Lane Marker
statistics Lock, Lane Marker
mapping, Relative
lane skew
measurement (up
to 104
microseconds),
Sync Header and
PCS Lane Marker
Error counters,
indicators for Loss
of Synch Header
and Lane Marker,
BIP8 errors.
Mechanical Specification of
FlexAP10G16S/FlexFE10G16S
Load Modules
Front Panel The Front panel of FlexAP10G16S/FlexFE10G16S load module is shown in the
following figure:

Mechanical Specification of FlexAP1040SQ Load Modules
Figure 34-5. Front panel of FlexAP10G16S/FlexFE10G16S
Led Panel Table 34-3. Led panel of FlexAP10G16S/FlexFE10G16S Load Module

Specifications
LED1 TX
10GE Link up = Solid Green
10GE TX Active = Blinking Green
10GE TX Error = Blinking Red
Inactive = Off
LED2 RX
Loopback = Solid Green
10GE RX Active = Blinking Green
10GE RX Error = Blinking Red
Link Down = Solid Red
Port Inactive = Off
When port is in aggregation mode (the PCPU resource is used by other port), TX/
RX LEDs are inactive (i.e. off). The aggregation egress port will have normal
TX/RX LED operation.
FlexAP1040SQ Load Modules
Front Panel The Front panel of FlexAP1040SQ load module is shown in the following figure:
Production – 944-
Figure 34-6. Front panel of FlexAP1040SQ
1062-02

34 Mechanical Specification of FlexAP1040SQ Load Modules
Led Panel The Led panel of FlexAP1040SQ load module is shown in the following figure:
Production – 944-
Figure 34-7. Led panel of FlexAP1040SQ
1062-02
Table 34-4. Led panel of FlexAP1040SQ Load Module Specifications
10GE Mode 1 LED/Port where LED number matches

port number
Blinking Green Tx/Rx Activity
Blinking Red Rx Error
Solid Red Link down
Solid Green Link up
Solid Yellow Loopback
Off Port is inactive
When port is in aggregation mode (the PCPU resource is used by other port), TX/
RX LEDs are inactive (i.e. off). The aggregation egress port will have normal
TX/RX LED operation.
40GE Mode LED/Port aligned from top/down defined as

follows:
• Tx
• Rx
• Link
• Error
Definition matches the 40G Only definition.

Mechanical Specification of FlexAP40QP4 Load Modules
FlexAP40QP4 Load Modules
Front Panel The Front panel of FlexAP40QP4 load module is shown in the following figure:
Figure 34-8. Front panel of FlexAP40QP4

34 Mechanical Specification of FlexAP40QP4 Load Modules
Led Panel Table 34-5. Led panel of FlexAP40QP4 Load Module Specifications
LED/Port aligned from top/down defined as

follows:
• Tx
• Rx
• Link
• Error
LED1 TX
10GE TX Active = Blinking Green
10GE TX Error = Blinking Red
Inactive = Off
LED2 RX
10GE RX Active = Blinking Green
10GE RX Error = Blinking Red
Port Inactive = Off
LED3 Link
Link up = Solid Green
Link Down = Solid Red
Internal Loopback = Solid Yellow
Line Loopback = Solid Blue
Port Inactive = Off
LED4 Error
Remote Faults = Blinking Yellow
Local Faults = Solid Red
Port Inactive = Off

Chapter 35: IXIA Xcellon-Multis
35 Load Modules
This chapter provides details about Xcellon-Multis family of load modules—

Xcellon-Multis is a new, next generation, high density, tri-speed, 100/40GE load

module (i.e. NG 100GE) family of products. This load module family comprises
the industry’s highest density 40G and 100G higher speed Ethernet (HSE) test
equipment, providing more flexible test coverage and 4x100GE, 12x40GE, or
dual-rate 40GE/100GE, all in a single-slot load module. This is done using cable
fan-out technology. Fan-out technology allows a higher speed port to fan-out to
several ports of lower speed thus enabling you to have multiple speeds from a
single port and higher port densities per chassis.
The Xcellon-Multis card has four Ethernet ports with 100GE speeds. The card
has a transceiver corresponding to each port. In each port , you can insert a fan-
out cable, which fans the output into multiple ports.
Xcellon-Multis supports the following:

• 4 x 100GE CXP ports per slot – 2x Xcellon-Lava.
• 12 x 40GE QSFP+ ports per slot – 3x Xcellon-Flex.
• 48x100GE or 144x40GEports per XG12 chassis.
• Broad Layer 23 protocol coverage.
• Multimode fiber support.

IXIA Xcellon-Multis Load Modules
35 Key Features
Key Features
The key features of Xcellon-Multis load modules are as follows:
Highest density
Xcellon-Multis comprises three CXP-based load modules in a single chassis slot

• 4x100GE only
• 12x40GE only, using fan-out technology
• Dual-rate 4x100GE and 12x40GE, using fan-out technology
Fan-out technology
• Provides high-density interfaces over multiple speeds.
• Increases interface flexibility.
• Facilitates a wide range of interoperability testing.
Multi-personality
• Supports 100/40GE speeds, all-in-one high density load module.
• Supports multiple interface types: CXP, QSFP interfaces.
• Facilitates multi-speed tests on a single card.
Layers 2-7 coverage

• Supports mid-range-to-high-scale protocol testing for L2-3 routing/switching
and data center test cases.
• Provides L4-7 capability for all cards.
Same feature set across all speeds

• Provides data plane features for 100/40GE testing.
• Provides L23 protocol coverage for 100/40GE testing.

Load Modules
Load Modules
The Xcellon-Multis family consists of the following models on a single slot card:
• CXP, 100GE single rate module that has 4-ports of 100GE CXP, which is the
highest density 100GE test module.
• CXP 100/40GE dual rate module that has 4-ports of 100GE CXP 12-ports of
40GE QSFP+ (using fan-out technology) providing the highest density 40GE
test module test module.
• 12-ports of 40GE QSFP+ (using fan-out technology) providing the highest
density 40GE test module test module.
Each of these load modules are described as follows:
XM100GE4CXP Xcellon-Multis XM100GE4CXP is a 100-Gigabit Ethernet, single rate load

module. It has 1-slot with 4-ports native CXP interfaces. It provides L2-7 support
and is compatible with XM12 HP rackmount, XM2 desktop, and XG12
rackmount chassis.
You need to select one or more of the following per port:
• 948-0030 CXP 100GE pluggable
• Optical transceivers
• 942-0035 MTP-MTP 24-fiber multimode fiber cable, or point-to-point CXP
Active Optical Cable (AOC)
The XM100GE4CXP load module is shown in the following figure:
Figure 35-1. Xcellon-Multis Module-XM100GE4CXP
XM100GE4CXP Xcellon-Multis XM100GE4CXP+FAN is a 100/40-Gigabit Ethernet, dual rate

+FAN load module. It has 1-slot with 4-ports native CXP interfaces and up to 12-ports
of 40GE via fan-out cables. It provides L2-7 support and is compatible with
XM12 HP rackmount, XM2 desktop, and XG12 rackmount chassis.
You can select one or more of the available media per port of the following:
• 948-0030 CXP 100GE pluggable, optical transceivers.

35 Load Modules
• 942-0035 MTP-MTP 24-fiber multimode fiber cable, or point-to-point CXP

Active Optical Cable (AOC), or CXP-to-3x40GE QSFP Active Optical Cable
(AOC) for 3x40GE fan-out, or MTP-to-MTP passive fiber for 3x40GE Fan-
out. This cable may be used with 948-0028 QSFP 40GBASE-SR4 transceiv-
ers. The XM100GE4CXP+FAN load module is shown in the following fig-
ure:
Figure 35-2. Xcellon-Multis Module-XM100GE4CXP+FAN
XM40GE12QSFP Xcellon-Multis XM40GE12QSFP+FAN is a 40-Gigabit Ethernet load module. It

+FAN has 1-slot with 12-ports of 40GE via fan-out cables and provides L2-7 support.
A quantity of 4 each, 3-meter CXP-to-3x40GE QSFP fan-out cables (942-0054)

are available with this load module. This is compatible with XM12 HP
rackmount, XM2 desktop, and XG12 rackmount chassis.
The XM40GE12QSFP+FAN load module is shown in the following figure:
Figure 35-3. Xcellon-Multis Module-XM40GE12QSFP+FAN

Part Numbers
Part Numbers
Part Numbers for Xcellon-Multis Load Module and Supported Adapters are
provided in the following table.
Table 35-1. Part Numbers for Xcellon-Multis Modules
Model Number Part Description

Number
XM100GE4CXP 944-1100 • 4-ports of 100GE with the CXP

physical interface.
• 100GE only.
• Does not have 40GE or fan-out of
40GE.
XM100GE4CXP+FAN 944-1101 • 4-ports of 100GE and upto 12

ports of 40GE with CXP physical
interface (3x40GE fan-out x 4
ports).
• 100GE and 40GE.
• 40GE fan-out capable (3x40GE).
XM40GE12QSFP+FAN 944-1102 • 12-port 40GE with QSFP physical

interface.
• 40GE only.
• 100GE speed is disabled on all 4-
ports.

35 Specifications
Specifications
Table 35-2. Xcellon-Multis Load Module Specifications
Feature Xcellon-Multis (100 GE Xcellon-Multis (100/40GE Xcellon-Multis (40GE

only) combo) only
Load Modules XM100GE4CXP XM100GE4CXP+FAN XM40GE12QSFP+FAN
Hardware Load Module Specifications
Slot/Ports 1-slot / 4x100GE ports 1-slot / 4x100GE and 1-slot / 12x40GE ports
12x40GE ports
Physical Interface CXP native CXP 4x100GE (native) 12, via fan-out
QSFP 12x40GE (fan-out)
Chassis Capacity: Maximum Number of Cards and Ports per Chassis Model
XG12 Chassis 12 cards: 12 cards: 12 cards:

(940-0005) • 48-ports of 100GE • 48-ports of 100GE • 144-ports of 40GE
• 144-ports of 40GE
XM12 HP Chassis 8 cards: 8 cards: 8 cards:

(941-0009 • 32-ports of 100GE • 32-ports of 100GE • 96-ports of 40GE
• 96-ports of 40GE
XM2 Chassis 1 card: 1 card: 1 card:

(941-0003) • 4-ports of 100GE • 4-ports of 100GE • 12-ports of 40GE
• 2-ports of 40GE
CPU and Memory Multicore processors with 4GB of memory per processor
IEEE802.3ba-2010 100GBASE-SR10 100GBASE-SR10 40GBASE-SR4

Interface Protocols 40GBASE-SR4
Transceiver Support Pluggable CXP, 12-lane, Pluggable CXP, 12-lane, QSFP+ MSA
MMF for 100GE operation MMF for 100GE operation
QSFP+ MSA

Temperature Range
Load Module 16.0” (L) x 12.0” (W) x 1.3” (H)

Dimensions 406mm (L) x 305mm (W) x 33mm (H)
Transmit Feature Specifications
Transmit Engine Wire-speed packet generation with timestamps, sequence numbers, data integrity
signature, and packet group signatures
Max. Streams per 100GE: 128 100GE: 128 40GE: 32 / fan-out link
Port 40GE: 32 / fan-out link

Specifications

only) combo) only
Max. Streams per Supported Supported Supported

Port in Data Center
Ethernet
Stream Controls Rate and frame size change on the fly, sequential and advanced stream scheduler
Minimum Frame Size 100GE: 100GE: 40GE:

• 60 bytes (line rate) • 60 bytes (line rate) • 64 bytes (line rate)
• 49 bytes (< line rate) • 49 bytes (< line rate) • 49 bytes (< line rate)
40GE:
• 64 bytes (line rate)
• 49 bytes (< line rate)
Maximum Frame Size 14,000 bytes
Maximum Fame Size 9,216 bytes

in Data Center
Ethernet
Priority Flow Control 18 line-rate-capable queues with each supporting up to 2,500 byte frame lengths
1 queue supporting up to 9,216 byte frame lengths
Frame Length Fixed, increment by user-defined step, weighted pairs, uniform, repeatable random,
Controls IMIX, and Quad Gaussian
User defined fields Fixed, increment or decrement by user-defined step, sequence, value list, and random
(UDF) configurations. Up to ten, 32-bit wide UDFs are available.
Value Lists (max.) 4 million / UDF 100GE: 4 million / UDF 40GE: 1 million / UDF
40GE: 1 million / UDF
Sequence (max.) 256K / UDF 100GE: 256K / UDF 40GE: 64K / UDF
40GE: 64K / UDF
Error Generation Generate good CRC or force bad CRC, undersize and oversize standard Ethernet
frame lengths, and bad checksum
Hardware Checksum Checksum generation and verification for IPv4, IP over IP, IGMP/GRE/TCP/UDP,
Generation L2TP, GTP
Link Fault Signaling Reports, no fault, remote fault, and local fault port statistics
Latency 100GE: 2.5 nanoseconds 100GE: 2.5 nanoseconds 40GE: 2.5 nanoseconds
Measurement 40GE: 2.5 nanoseconds
Resolution
Intrinsic Latency Removes inherent latency error from 40GE or 100GE port electronics
Compensation
Transmit line clock Ability to adjust the parts per million line frequency over a range of -100 ppm to +100
adjustment ppm per resource group

35 Specifications

only) combo) only
Receive Feature Specifications
Receive Engine Wire-speed packet filtering, capturing, real-time latency and inter-arrival time for each
packet group, with data integrity, sequence and advanced sequence checking
capability
Trackable Receive 100GE: 512K 100GE: 512K 40GE: 128K

Flows per Port 40GE: 128K
Minimum Frame Size 64 bytes at line rate

> 49 bytes not a line rate
Filters (User-Defined 2 SA/DA pattern matchers, 2x16-byte user-definable patterns with offsets capability for
Statistics, UDS) start of: frame, IP, or protocol. Up to 6 UDS counters are available
Hardware Capture 100GE: 2GB 100GE: 2GB 40GE: 2GB per 1, user-
Buffer per Port or 40GE: 2GB per 1, user- selected link of the 3x40GE
Resource Group selected link of the 3x40GE fan-out link resource group
fan-out link resource group
Statistics and Rates Link state, line speed, frames sent, valid frames received, bytes sent/received,
fragments, undersize, oversize, CRC errors, VLAN tagged frames, 6 user-defined
stats, capture trigger (UDS 3), capture filter (UDS 4), 8 QoS counters, data integrity
frames, data integrity errors, sequence and advanced sequence checking frames,
sequence checking errors, ARP, and PING requests and replies
PCS Lanes Port PCS Sync Errors, Illegal Codes, Remote Faults, Local Faults, Illegal Ordered Set,
Statistics Illegal Idle, Illegal SOF, Out Of Order SOF, Out Of Order EOF, Out Of Order Data, Out
Of Order Ordered Set
Latency / Jitter Cut-through, store & forward, forwarding delay, up to 16 time bins latency/jitter, MEF
Measurements jitter, and inter-arrival time
L2/3 Routing, Routing: RIP, RIPng, OSPFv2/v3, ISISv4/v6, EIGRP, EIGRPv6, BGP/BGP+
Bridging, and Timing MPLS: RSVP-TE, RSVP-TE P2MP, LDP, mLDP, BGP RFC 3107, MPLS-TP, MPLS
OAM
MPLS VPN: L2VPN PW, L3VPN/6VPE, 6PE , VPLS-LDP, VPLS-BGP, VPLS-BGP AD
and LDP FEC 129, Inter-AS VPN Option A, B, and C, Seamless MPLS, Carrier
Supporting Carrier (CsC), GRE mVPN, NG MVP (mLDP and RSVP-TE P2MP), EVPN/
PBB-EVPN
High-Availability: BFD, Graceful Restart, MPLS Ping/TraceRoute, LSP BFD, VCCV
BFD, Real-time dynamic label swap for convergence time measurement up to
millisecond accuracy
IP Multicast: IGMPv1/v2/v3, MLDv1/v2, PIM-SM/SSM, PIM-BSR, multicast VPN
Switching: STP/RSTP, MSTP, PVST+/RPVST+, LACP, LLDP, Protocols over LACP
Bundle
Carrier Ethernet: Link OAM, CFM, Service OAM, PBT/PBB-TE, SyncE, PTP
(1588v2), E-LMI

Specifications

only) combo) only
Data Center Ethernet Priority Class-Based Flow Control (IEEE802.1Qbb), FCoE/ FIP, LLDP/DCBX, VNTAG/
VIC, OpenFlow, FabricPath, TRILL, SPBM, VEPA, VXLAN
Broadband Access Broadband: ANCP, PPPoX, DHCPv4 client/server, DHCPv6 client/server, L2TPv2,
Radius Attributes for L2TP, Dual-Stack PPPoX, AMT
Authentication: 802.1x, WebAuth, Cisco NAC

35 Application Support
Application Support
The Ixia application support for Xcellon-Multis CXP load modules is provided in
the following table:
Table 35-3. Xcellon-Multis Application Support
Application Support
IxNetwork Provides wire-rate traffic generation with service modeling

that builds realistic, dynamically-controllable data-plane
traffic. IxNetwork offers the industry's best test solution for
functional and performance testing by using comprehensive
emulation for routing, switching, MPLS, IP multicast,
broadband, authentication, Carrier Ethernet, and data
center Ethernet protocols.
IxAutomate IxAutomate application offers a powerful, customizable test

tool to automate the performance, scalability, and functional
testing of network devices. IxAutomate provides a simple to
use graphical user interface (GUI) to configure custom
automated test scenarios and analyze test results.
IxAutomate provides a rich suite of pre-built tests based on
industry-standard RFCs and customer requirements.
Tcl API Custom user script development for layer 1-7 testing.

Mechanical Specifications
Front Panel The Front panel of Xcellon-Multis load module is shown in the following figure:
Figure 35-4. Front panel of Xcellon-Multis
Led Panel The LED panel specifications are provided in the following table.
Table 35-4. Led panel Specifications of XM100GE4CXP Load Module
Tx Status • OFF indicates port is inactive or no power

• Solid Red indicates link is down
• Solid Green indicates link is up
• Blinking Green indicates Tx is active
Rx Status • OFF indicates port is inactive or no power

• Blinking Red indicates Rx is active with errors
• Blinking Green indicates Rx is active
Mode Status • Solid Red indicates card fault

• OFF indicates that port is in 100G mode
Table 35-5. Led panel Specifications of XM40GE12QSFP+FAN (40GE only)

Load Module
Tx Status • OFF indicates ports are inactive or no power

• Solid Red indicates link is down on all 3 ports
• Solid Yellow indicates link is partially up or
down (any of the 3 ports)
• Solid Green indicates link is up on all 3 ports
Rx Status • OFF indicates port is inactive or no power

Mode Status • Solid Red indicates card fault

• Solid Green indicates that port is in 40G mode

35 Fan-out Capability
Fan-out Capability
The 3x40GE fan-out is a new capability that provides up to 12 independent 40GE
QSFP+ links or generic 40GE fiber links. There are up to three 40GE QSFP+
fiber-based links provided via a cable per 100GE CXP physical port, using all of
the 4-ports of 100GE CXP on the Multis load module.
Fan-out Cable The Xcellon-Multis cable options are described in the following sections.
Options
100GE CXP-to-3x40GE QSFP+ AOC fiber fan-out cables
CXP-to-3x40GE QSFP Active Optical Cable (AOC) cables are used with
Xcellon-Multis XM100GE4CXP+FAN 100/40GE (944-1101) and
XM40GE12QSFP+FAN 40GE (944-1102) load modules.
100GE CXP-to-3x40GE QSFP+ AOC fiber fan-out cables have the following
features:
• Active Optical Cable (AOC)
• Multi-mode fiber (MMF), 850nm
• 942-0053 – 1 meter
• 942-0054 – 3 meter
• 942-0055 – 5 meter
The 100GE CXP-to-3x40GE QSFP+ AOC fiber fan-out cable is shown in the
following figure:
Figure 35-5. 100GE CXP-to-3x40GE QSFP+ AOC fiber fan-out cable
MT-MT 3x40GE passive fiber fan-out cables
The MT-MT 3x40GE passive fiber fan-out cables requires 1 each CXP 100GE
pluggable optical transceiver (948-0030). This combination is compatible with
Xcellon-Multis XM100GE4CXP+FAN 100/40GE (944-1101) and
XM40GE12QSFP+FAN 40GE load modules.
The MT-MT 3x40GE passive fiber fan-out cables have the following features:
• Multi-mode frequency (MMF), 850nm
• F-F key-up compatible with CXP & QSFP optical transceivers

Fan-out Capability
• 942-0060 – 3 meter
• 942-0061 – 5 meter
• Transceivers are sold separately
The MT-MT 3x40GE passive fiber fan-out cable is shown in the following figure:
Figure 35-6. MT-MT 3x40GE passive fiber fan-out cable
CXP point-to-point AOC Cable (no fan-out)

The CXP point-to-point AOC cable has the following features:
• Active Optical Cable (AOC)
• Multi-mode frequency (MMF), 850nm
• 942-0052 – 3 meter
The CXP point-to-point AOC cable is shown in the following figure:
Figure 35-7. CXP point-to-point AOC cable
Features The 100GE fan-out capability has the following features:

• Each 100GE port and transceiver combination has the ability to fan-out to
three 40GE QSFP+ links using a fiber fan-out cable media type, or a plugga-
ble transceiver used with a fiber-only fan-out cable.
• Each 100GE port, when in the 3x40GE fan-out configuration, supports one-
user for all three 40GE links.
• Each 100GE port with a transceiver that uses a fan-out cable to produce
3x40GE links will equally divide and allocate the data and control plane
resources of the 100GE port to each 40GE link.
• There are 32 transmit streams for each of 40GE link in a 3x40GE fan-out con-
figuration and at least 64K Rx PGID capacity per link.
• There is one LED per 100GE CXP port that indicates that the port is in fan-
out mode.

• PCS lanes and Link Fault Signaling port counter support supports link trou-
bleshooting for the entire port.
The Xcellon-Multis load module with CXP-to-3x40GE fan-out fiber cables for a
100GE CXP port with a 100GE transceiver installed, is shown in the following
figure.
Figure 35-8. Xcellon-Multis load module with CXP-to-3x40GE fan-out
Benefits Due to the enormous growth in Internet users and devices, the total bandwidth
requirements of a single switch or router has reached multiple terabits. Devices
that scale up to hundreds of 40GE and 100GE ports, instead of dozens, are
needed to match such huge bandwidth requirements.
Xcellon-Multis family of load modules allows Higher Speed Ethernet testing

using cable fan-out technology. This allows higher ports speeds to fan-out to
several ports (links) of another speed. It also has the following benefits:
• 100GE/40GE fan-out technology separates a phyiscal interface into multiple
interfaces.
• The same features for 100GE and 40GE can be used from a single port or a
group of ports.
• The same features for 100GE and 40GE all able to be used from a single port
or a group of ports.
• Enables higher port densities per chassis – 2x the 100GE capacity and 3x the
40GE capacity.
• A simple fan-out cable allows you to have 3 ports of 40GE QSFP at a lower
cost than a new, full load module.
• Multis provide an efficient way to have 100GE using the native physical port
of CXP, and then have in the same port of the same card 3x40GE QSFP inter-

Fan-out Capability
faces. A second card with 40GE QSFP naïve interface is not needed. This
saves a slot in your chassis.
• The fan-out technology allows the user to have 100GE/40GE port all emanat-
ing from a single card. Compared to traditional Ixia cards, this saves power
because you do not have to have two or three different cards in the chassis to
perform 100GE/40GE tests.
• Every chassis in the lab produces less heat output to be cooled with less total
number of load module installed in the chassis. Multis reduces the number of
load modules in the chassis by being:
• High port density
• Providing Fan-out technology
Transceivers and The Xcellon-Multis family supports optical transceivers and fiber cables for each
Cables of the physical interfaces that are supported.
The following are the two types of 3x40GE fan-out cables:

• Active Optical cable (AOC): CXP to (3) QSFP+, fiber, active, fan-out cable.
• Fiber fan-out cable: MTP to (3) MTP QSFP+, fiber, passive, fan-out cable.
Active Optical Cable
The following tables list the specifications of the AOC cable.

Table 35-6. CXP to 3-QSFP+ 40GE AOC fan-out
CXP AOC Cable length Cards/Adapters to Interoperate

part number with
ICD120GVP2420-05 5.0 m MK, 4x40GE, K2
1110251303 3.0 m MK, 4x40GE, K2
1110251305 5.0 m MK, 4x40GE, K2
1110251307 7.0 m MK, 4x40GE
1110251310 10.0 m MK, 4x40GE
Table 35-7. CXP 100GE Active Optical Cable

part number with
FCBGD10CD1C03/ 5.0 m MK, K2

ICD120GVP2410-03
FCBGD10CD1C05/ 3.0 m MK
ICD120GVP2410-05


part number with
ICD120GVP2410-10
ICD120GVP2410-20
Fibre Fan-out Cable
The following table lists the specifications of the fibre fan-out cable.
Table 35-8. MTP to (3) MTP QSFP+, fiber, passive, fan-out
MTP Fan-out Cable length Cards/Adapters/Optics to

part number Interoperate with
Custom 1.0 m QSFP optic, MK, 4x40GE, Combo

Fan-out Capability
CXP CXP is useful in the clustering and high-speed computing areas. It is about one-
fourth the size of a CFP transceiver providing higher density network interfaces.
It is an excellent low cost 100GE system for Multimode fiber cables.
CXP is a copper connector system. It provides twelve 10 Gbps links suitable for
100 Gigabit Ethernet, three 40 Gigabit Ethernet channels, or twelve 10 Gigabit
Ethernet channels or a single Infiniband 12× QDR link.
CXP components are low cost, field proven and available in volume.
The following are the CXP formats:

• Pluggable transceiver
• Active Optical Cable
The following figure shows the CXP Active Copper, Optical (pluggable), Active
Optical:
Figure 35-9. CXP Active Copper, Optical (pluggable), Active Optical

QSFP The Quad (4-channel) Small Form-factor Pluggable (often abbreviated as QSFP
or QSFP+) is a compact, hot-pluggable transceiver used for data communications
applications. It interfaces a network device (switch, router, media converter or
similar device) to a fiber optic cable.
The QSFP specification supports Ethernet, Fibre Channel, InfiniBand and

SONET/SDH standards with different data rate options. QSFP+ transceivers are
designed to support Serial Attached SCSI, 40G Ethernet, 20G/40G Infiniband,
and other communications standards. QSFP modules increase the port-density by
3x-4x compared to CFP modules.
The following figures show the QSFP+ Pluggable and Cable modules:
Figure 35-10.QSFP+ Pluggable module
Figure 35-11. QSFP+ Cable module

Chapter 36: IXIA PerfectStorm Load
36 Modules
This chapter provides details about PerfectStorm 10GE and 40GE family of load
modules—specifications and features.
Ixia’s PerfectStorm family of load modules is a scalable solution for testing

converged multi-play services, application delivery, and network security
platforms for both wired and wireless networks.
The PerfectStorm product family consists of a new next generation chassis

(XGS12), an XGS integrated system controller for both IxLoad and
BreakingPoint and two load modules 8x10GE and 2x40GE.
The PerfectStorm10GE and 40GE load modules have two variants, fusion
(IxLoad and BreakingPoint) and non-fusion (IxLoad only). The key feature of
PerfectStorm 10GE/40GE NG cards is the fusion between IxLoad and
BreakingPoint applications.
PerfectStorm supports the following:

• both IxLoad and BreakingPoint software applications; BPS runs on the fusion
variants of the load module
• native 40GE QSFP+ interfaces
• line-rate application performance per interface
• hardware-based acceleration for SSL and IPsec performance

IXIA PerfectStorm Load Modules
36 Key Features
Key Features
The key features of PerfectStorm load modules are as follows:
Unified Applications and Security Test Platform
PerfectStorm is a unified applications and security test platform, with support for
BreakingPoint and IxLoad software.
Networking Interfaces per Blade

• 8 x 10G
• 2x 40G
Blended Application Traffic
PerfectStorm Fusion can create blended application traffic and current security
attacks with a very high count of concurrent wired and wireless users from a
single 11u chassis.
Massive Scale Real-World Traffic Conditions
PerfectStorm tests and validates IT systems under controlled real-world scenarios

that model your own unique environments.
It understands actual performance, system limitations, and real security posture
in a better way, to right size data centers and eliminate incidents in production.
It generates stateful applications and malicious traffic that simulate millions of
real-world end-user environments to test and validate infrastructure, a single
device, or an entire system. This includes complex data, video, voice, storage,
and network application workloads.
Real Attacks
• 6,000+ live security attacks, 35,000+ pieces of live malware found in enter-
prise, core, and mobile networks, 180+ evasions
• DDoS and botnet simulation and custom attacks
• Research and frequent updatesHardware-based Acceleration
PerfectStorm provides hardware-based acceleration for SSL and IPsec.
Multi-user Environment
PerfectStorm’s multi-user environment leverages the per port user ownership

model for all ports on the test modules installed into the chassis.
High-performing Business Applications
PerfectStorm ensures high-performing, and more available and secure business

applications.

Key Features
Disaster Recovery
PerfectStorm validates disaster recovery and business continuity.
Reduced Legal Exposure
PerfectStorm provides reduced legal exposure due to data loss by validating

security using the industry's most up to date application and threat intelligence.

36 Platform Support
Platform Support
PerfectStorm is equipped with powerful multi-core, multi-threaded network
processors, to satisfy the testing needs of equipment manufacturers having
higher-density 10GE and 40GE equipments. As service providers and large
enterprises prepare to deploy these equipments in their own networks, they must
test and verify performance and functionality prior to deployment.
PerfectStorm’s single, integrated system equipped with 12 PerfectStorm blades

allows control of application traffic to nearly a terabit, up to 720 million
concurrent connections, and new TCP connection rates of up to 24 Million. The
hardware-based acceleration supports massive encryption levels. The system
uses inline field programmable gate arrays (FPGAs) for enhanced accuracy
pertaining to latency measurements with a resolution of 10ns.
PerfectStorm is compatible with XGS12 which is a 12-slot Chassis. The Chassis

architecture supports easy setup and management of high scale, multi-user
system. The XGS12 chassis includes a pluggable system controller for chassis
management and web-based UI. This chassis is backward compatible with XM2/
XM12 blades.
For more information on XGS12, see Chapter 7, XGS12 Chassis.

Load Modules
Load Modules
PerfectStorm load module comprises a two board set, the Main Board and the
PHY Card. The Main Board contains the backplane interface, processors and
FPGAs. The card occupies one slot in the XGS12 chassis and consumes no more
than 400W of power.
The PerfectStorm family consists of the following models:

• PerfectStorm 10GE 8-port (SFP+)
• PerfectStorm Fusion 10GE 8-port (SFP+)
• PerfectStorm 40GE 2-port (QSFP+)
• PerfectStorm Fusion 40GE 2-port (QSFP+)
Each of these load modules are described as follows:
PS10GE8 PerfectStorm PS10GE8 is a 8 port 10-Gigabit Ethernet, load module with SFP+
interface. Each 10GE port uses of 1/8th of the network processor and memory
resources available on the load module, allowing delivery of application traffic at
wire-speeds for each port.
It supports only IxLoad software and is compatible with XGS12 chassis.
The PS10GE8 load module is shown in the following figure:
Figure 36-1. PerfectStorm Module-PS10GE8
PS10GE8NG PerfectStorm PS10GE8NG is a 8 port 10-Gigabit Ethernet, fusion load module

with SFP+ interface. This mode provides extra flexibility to allocate all available
NP resources and memory available on a single module while using a single 10
GE interface to transmit or receive the traffic. Ixia test applications transparently
configure the allocation of NP resources to achieve the maximum performance.
It supports IxLoad and BreakingPoint software and is compatible with XGS12
chassis.
The PS10GE8NG load module is shown in the following figure:

36 Load Modules
Figure 36-2. PerfectStorm Module-PS10GE8NG
PS40GE2 PerfectStorm PS40GE2 is a 2 port 40-Gigabit Ethernet, load module with QSFP+
interface. Each 40GE port uses of ½ of the network processor and memory
resources available on the load module, allowing delivery of application traffic at
wire-speeds for each port.
It supports only IxLoad software and is compatible with XGS12 chassis.
The PS40GE2 load module is shown in the following figure:
Figure 36-3. PerfectStorm Module-PS40GE2
PS40GE2NG PerfectStorm PS40GE2NG is a 2 port 40-Gigabit Ethernet, fusion load module

with QSFP+ interface. This mode provides extra flexibility to allocate all
network processor and memory resources available on a load module to a single
40GE port. Ixia test applications transparently configure the allocation of NP
resources to achieve the maximum performance.
It supports IxLoad and BreakingPoint software and is compatible with XGS12
chassis.
The PS40GE2NG load module is shown in the following figure:
Figure 36-4. PerfectStorm Module-PS40GE2NG

Part Numbers
Part Numbers
Part Numbers for PerfectStorm Load Modules and supported adapters are
provided in the following table.
Table 36-1. Part Numbers for PerfectStorm Modules
Model Number Part Description

Number
PS10GE8NG 944-1200 • 8-ports of 10GE with the SFP+

physical interface.
• SSL and IPsec hardware accelera-
tion.
PS10GE8 944-1204 • 8-ports of 10GE with the SFP+

physical interface.
tion.
PS40GE2NG 944-1201 • 2-ports of 40GE with the SFP+

physical interface.
tion.
PS40GE2 944-1205 • 2-ports of 40GE with the SFP+

physical interface.
tion.

36 Specifications
Specifications
Table 36-2. PerfectStorm Load Module Specifications
Feature PerfectStorm PerfectStorm PerfectStorm PerfectStorm

10GE Fusion 10GE 40GE Fusion 40GE
Load Modules PS10GE8 PS10GE8NG PS40GE2 PS40GE2NG
Hardware, Load Module Specifications
Number of Ports 8 8 2 2
Physical Interface 8-port, 10GE SFP+ 8-port, 10GE SFP+ 2-port, 40GE 2-port, 40GE
QSFP+ QSFP+
Transceiver Support 10GBASE-SR/SW 10GBASE-SR/SW QSFP+, QSFP+,

(pluggable (850 nm) (850 nm) 40GBASE-SR4 40GBASE-SR4
transceivers) 10GBASE-LR/LW 10GBASE-LR/LW
(1310 nm) (1310 nm)
Memory 64GB 64GB 64GB 64GB
Hardware Encryption Yes Yes Yes Yes

Offload
Hardware-Based N/A N/A N/A N/A

Traffic Capture
FPGA Offload Yes Yes Yes Yes
IPv4, IPv6, UDP, TCP Hardware checksum generation
Load Module 16" (L) x 12.00" (W) x 1.3" (H)

Dimensions 406 mm (L) x 305 mm (W) x 33 mm (H)

Temperature Range
Chassis Capacity
Cards per Chassis 12 12 12 12
Port Density per 144-port, 10GE 144-port, 10GE 24-port, 40GE 24-port, 40GE
XGS12 Chassis SFP+ SFP+ QSFP+ QSFP+
Chassis Compatibility XGS12 XGS12 XGS12 XGS12
XGS12 Chassis XGS12-HS (940- XGS12-HS (940- XGS12-HS (940- XGS12-HS (940-
Bundles 0006) 0006) 0006) 0006)
XGS12 (940-0007) XGS12 (940-0007)

Specifications
Feature PerfectStorm PerfectStorm PerfectStorm PerfectStorm

10GE Fusion 10GE 40GE Fusion 40GE
Transceiver and Cable Support
Part number: 988-0011: Part number: 948-0028:

SFP+, 10Gb/1Gb SR optical Xcvr, 850nm QSFP+ 40GBASE-SR4 optical
(cable included) transceivers
Part number: 988-0012: Part number: 942-0041:
SFP+, 10Gb/1Gb LR optical Xcvr, MT 12-fiber MMF cable, 3-meter length
1310nm

36 Application Support
Application Support
The Ixia application support for PerfectStorm load modules is provided in the
following table:
Table 36-3. PerfectStorm Application Support
Hardware Application Support
PerfectStorm PS10GE8 IxOS, IxLoad, TCL API
PerfectStorm Fusion IxOS, IxLoad, BreakingPoint, TCL

PS10GE8NG API
PerfectStorm PS40GE2 IxOS, IxLoad, TCL API
PerfectStorm Fusion IxOS, IxLoad, BreakingPoint, TCL

PS40GE2NG API

Front Panel The Front panel of the 8x10GE and 2x40GE PerfectStorm load modules are
shown in the following figures (applies to Fusion and non-Fusion versions):
Figure 36-5. Front panel of 8x10GE PerfectStorm PS10GE8
Figure 36-6. Front panel of 8x10GE Fusion PerfectStorm PS10GE8NG
Figure 36-7. Front panel of 2x40GE PerfectStorm PS40GE2
Figure 36-8. Front panel of 2x40GE Fusion PerfectStorm PS40GE2NG
LED Panel The LED panel specifications are provided in the following table.
Table 36-4. LED panel specifications of PS10GE8(NG) and PS40GE2(NG)
Load Modules
Link • OFF indicates link is down

• Solid Green indicates link is up
Tx • Off indicates Tx is inactive

Rx/Err • Off indicates Rx is inactive


36 Mechanical Specifications

Chapter 37: IXIA Xdensity
37 XDM10G32S/8S Load
Modules
XDM10G32S Load This section provides details about Xdensity family of load modules—
Modules specifications and features. The IxExplorer name of this load module is
XDM10G32S.
Xdensity is a 32 port load module with 10GE density per port. Each slot in this
load module consists of 32 ports that can scale up to 384 ports in a single XM12
chassis. The high scalability feature of Xdensity load module provides test
solutions for high density 10GE converged data center switches and routers.
The key features of Xdensity load module are mentioned as follows:
Key Features
• An optimum solution for testing ultra-high-density 10GE switches
• Economical, energy-efficient solution for the build-out of large 10GE test-
beds
• Industry's leading 10GE SFP+ port density:
• 32-ports of 10GE in a single-slot load module
• 384-ports of 10GE SFP+ interfaces in a single 10U rackmount chassis
• Up to 4 users can access the load module at one time, with 8-ports per user
• Compatible with Ixia’s XM2, XM12, and XG12 chassis
• Support for host protocol emulation to test layer 3 devices: ARP, NDP, IPv4,
IPv6, IGMP, MLD, and DHCPv4/v6 (client and server)
• A targeted set of routing and bridging protocols are supported per port that
can be configured with any mix of supported protocols required: BFD,
BGPv4/v6, CFM, EIGRP, ISISv4/v6, ISIS-DCE, LDP, Link OAM, OSPFv2,
OSPFv3, PIM-SM/SSM-v4/v6, RIP, RIPng, STP/RSTP/MSTP, RSVP-TE
• Data center-ready – with data center bridging LLDP/DCBX, FCoE, FIP, FCF,
and priority-based flow control (PFC, IEEE802.1Qbb) protocol support
• Built with multicore processor technology

IXIA Xdensity XDM10G32S/8S Load Modules
37
The XDM10G32S load module is shown in the following figure:
Figure 37-1. Xdensity Load Module(XDM10G32S)
XDM10G8S Load This section provides details about Xdensity family of load modules—
Modules specifications and features. The IxExplorer name of this load module is
XDM10G8S.
Xdensity is a 8 port load module with 10GE density per port. Each slot in this
load module consists of 8 ports that can scale up to 96 ports in a single XM12 or
XG12 chassis. The high scalability feature of Xdensity load module provides test
solutions for high density 10GE converged data center switches and routers.
The key features of Xdensity load module are mentioned as follows:

• An optimum solution for testing high density network switches that requires
higher per port levels of L23 protocol emulation scale and performance. The
XDM10G8S offers up to 4 times higher protocol performance per port com-
pared to the XDM10G32S.
• Energy-efficient solution for 10GE test environments
• 8-ports of 10GE in a single-slot load module
• 96-ports of 10GE SFP+ interfaces in a single 10U rackmount chassis:
• Compatible with Ixia’s XM2, XM12, and XG12 chassis
• Support for host protocol emulation to test layer 3 devices: ARP, NDP,
IPv4, IPv6, IGMP, MLD, and DHCPv4/v6 (client and server)
• A targeted set of routing and bridging protocols are supported per port that
can be configured with any mix of supported protocols required: BFD,
BGPv4/v6, CFM, EIGRP, ISISv4/v6, ISIS-DCE, LDP, Link OAM,
OSPFv2, OSPFv3, PIM-SM/SSM-v4/v6, RIP, RIPng, STP/RSTP/MSTP,
RSVP-TE
• Data center-ready – with data center bridging LLDP/DCBX, FCoE, FIP,
FCF, and priority-based flow control (PFC, IEEE802.1Qbb) protocol sup-
port
• Built with multicore processor technology
• Compatible with Ixia's XM2 and XM12 chassis
• Compatible with Ixia's XG12 chassis

The XDM10G8S load module is shown in the following figure:
Figure 37-2. Xdensity Load Module(XDM10G8S)

37 Part Numbers
Part Numbers
Table 37-1. Part Numbers for Xdensity Load Module
XDM10G32S 944-1080 Xdensity, XDM10G32S,

Ultra-high density, 10-
Gigabit Ethernet load
module with 32-ports of
SFP+ interfaces with L2-3
data plane and limited
routing protocol emulation
support; for XG12 (940-
0005) Rackmount chassis,
XM12-02 (941-0009) High
Performance chassis and
XM2-02 (941-0003) portable
chassis; REQUIRES one or
more SFP+ transceiver
options: 10GBASE-SR/SW
(948-0013), or 10GBASE-
LR/LW (948-0014); NOTE: If
XM12-01 (941-0002)
chassis is used with this load
module, the FRU-
XDM10G8S 944-1098 Xdensity, XDM10G8S, 10-

Gigabit Ethernet load
module with 8-ports of SFP+
interfaces with L2-3 routing
protocol emulation and data
plane support; for XG12
(940-0005) Rackmount
chassis, XM12-02 (941-
chassis and XM2-02 (941-
0003) portable chassis;
REQUIRES one or more
SFP+ transceiver options:
10GBASE-SR/SW (948-
0013), or 10GBASE-LR/LW
(948-0014); ); NOTE: If
XM12-01 (941-0002)
chassis is used with this load
module, the FRU-

Specifications
Specifications
Table 37-2. Xdensity Load Module Specifications
Feature Xdensity 32 port Xdensity 8 port
Load Modules XDM10G32S XDM10G8S
Number of ports per module 32 8

module
Maximum ports per chassis XM12 High XM12 High

Performance(4000W): 384ports Performance(4000W): 384ports
10GESFP+ 10GESFP+
XM2 Desktop: 64-ports XM2 Desktop: 64-ports
10GESFP+ 10GESFP+
XG12: 384 ports XG12: 384 ports
SFP+ transceiver support • 10GBASE-SR/SW (multimode fiber)

• 10GBASE-LR/LW (single mode fiber)
• 10GBASE-CR (passive, copper twinaxial)
Multi-core processor technology Yes Yes
Frame Size Minimum Frame Size at Line Minimum Frame Size at Line
Rate: 64 Rate: 64
Minimum Frame Size - may not Minimum Frame Size - may not
be at Line Rate: 64 be at Line Rate: 64
Maximum Frame Size: P0: Maximum Frame Size: P0:
9216B 9216B
others 2500B others 2500B
Interface protocols IEEE8002.3ae10GE LAN IEEE8002.3ae10GE LAN
Host protocol emulationsupport ARP, NDP, IPv4, IPv6, IGMP, ARP, NDP, IPv4, IPv6, IGMP,
MLD and DHCPv4/v6 MLD and DHCPv4/v6
(Client+Server) (Client+Server)
Routing protocol emulation BFD, BGPv4/v6, CFM, EIGRP, BFD, BGPv4/v6, CFM, EIGRP,
support ISISv4/v6, ISIS-DCE, LDP, Link ISISv4/v6, ISIS-DCE, LDP, Link
OAM, OSPFv2, OSPFv3, PIM- OAM, OSPFv2, OSPFv3, PIM-
SM/SSM-v4/v6, RIP, RIPng, SM/SSM-v4/v6, RIP, RIPng,
STP/RSTP/MSTP, RSVP-TE STP/RSTP/MSTP, RSVP-TE
Performance benchmark tests RFC 2544, RFC 2889, RFC RFC 2544, RFC 2889, RFC
3819 3819
Number of transmit flows per Billions Billions

port (sequential values)
Number of transmit flows per Millions Millions

port (non-sequential values)

37 Specifications
User-Defined Fields (UDF) Counter, Value List, and Nested Counter, Value List, and Nested
Counter UDFs Counter UDFs
Transmit engine Wire-speed packet generation Wire-speed packet generation

with timestamps, sequence with timestamps, sequence
numbers, data integrity numbers, data integrity
signature, and packet group signature, and packet group
signatures signatures
User defined field features Fixed, increment or decrement Fixed, increment or decrement
by userdefined step, value list, by userdefined step, value list,
and nested UDF and nested UDF
Data field pattern per stream Random, increment (word/ Random, increment (word/
byte), decrement (word/byte) byte), decrement (word/byte)
Frame length controls Fixed, uniform random, auto, Fixed, uniform random, auto,
increment by user-defined step, increment by user-defined step,
dynamic frame rate change, dynamic frame rate change,
and frame size change on the and frame size change on the
fly fly
Error generation CRC good, bad CRC good, bad
IPv4, UDP, TCP, ICMP, Hardware checksum generation Hardware checksum generation
ICMPv6, IGMP checksum and verification and verification
Receive engine Wire-speed packet filtering, Wire-speed packet filtering,

data integrity, real-time latency, data integrity, real-time latency,
and sequence checking for and sequence checking for
each packet group each packet group
Trackable receive flows 8K per port 8K per port
Filters 48-bit source/destination 48-bit source/destination

address, 2x128-bit user- address, 2x128-bit user-
definable pattern and offset, definable pattern and offset,
frame length range, CRC error, frame length range, CRC error,
data integrity error, sequence data integrity error, sequence
checking error, IP/TCP/ UDP checking error, IP/TCP/UDP
checksum error checksum error
Statistics and rates Link state, line speed, frames Link state, line speed, frames
(counter size: 64 bits) sent, valid frames received, sent, valid frames received,
bytes sent/received, fragments, bytes sent/received, fragments,
undersize, oversize, CRC undersize, oversize, CRC
errors, VLAN tagged frames, 6 errors, VLAN tagged frames, 6
userdefined stats (UDS), data userdefined stats (UDS), data
integrity frames, data integrity integrity frames, data integrity
errors, sequence checking errors, sequence checking
frames, and sequence checking frames, and sequence checking
errors errors

Specifications
Intrinsic latency adjustment Ability to remove inherent Ability to remove inherent

latency from any MSA- latency from any MSA-
compliant 10GE SFP+ compliant 10GE SFP+
transceivers without factory transceivers without factory
support support
Transmit line clock adjustment Ability to adjust the parts per Ability to adjust the parts per
million (ppm) line frequency million (ppm) line frequency
over a range of +/-100 ppm over a range of +/-100 ppm
Operating temperature range 41°F to 104°F (5°C to 40°C), 41°F to 104°F (5°C to 40°C),
ambient air temperature ambient air temperature
Load module dimensions 15.95'' (L) x 12.00'' (W) x 1.28'' 15.95'' (L) x 12.00'' (W) x 1.28''
(H) 405mm (L) x 305mm (W) x (H) 405mm (L) x 305mm (W) x
33mm (H) 33mm (H)
Load module weights Module only: 7.1 lbs. (3.2 kg) Module only: 7.1 lbs. (3.2 kg)
Shipping weight: 9.4 lbs. (4.3 Shipping weight: 9.4 lbs. (4.3
kg) kg)
Tranceiver Type SFP+ SFP+
Direct Attach Copper No Yes
LED No No
ppm Adjust range +/-100ppm +/-100ppm
ppm Adjust port/card Card Card
Trigger out No No
External Clock In(Frequence) No No
External Clock Out No No
Ambient Operating 5-40 5-40

Temperature Range (C)
Timestamp - Resolution 20ns 20ns
Timestamp - High Resolution No No
Timestamp - End of Frame No No

Instrumentation
Timestamp - Floating No No
Intrumentation
IEEE802.3x Flow control No No
WAN No No
Number of streams in 16 16
Advanced Scheduler Mode
(Data Center Mode)

37 Specifications
Transicevier Intrinsic Latency No No

Calibration
Intrinsic Latency Yes Yes
Data Integrity Yes Yes
Auto Instrumentation Yes Yes
Preamble - Changeable No No
Content
Preamble - Byte Count Mode No No
Preamble - SFD Detect Mode Yes Yes
Preamble - Cisco CDL Mode No No
Xdensity Four User As many as Four users can operate on a single Xdensity load module. A user can
Support own from one to four port resource groups per load module. 32 ports of Xdensity
is divided into four resource groups and each resource group consists of 8 ports
defined as follows:
• Resource group 1: Ports 1-8 (Port 1 is resource group Master)
A user can own non-consecutive resource group (i.e. resource group 1 and
resource group 4). Port Cluster specifications are as follows:
• A Port Cluster may be owned by exactly one user
• Taking ownership of any un-owned port within the port cluster will automati-
cally force ownership of the entire Port Cluster. Ownership of some (but not
all) ports within a Port Cluster is not a legal condition.
• Releasing ownership of any owned port within a Port Cluster will automati-
cally force release of ownership of all ports within that Port Cluster.
• Reboot of CPU must take place through the Resource Group Master. If user
wish to reboot for example port two entier resource group that is port one to
port eight gets re-booted.
• User can only Telnet to a Resource Group Master
• Frequency adjustment (PPM Adjust) functionality is available across the
entire Xdensity load module. If there is one owner across an entire Xdensity
load module then the user will be allowed to change PPM value for the card.
If more than one user owns Port Clusters across an Xdensity load module,
then PPM cannot be changed by anyone.

Chapter 38: IXIA Stream Extraction
38 Modules
The Stream Extraction module has three ports: two test ports and one monitor
port. The monitor port has up to eight pattern matchers that you can configure. In
addition, there are AND/OR operations to the pattern matching that do not exist
in other module.
Figure 38-1. AFM1000SP-01 Load Module
You can configure the pattern matching based on the MAC address, IP Address,
or TCP/UDP address.

IXIA Stream Extraction Modules
38 Part Numbers
Part Numbers
The part numbers are shown in Table 38-1. Items without a Price List
AFM1000SP-01 AFM1000SP-01 3 port Stream Extraction module,

port 1 RJ-45 copper, port 2/3 RJ-45
Dual PHY copper/fiber.
Specifications
The load module specifications are contained in the following table.
Table 38-2. AFM1000SP-01 Load Module Specifications
AFM1000SP-01
# ports 3 (to capture, one analyzer)
Data Rate 10/100/1000 Mbps
Connector RJ-45 (Copper) port 1

RJ-45 Dual PHY (Copper and Fiber) port 2/3
Capture buffer size N/A
Captured packet size N/A
Streams per port N/A
Advanced scheduler streams N/A

per port
Flows per port N/A
Preamble size: min-max N/A
Frame size: min-max N/A
Inter-frame gap: N/A

min-max
Inter-burst gap: min-max N/A
Inter-stream gap: N/A

min-max
Latency N/A

Port LEDs
Port LEDs
Each port incorporates a set of LEDs, as described in Table 38-2 on page 38-2.
Table 38-3. AFM1000SP-01 Load Module Port LEDs
LED Label Usage
Link/Tx Color is used to indicate the link speed:

(Upper • 1000Mbps–Green
LED)
• 10Mbps–Yellow
Statistics
Statistics counters for AFM1000SP-01 cards may be found in Table B-28 on
page B-157.

38 Statistics

Chapter 39: IxVM
39
IxVM is a software-based test platform that enables you to turn standard Linux
Ethernet ports into virtual Ixia ports. IxVM can create virtual Ixia ports from the
virtual Ethernet ports on a Linux virtual machine (VM), or from the physical
Ethernet ports on a physical Linux server.
To configure the traffic generated by the virtual Ixia ports, you use compatible
versions of Ixia applications such as IxExplorer, IxNetwork, and IxLoad. When
you use these applications, working with a virtual Ixia port is the same as
working with a real chassis, with only a few minor differences.

IxVM
39
IxVM offers the following benefits:
• Low hardware cost - you can use low-cost Linux servers or dedicated virtual-
ization servers to generate traffic.
• More efficient use of hardware - the same Linux servers used to generate Ixia
traffic can also be used for other non-Ixia applications, or the virtual Ixia
ports can be hosted on a virtualization server used to host other applications.
• Choice of deployment models - IxVM components are supplied as pre-con-
figured .ova templates or as standalone RPM packages for quick deployment.
• Rapid deployment - Virtual Ixia ports can be instantiated as necessary, used to
generate traffic, and then destroyed when no longer needed, releasing system
resources for other uses.
• Ease of Use - IxVM-aware Ixia applications are nearly identical to the stan-
dard versions, reducing learning time.
• Reduced System Administration - because the IxVM chassis is virtual, it does
not have to be housed in a lab or monitored.
In this section:
• Features
• Requirements
• Licensing
Features IxVM main features include:

• Support for VMware vSphere, KVM or Xen hypervisors.
• Ixia-enhanced kernel OVA template for full functional routing and switching
testing.
• Reduced-footprint rpm-based installers for KVM or Xen and bare-metal
Linux deployments.
• 32 bit Ixia Kernel self-extracting images for KVM or Xen hypervisors.
• Discovery service that finds virtual Ixia ports and adds them to list of avail-
able ports in the test application.
• Deployment of IxVM software upgrades using Ixia Deployment Wizard.
• Jumbo frame generation for high-throughput testing.
• Support for many IxNetwork and IxLoad protocols.
Requirements IxVM requires the following:
Hardware
IxVM Server: IxVM server requires Windows 7 32-bit.
ESX(i) deployments: IxVM runs on any virtualization server that ESX(i)

supports.

IxVM
KVM, Xen or other deployments: For KVM or Xen and bare-metal deployments,
Ixia recommends a high-performance server with CPUs that include
virtualization extensions such as Intel-VT or AMD-V. A high-end application
server is available from Ixia - contact your Ixia sales representative for more
information.
Hypervisor / Host OS
IxVM supports the following hypervisors or host OSes:

• VMware ESXi 5.0 or ESXi 5.1 for vSphere deployments (OVA deployments)
• KVM (QEMU) over CentOS 6.3 64-bit (KVM self-extracting deployments)
• Xen over CentOS 5.6 64-bit (Xen self-extracting deployments)
VM Operating Systems (Guest OS)
IxVM virtual ports can be created on any VM running one of the following
operating systems:
• Ixia-enhanced kernel
• RedHat Enterprise Linux 6.3, 32-bit
• CentOS 6.3, 32-bit
• SUSE Linux Enterprise Server 11, 32 bit
Distribution Methods
IxVM is distributed using a variety of methods. The table below lists how IxVM
is distributed for supported combinations of hypervisor and guest OS.
Guest OS Distribution Method
Hypervisor or Host OS Ixia Kernel RedHat/CentOS/SUSE
VMware ESXi 5.0 OVA/RPM RPM
VMware ESXi 5.1 OVA/RPM RPM
KVM (QEMU) over CentOS 6.3 64-bit RPM/Self-extracting RPM

image
Xen over CentOS 5.6 64-bit RPM/Self-extracting RPM

image
Note: The Ixia Kernel rpm should only be used for upgrading to newer
versions of IxVM using the Deployment Wizard.

IxVM
39
VM Discovery
Discovery Server discovers virtual Ixia ports, and adds them to the list of
available ports in Ixia testing applications. You can download Discovery Server
from the IxVM page of Ixia's website.
Update Utility
Deployment Wizard updates the IxVM platform with new versions of the IxVM
software. You can download Deployment Wizard from the IxVM page of Ixia's
website.
Ixia Application Software
The following applications are supported on the IxVM platform:

• IxNetwork
• IxExplorer
• IxLoad
You can download all three from Ixia's website.
The following tables lists the Ixia applications you can run on each combination
of hypervisor and guest OS:
Guest OS
Hypervisor or Host Ixia Kernel

OS
VMware ESXi 5.0 IxExplorer

IxNetwork
IxLoad

IxNetwork
IxLoad
KVM (QEMU) over IxExplorer

CentOS 6.3 64-bit IxNetwork
Xen over CentOS 5.6 IxExplorer

64-bit IxNetwork

IxVM
Guest OS
Hypervisor or Host OS RedHat/CentOS 6.3 32-bit

IxNetwork

IxNetwork
KVM (QEMU) over CentOS 6.3 64-bit IxExplorer

IxNetwork
Xen over CentOS 5.6 64-bit IxExplorer

IxNetwork
Guest OS
Hypervisor or Host OS SUSE LINUX ES 11 32-bit

IxNetwork

IxNetwork
KVM (QEMU) over CentOS 6.3 64-bit IxExplorer

IxNetwork
Xen over CentOS 5.6 64-bit IxExplorer

IxNetwork
CentOS 5.6 64-bit on bare metal
About the Red Hat and CentOS Kernels
RedHat Enterprise Linux 6.x and CentOS 6.x are based on the same kernel.
RedHat Enterprise Linux requires a subscription, in return for which Red Hat Inc.
provides support and other services. CentOS is the Community Enterprise
edition, and is free. The same RPM packages can be compiled and installed on
both RedHat and CentOS.
Licensing The following are the licensing requirements of IxVM and its related Ixia
components:
Licensed:
• IxVM Server requires a license.
• IxLoad, IxNetwork, and IxNetwork-FT require licenses.

IxVM
39
Note: All IxVM-enabled test applications such as IxVM Server, IxExplorer,

IxNetwork/IxNetwork-FT and IxLoad use floating licenses, meaning that a
specified license server stores a number of licenses that can be re-used
alternatively by a number of installed test applications.
Each time a test application starts, one license is used from those available on
the licensing server. This allocation process continues as more applications
request licenses, until the pool of remaining licenses is depleted.
For each of the test applications, you specify the licensing server in the
following locations:
• For IxVM Server, specify the server host on the TOOLS > OPTIONS > GEN-
ERAL tab.
• For IxNetwork-FT, specify the server host on the IxExplorer TOOLS >
OPTIONS > LICENSE MANAGEMENT tab.
• For IxNetwork, specify the server host on the FILE > TOOLS > LICENSING
tab.
• For legacy Network-FT TCL scripts, follow the instructions for setting the
license server through IxExplorer / Network-FT. Once you set the Explorer /
Network-FT license server, you can run your TCL scripts.
• For IxLoad, specify the server host by clicking OPTIONS > LICENSE
SERVER on the toolbar.
If you change the license server location in any of the test applications, you
must restart the application for the new location to take effect.
The license server host must have the IxProxy service running on it to traverse
any firewalls between the license server host and the hosts running the test
applications. IxProxy is supplied with IxVM Server and must be manually started
using the SERVICES - ADMINISTRATIVE tool of Windows.
Not Licensed:
• IxExplorer does not require a license.
• Analyzer does not require a license.
• Deployment Wizard does not require a license
Note: The new Subscription Licensing model for IxVM ports, will impose to have
installed on the license server at least the same number of licenses as the
number of ports from the virtual chassis.
For example, if on the virtual chassis there are 10 ports, then on the license
server there should be at least 10 Tier-3 licenses.
The Ixia licensing process is described in the Ixia Licensing Guide.

IxVM
IxVM Deployment Models

There are three general ways that you can deploy IxVM:
• vSphere: In a vSphere deployment, you use vSphere to create VMs that are
based on the Ixia kernel OVA template or on one of the supported Linux dis-
tributions.
• KVM or Xen: In a KVM or Xen deployment, you install IxVM disk images
on a KVM or Xen server, and the supporting software on either a Windows
VM or Windows computer. You can also use the KVM or Xen self-extracting
image to create Ixia Kernel VMs.
• Bare metal: In a bare metal deployment, you install IxVM RPM packages on
a bare metal Linux server, and the supporting software on a Windows com-
puter.
This section describes each method.
In this section:
• vSphere Deployment
• KVM Deployment
• XEN Deployment
• XEN Deployment
• Windows components
vSphere In an vSphere deployment, you use vSphere to create VMs based on the Ixia
Deployment kernel template file (.ova).
In the figure below, the following components are present:

• Virtualization server with VMware ESX(i): The virtualization server is the
physical machine that hosts the ESX(i) virtualization operating system.
• Windows VM: The Windows VM is a virtual Windows computer hosted on
the virtualization server, and functions as the IxVM chassis controller. It hosts
the following applications:
• IxServer, which manages traffic between Ixia applications and the virtual
Ixia ports.
• Discovery Server, which discovers virtual Ixia ports running on the virtual-
ization server, and adds them to the lists of test ports in Ixia testing applica-
tions.
• IxNetwork, IxExplorer, and IxLoad, the Ixia testing applications.
• Linux VMs: The Linux VMs are VMs hosted on the virtualization server that
are running one of the supported Linux kernels and the IxVM packages that
generate the test traffic. Each VM has two NICs: one for management traffic,
and one for test traffic.

IxVM
39 IxVM Deployment Models
• Virtual switches: The vSwitches are virtual equivalents of physical switches

and perform the same function, routing traffic to and from the virtual Ixia
ports. The virtual switches are created using vSphere.
• Windows computer: The Windows computer is used to access and control the
VMs on the ESX(i) host using vSphere.
KVM Deployment In a KVM deployment, the virtual Ixia ports are created on virtual machines
running under the KVM hypervisor on a KVM server. The figure below shows
the components used in a KVM deployment.

• KVM server: The KVM server is the physical machine that hosts the KVM
hypervisor.

IxVM

the KVM server, and functions as the IxVM chassis controller. It hosts the
following applications:
Ixia ports.
tions.
• IxNetwork and IxExplorer, the Ixia testing applications.
Alternatively, a physical computer can also be used as the IxVM control-
ler.
• Virtual switches: The virtual switches are virtual equivalents of physical
switches and perform the same function, routing traffic to and from the vir-
tual Ixia ports. The virtual switches are created using KVM.
• Management host: The management host is used to manage the VMs on the
KVM host using a KVM management utility.

IxVM
XEN Deployment In a XEN deployment, the virtual Ixia ports are created on virtual machines
running under the XEN hypervisor on a XEN server. The figure below shows the
components used in a XEN deployment.

• XEN server: The XEN server is the physical machine that hosts the XEN
hypervisor.
the XEN server, and functions as the IxVM chassis controller. It hosts the fol-
lowing applications:
Ixia ports.
tions.
• IxNetwork and IxExplorer, the Ixia testing applications.

IxVM
Alternatively, a physical computer can also be used as the IxVM control-

ler.
• Virtual switches: The virtual switches are virtual equivalents of physical
switches and perform the same function, routing traffic to and from the vir-
tual Ixia ports. The virtual switches are created using XEN.
• Management host: The management host is used to manage the VMs on the
XEN host using a XEN management utility.
Bare-metal Linux Although deploying IxVM as a series of VMs is the most typical scenario for
Deployment using IxVM, it can also hosted on a bare-metal Linux server. The figure below
shows the components used in a bare-metal deployment of IxVM.

• Linux server: The Linux server runs one of the Linux kernels supported by
IxVM, and the supporting IxVM packages that generate the test traffic.
• Windows computer: The Windows computer hosts the following applica-
tions:
Ixia ports.
tions.
• IxExplorer and IxNetwork, the Ixia applications used to configure and run
tests, and that use the virtual Ixia ports to generate traffic.
• Switch: The switch routes the test traffic to and from the SUT.

IxVM
Windows The Windows components required to manage and use IxVM virtual cards can be
components installed in any of the following places:
• On a Windows VM
If you have a vSphere, KVM or Xen environment, you can create a Windows
VM (or use an existing one) and then install the IxVM components on it.
• On a physical Windows computer
In vSphere, KVM or Xen deployments, you can also use a physical computer
as the IxVM controller. If you are deploying on bare metal, a physical com-
puter is the only option for the IxVM controller.
Note: You cannot install the IxVM component on an Ixia chassis.

IxVM
Installing IxVM Components on a Physical computer or Windows VM
To use a physical computer or Windows VM as the IxVM controller, install the

following applications on the computer or Windows VM, making sure to select
the options for IxVM support when you install them:
• IxOS
• Discovery Server
• Deployment Wizard
• IxExplorer
TCP/UDP Ports Required
The following ports are needed for communication between Windows VM and
Linux VMs:
TCP
• 998 betaftpd_shadow
• 999 inetd
• 1000 ixdiscoveryagent
• 6001 ixServiceManager
• 6665 InterfaceManager
• 9101 ixStatDaemon
• 9102 ixStatDaemon
• 9613 ixDodClient
• 9614 pcpuManagerar

IxVM
UDP
• 123 ntpd
Windows VM ports
Windows VM ports are as follows:

• TCP ports: 1000, 1080, 5285, 6001, 6005, 8021, 9101, 9102, 9613, 17668,
17669, 17670, 17672, 33000, 57843, 57845, 57846, 57847, 61248, 61260,
61272, 61274
• UDP ports: 1000, 65031

IxVM
Installing IxVM
Installing IxVM
The installation process for IxVM depends on the deployment type you are
using:
• vSphere: In a vSphere deployment, you can install IxVM by creating VMs in
vSphere and basing them on the Ixia kernel OVA template. The OVA tem-
plate includes all the supporting software required for IxVM pre-installed.
• KVM or Xen: In a KVM or Xen deployment, you use self-extracting disk
images to create VMs that have all the IxVM packages already installed, or
you use RPMs to install the IxVM packages on VMs that you have created
yourself.
• Bare-metal: In a bare-metal deployment, you use RPM to install the IxVM
packages on a bare-metal server that is running one of the supported Linux
distros.
Note: On Xen hypervisors, installing IxVM on a VM created without the self-

extracting script file is not supported.
The following sections describe each method:

• OVA-based Installation
• KVM Installation
• Bare-metal (RPM) Installation
OVA-based The sequence for deploying IxVM on vSphere is as follows:

Installation 1. Download and install VMware ESX(i) on your VMware server (if you have
not already done so).
2. If you intend to use a VM as the IxVM chassis controller, create a Windows
VM in VMware, and install IxServer and the supporting applications on it.
3. Download the Ixia kernel template (.ova) file, and use the template to create
the one or more Linux VMs to host the virtual Ixia ports
4. Configure Discovery Server.
The following sections describe each of these steps.
After you have completed the steps, you can begin using the virtual Ixia ports
with your Ixia testing application.
Downloading and Installing vSphere
If you have not already installed VMware's ESX(i), you must install it on your
server. ESX(i) is available free and has the same user interface as the enterprise
versions of vSphere and vCenter Server.

IxVM
39 Installing IxVM
Note: ESX(i) is a Type 1hypervisor -- a virtualization operating system. It is not a

virtualization application that you can run on top of another operating system. If
you install ESX(i), it replaces the existing operating system on your server
A video is available showing the ESX(i) installation process: http://

www.youtube.com/watch?v=3UjSd8rbJvQ (http://www.youtube.com/
watch?v=3UjSd8rbJvQ). Note the steps at the end of the video for configuring
the password and IP address of the server.
1. Access the VMware web site and register for a free account: https://
www.vmware.com/tryvmware/index.php?p=free-esxi&lp=1 (https://
www.vmware.com/tryvmware/index.php?p=free-esxi&lp=1)
2. Download the VMware ESX(i) ISO image, and then burn it to a CD-ROM.
Make sure that you save the ESX(i) license key.
3. Power on your server and enter the BIOS setup utility.
4. Enable all the virtualization features in the BIOS.
5. In the BIOS, make sure that the boot order shows the CD-ROM first and the
internal hard disk second.
6. Insert the CD-ROM into your server's CD-ROM drive, save the changes to
the BIOS and then reboot the server.
7. Install ESX(i) on your server.
8. On the computer that you will use to access the server, open a web browser
and enter the server's IP address in the URL field.
9. Install vSphere client on the computer.
Creating the Source and Destination Networks
Before you create and deploy the VMs, you should already have created the
virtual networks that they will use. To create the virtual networks, you use
vSphere client. You will need two networks:
On the Windows VM (virtual chassis):

• An access network that enables you to access the virtual chassis. This net-
work connects to your corporate LAN. The default network created for this
purpose in vSphere is named "VM Network".
• A card management network to act as "virtual backplane" that connects to the
IxVM cards.
Two networks are pre-configured on the Ixia kernel OVA:

• IxVM Management Network, the virtual backplane.
• IxVM Test Network 1, the path for test traffic to the DUT or SUT.
During the process of creating the VMs, you map the source networks configured
in the .ova template to the destination networks on your VMware server.

IxVM
Installing IxVM
To create the networks, use the following procedure:

1. Open vSphere client, and display the Inventory tab.
2. Click the Configuration tab.
3. In the Hardware pane, click Networking.
4. Click Add Networking.
The Add Networking wizard starts, and displays the Connection Type win-
dow.
5. Click Virtual Machine, then click Next.
The Network Access window displays
6. Click Create a Virtual Switch.
The Connection Settings window displays.
7. In the Network Label field type a name, then click Next.
8. Repeat for the additional vSwitches (networks).
Deploying the IxVM Appliances (OVAs)
The IxVM Ixia kernel is available as an Open Virtual Appliance (.ova) file,
which is a template for a virtual machine. The .ova template creates a VM with a
Linux kernel that has been modified by Ixia for greater performance in some
testing scenarios. To use the .ova file, you use vSphere client to create a VM, and
specify the .ova file as the template for the VM.
Note: Before you create and deploy the VMs, you must already have created
the virtual networks that they will use in vSphere. See Creating the Source and
Destination Networks on page 39-16.
To create a VM based on an IxVM OVA file:

1. Download the .ova file from the Ixia website. Store them in a location where
they can be accessed from the ESX(i) server.
2. From the vSphere client menubar, choose FILE | DEPLOY OVF TEM-
PLATE.
The Source window displays.
3. Choose DEPLOY FROM FILE:, then click BROWSE, and select the .ova
file. Click NEXT.
The OVF Template Details window displays.
4. Make a note of the Username and Password shown on the OVF Template
Details window. The default usernames and passwords are:
root/ixia123
Click NEXT.

IxVM
39 Installing IxVM
The End User License window displays.

5. Click ACCEPT to accept the license, then click NEXT.
The Name and Location window displays.
6. Enter a unique name for the VM, then click NEXT.
The Datastore window displays.
7. Select the data store where you want your VM files to be stored, then click
NEXT.
The Network Mapping window displays. On this window, you map the net-
works configured in the .ova template to the networks on your virtualization
server.
8. Map the template’s networks to your VMware networks, then click NEXT.
The Ready to Complete window displays, showing a summary of the deploy-
ment options you have selected.
9. Choose one:
• If you are installing using vSphere client with vCenter, the wizard displays
windows enabling you to select the IP address allocation method. Choose
the method you want to use.
• If you are installing using vSphere client without vCenter, the VM is auto-
matically created with IP address allocation set to DHCP. If you want to
use static IP addresses, you must use the VM's console interface to specify
the IP addresses of the VM after it boots. See Configuring static Addresses
(see "Configuring Static Addressing" on page 2).
Review the final deployment details, then click FINISH. Allow the VM sev-
eral minutes to deploy.
10. Boot the VM.
11. Repeat the deployment procedure for the remaining VMs that you want to
create.
Configuring Static Addressing
If you created an IxVM template using vSphere without vCenter, the VM is

automatically created with IP address allocation set to DHCP. If you want to use
static IP addresses, you must use the VM's console interface to specify the IP
addresses of the VM after it boots.
To configure a static address on a VM:

1. In vSphere client, select the VM that you want to configure.
2. Click the CONSOLE tab.
A console session for the VM starts, and prompts you to login.
3. Login to the VM with the user name and password configured on it when it
was created.

IxVM
Installing IxVM
Note: You can display the user name and password by clicking the Summary
tab, then select Annotations, and then click Edit. Scroll through the window untill
the user name and password displays.
4. Start the vi editor and load the IP address script for the eth0 interface by typ-
ing the following command:
vi /etc/sysconfig/network-scripts/ifcfg-eth0
5. Type I or press the INSERT key to switch to edit mode.
6. Change BOOTPROTO to static.
7. Add a new line that contains the following:
IPADDR=<ipaddress>
where <ipaddress> is the address you want to assign to VM's eth0 interface.
NETMASK=<mask>
where <mask> is the netmask to be applied to the IP address.
8. Close and save the file: Press ESC, then type: : W Q ! (colon, w(rite), q(uit),
exclamation point).
9. Repeat for the eth1 interface (edit the file ifcfg-eth1).
10. Issue the following commands to bring the interfaces up:
ifup eth0
ifup eth1
Configuring Discovery Server
Use the following procedure to configure Discovery Server.

1. Start Discovery Server using the following command:
START | ALL PROGRAMS | IXIA | IXIA DISCOVERY SERVER | IXIA
DISCOVERY SERVER
Discovery Server starts, and minimizes to the tray.
2. Double-click the DISCOVERY SERVER icon.
3. Click the BROADCAST DISCOVERY tab.
The Broadcast Addresses list contains the list of IP addresses configured in
the VM. For some installations, this may include the address of the IxVM
management port (the first LAN connection), and the second LAN connec-
tion. Discovery Server displays the IP addresses for all the network adapters
configured on the Windows VM so that you can select the networks that you
want to search for IxVM cards.
4. Select the check box for the address of the IxVM card management IP port
(typically, 10.0.0.x), and clear the check box for the second LAN connection.

IxVM
39 Installing IxVM
Note: If you restart Discovery Server, the check boxes are reset to their default
values.
Optimizing Performance
You may be able to improve performance by applying the following

optimizations:
Power Management
In the ESX(i) server BIOS, ensure that Power Management is set to High
Performance.
Hyperthreading
In vSphere, click the Configuration tab, then click Processors, and disable
hyperthreading. Reboot the ESX(i) server.
Figure 39-1. The Configuartion Tab
NIC Type
In vSphere, click the Hardware tab, and change the test NIC Interface types to
VMXNET3.

IxVM
Installing IxVM
Figure 39-2. The Hardware Tab
Visit VMware’s Networking Blog for more details on how to enable Jumbo
Frames: http://blogs.vmware.com/networking/

IxVM
39 KVM Installation
KVM Installation
For KVM deployments, Ixia supplies IxVM in two forms:
• as a script containing a self-extracting disk image (.img) that creates a new
VM running the Ixia kernel
To install using the script, follow the procedure below.
• as RPM packages that you can install on existing Linux VMs
To install using the RPMs, follow the same procedure as for a bare metal
deployment. For details see Bare-metal (RPM) Installation on page 39-74.
Before Installation
Before you install IxVM:

• Install and configure KVM/Qemu, if you have not already done so.
In KVM, create the bridges (virtual networks) for the VMs you will create.
You will need two bridges:
• one for the card management traffic
• one for the generated test traffic
Note: For details on the various switches the script accepts, run the script with
the help switch before you run it to install IxVM:
./VM_IxVM_QemuKVM-<version>.sh -help
Installing IxVM on KVM

1. The script requires root-level privileges to run. Login to the KVM host using
an account that has root privileges.
2. Copy the VM_IxVM_QemuKVM-<version>.sh script to the KVM host. If
you are copying using WinSCP, set the Transfer Settings to Binary mode .
3. Make the script file executable:
chmod +x VM_IxVM_QemuKVM-<version>.sh
4. Set your path to the location where you want to store the VM (or use -d to
specify a different path when you run the script).
5. Run the script.
./VM_IxVM_QemuKVM-<version>.sh
If you want to create the the VM in a different location, use the -d switch fol-
lowed by the path:
./VM_IxVM_QemuKVM-<version>.sh -d <path>
The script starts, and prompts you for a name for VM.
6. Enter a name for the VM, then press ENTER.

IxVM
KVM Installation
The script displays a list of the bridges and virtual networks on the KVM
host. You must choose two bridges or virtual networks:
• one for the card management traffic
• one for the generated test traffic
7. Type the name of the bridge or virtual network you want to use for the man-
agement traffic, then press ENTER.
8. Type the name of the bridge or virtual network you want to use for the test
traffic, then press ENTER.
The script unpacks the .img file and creates a VM in the current directory.
9. If you are using Virtual Machine Manager (VMM), restart it before you start
the new VM.
The password for the VM's root account is ixia123.
Note: In addition to the .img file, the script also creates an .xml file in
/etc/libvirt/qemu/
that describes the VM's hardware configuration.
If you delete the VM from VMM, only the .xml file is deleted; you must manually
delete the .img file

IxVM
39 KVM Tutorial
KVM Tutorial
Introduction KVM (Kernel-based Virtual Machine) is a full virtualization solution for Linux
that takes advantage of CPU based hardware acceleration such as Intel VT or
AMD-V. KVM itself exists as a kernel module and can be installed on a Linux
system that has the supported set of Intel/AMD processors.
This document will demonstrate one use case of virtualization by leveraging the
capabilities of the KVM Linux kernel extensions and open source virtualization
software such as Red Hat’s Virtual Machine Manager.
Other sources of http://www.linux-kvm.org

information
KVM Homepage.
http://libvirt.org
libvirt Homepage.
http://libvirt.org/docs.html
libvirt Documentation.
Before you begin Please make sure that you have followed the first part of this guide: “Preparing
Ixia Application Controller for KVM based IxVM” and ensure that you have
VNC remote connectivity to your server.
Hardware requirements
This document focuses on the Ixia Application controller (also known as

“AppServer”) and the time of writing, this is a single-processor Intel Xeon (quad
core), 24GB of DDR2 RAM, two integrated GbE LAN ports, and one slim DVD-
ROM drive.
Software requirements
• Windows 7 ISO or CD/DVD.
• IxOS 6.50 EA + IxVM Server component.
• IxNetwork 7.12 EA.

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KVM Tutorial
Time requirements
Start to finish, Windows 7 installation, IxOS and IxNetwork installation can take
from an hour to three hours (not including the time to download).
CentOS version requirements
At the time of writing this document, only CentOS 6.3 is fully supported for
IxVM – it is also important to note that performing an update (for i.e. `yum
update`) will upgrade the version of CentOS to an unsupported version
Note: Running IxVM on a CentoS 5.6 KVM should still work, but there are some
limitations that are caused by the version of this hypervisor. Ixia suggests you
use a CentOS 6.3 KVM.
-- please do not run such commands when working with Ixia IxVM software.
In addition, make sure you ignore popup messages such as the following!
Figure 39-3. The pop-up message
Topology Use case 1 – Back to back test
The sphere in the following topology represents all virtualized components that
are hosted by the Ixia application controller including the DHCP and NTP server.

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39 KVM Tutorial
Use case 2 – External connectivity
Building upon the previous use-case, this will focus on enabling port forwarding
on the host, which will allow non-virtualized components such as IxTCL wish
shell, IxNetwork and the Microsoft Remote Desktop client to remotely connect
to the virtualized Windows VM without consuming CPU or memory resources
on the host – this would considerably benefit customers that are conservative
regarding host CPU/memory consumption by the Windows VM.

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Use case 1 – Back Prerequisites

to back test
Ensure that you have the following:
• License for IxVM/IxNetwork.
• Ixia web login to access Ixia’s Downloads & Updates.
Introduction to libvirt daemon
Ensure that the libvirtd is running:[root@localhost ~]# service libvirtd status
libvirtd (pid xxxx) is running…
If for some reason, the service/daemon is not running, manually start of the
service:
[root@localhost ~]# service libvirtd start
Starting libvirtd daemon:[OK]

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39 KVM Tutorial
Establish the QEMU connection
Launch VMM (Virtual Machine Manager) from Applications -> Systems Tools -
> Virtual Machine Manager.
Figure 39-4. Virtual Machine Manager screen
Establish a connection to the QEMU/KVM hypervisor via File -> Add

Connection -> Connect:
Figure 39-5. The Add Connection screen
Note: Make sure the hypervisor is set to QEMU and not XEN. The default
hypervisor for the GUI is XEN.

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KVM Tutorial
Figure 39-6. The Virtual Machine Manager screen
Create Ethernet Bridge for Management network
On the main dialog of Virtual Machine Manager, click on the connection to

localhost (ID: qemu) to highlight it and then navigate to: Edit -> Host Details ->
Virtual Networks. Click on the default network to highlight it and ensure that it is
Active and enabled for “Autostart on Boot”:
VMM has utilized the Linux brctl command to setup and maintain an Ethernet
bridge. The name of the device/network from libvirt’s perspective is default and
the Linux Ethernet bridge identifier is virbr0; to determine the status of this
bridge you can simply run: `ifconfig virbr0` from the shell. The purpose of the
bridge is to simply connect different multiple Ethernet capable virtual devices
together just as a real layer-2 switch would operate. In the context of this
particular use case, the bridge will serve as the management network that will
interconnect the Windows VM and two IxVM ports.
VMM will also provide the DHCP start and end addresses as parameters to a
process called dnsmasq, which is a lightweight DHCP server (among other
capabilities) to provide DHCP addresses to all connected hosts on the default
bridge, and for this use case this will translate to the Windows VM and the eth0
interface of the two IxVM ports.
For more information on libvirt networking:

• http://wiki.libvirt.org/page/Networking
• http://wiki.libvirt.org/page/Libvirtd_and_dnsmasq

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39 KVM Tutorial
Create Ethernet bridge for test ports
To establish a dedicated and isolated bridge between the IxVM ports, create a
new virtual network (click on the button with the + icon):
Figure 39-7. Create a new virtual network screen
Network Name: ixvm_bridge
Network: 0.0.0.0/24
DHCP Start/End range: 0.0.0.0
Physical network: Isolated virtual network
Ethernet Bridge: ixvm_bridge should now be running and DHCP (through

dnsmasq) should NOT be providing out any addresses since the range is null:

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Figure 39-8. Host Details screen
Now, close VMM and create a new shell using Terminal (from Applications ->
Accessories).
Note: This step assumes you have a separate file system mounted under /
nobackup as defined in the first document. If you need to mount this directory,
you must do so via `mkdir /nobackup` && `mount /dev/sda2 /nobackup`.
Create the following directories (if they do not already exist):
[root@localhost /]# cd /nobackup

[root@localhost nobackup]# mkdir libvirt
[root@localhost nobackup]# cd libvirt/
[root@localhost libvirt]# mkdir images
[root@localhost libvirt]# cd images
[root@localhost images]# pwd
/nobackup/libvirt/images
Download the latest KVM IxVM image into the above directory and ensure
executable permissions for root:
[root@localhost images]# chmod u+x VM_IxVM_QemuKVM-
1.0.0.68.sh
Instantiate IxVMPort1
Run the script to create instance for IxVM_Port1:
[root@localhost images]# ./VM_IxVM_QemuKVM-1.0.0.68.sh
Host System: CentOS

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39 KVM Tutorial
Creating virtual machine

Enter virtual machine(domain) name: IxVM_Port1
Setting up network configuration
NETWORKS_LIST
default
ixvm_bridge
Enter management network name: default
Enter test network name: ixvm_bridge
Stopping libvirtd daemon: [ OK ]
Starting libvirtd daemon: [ OK ]
VIRTUAL MACHINE INFO
Machine name: IxVM_Port1
Management NIC: default
Test NIC: ixvm_bridge
########################################################
# [warn]: libvirt daemon has just been restarted in order
that #
# new configuration to take effect; note that it may be #
# needed to restart Virtual Machine Manager also #
########################################################
Note: The script has essentially created a new QEMU-KVM instance and
connected the new VM’s eth0 virtual interface to the default network and eth1
to the ixvm_bridge (created earlier). When the IxVM_Port1 starts, it will
attempt to retrieve an IP address from the DHCP server through eth0 interface.
Instantiate IxVMPort2
Run the script again for IxVM_Port2:
[root@localhost images]# ./VM_IxVM_QemuKVM-1.0.0.68.sh
Host System: CentOS
NETWORKS_LIST
default
ixvm_bridge
Enter management network name: default

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KVM Tutorial

Management NIC: default
########################################################
that #
########################################################
Note: This second VM is connected to the same default network and

ixvm_bridge. The two VMs will be able to talk to each other and to the
Windows VM via the default network; moreover, the two VMs will have a
private and isolated connection to each other via the eth1 interfaces and
ixvm_bridge.
Create and instantiate IxVM management VM
Go back to the VMM GUI, highlight the “qemu” connection and click on “New”
to create a new VM instance:
Figure 39-9. The VM instance screen
Note: The VM status for both instances is in the Shutoff state and while they
are in this state they will not consume any host CPU cycles as it will need all
available processing power to complete the following task of instantiating a
Windows VM as fast as possible.
Name: IxVM

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39 KVM Tutorial
Virtualization method: Fully virtualized (CPU architecture: x86_x64)
Hypervisor: KVM
Installation method: Local installation media.
OS Type:Windows
OS Variant:Microsoft Windows XP (x86_64)
Installation media:<Select ISO or CD-ROM>
Storage:File (disk image)
Location:/nobackup/libvirt/images/IxVM.img
Size:60000 MB
Allocate:Uncheck (this option will allocate disk space on the fly as needed).
Network:Virtual Network -> Network: default.
Memory
Max memory:4000 MB
Startup mem.:1024 MB
Virtual CPUs:2
Click on “Finish” in the last dialog to create and launch the VM.
Install Windows 7
Once the VM has been successfully instantiated, follow and select the default
options of installing Windows 7:
Pre-requisites:
• Ensure that the Windows 7 installation key is available
• Ensure that you have the right drivers available before you start the installa-
tion.
Installation Steps:
1. First, you need to choose your language and keyboard settings.

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KVM Tutorial
Figure 39-10.Windows 7 Language and Keyboard
2. The Install now window appears. Click Install now to proceed.

3. The License Agreement window appears. Select the I accept the license terms
check box and click OK.
4. The Installation Type window appears where you need to select the type of
installation you want to do. Select Custom (advanced) for a fresh install of
Windows 7.
Figure 39-11. Windows 7 Installation Type

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39 KVM Tutorial
5. Next you need to choose the location in your disk where you want to install
Windows 7.
Figure 39-12.Windows 7 Installation Location
6. The installation starts and after sometime you will be asked to provide your
user name and computer name.
You can provide the user name as IxVM User.
Figure 39-13.Windows 7 User name
7. Next you need to provide a password for your account.

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Figure 39-14.Windows 7 Password
Note: Leaving the password blank is optional but will provide an advantage as
it will allow the Windows VM to login automatically without a blocking login
prompt.
8. You then need to configure the updates to Ask me later. Next configure your
time zone and location.
Windows 7 is now successfully installed on your virtual machine.
Customize Windows 7
To improve security, Windows 7 has the user account control option that is set by
default to ask permission for specific operations (ex: running different executable
files). To run IxVM properly, this option has to be disabled:
To change the settings, change the view in Control Panel to "Small icons" and go
to "User Accounts".
1. Click Start and then select Control Panel option.
2. Click User Accounts option. The user control panel screen shows as follows:

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39 KVM Tutorial
Figure 39-15.The user control panel screen
Go to "Change User Account Control Settings" and drag the dial down to "Never
notify". The screen shows the options as follows:
You need to restart Windows for the changes to take place. Please do this before
continuing with the rest of the changes.

IxVM
KVM Tutorial
By default, Windows will display alerts relating to the status of the Firewall,
Windows Automatic Updates and Virus Protection. Since none of these services
are required, disable the alerts:
2. Click Notification Area icons.
Now change the Action center behavior to "Hide icon and notifications" and
press OK.

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39 KVM Tutorial
Ensure the Windows Firewall is disabled (since it will interfere with IxVM
management traffic):
1. Click Start and then select Windows Firewall option.
2. Turn Windows Firewall on or off.
Figure 39-19.The Customize settings of each network type screen
The "Sleep" and "Turn off display" options need to be disabled also:

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2. Click Power options and then select Change plan settings option.
Figure 39-20.The Change plan settings screen
In the same window as above, go to "Change advanced power settings" and

under Hard Disk option Turn off hard disk after Setting enter 0 (zero) to set to
Never. When done, click OK and Save changes to finish with setting up the
power options.
Figure 39-21.The Power Options screen

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39 KVM Tutorial
Next, disable the automatic updates:

2. In the windows updates and in the left side of the screen click on the Change
settings.
3. Set the Important updates option to Never check for updates.
Figure 39-22.The Never check for updates screen
In case you intend to use Deployment Wizard to install or upgrade a virtual

chassis on this Windows machine you need to disable Simple file sharing or
Sharing wizard:
1. In the Windows Explorer options click Tools.
2. Click View tab under Folder Options.
3. Scroll down to the bottom where you will find "Use Sharing Wizard".
4. Clear the option.

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Figure 39-23.The View Tab screen
Finally to login remotely to this Windows 7 machine, you need to enable the
remote desktop option:
1. Click start and right click on My Computer.
2. In the left side of the Window select Remote settings.
3. Select the second option from the radio button options as shown in the below
screen shot:

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Figure 39-24.The Remote Tab screen

IxVM
IxVM Live CD Installation

The IxVM liveCD image can be installed in a virtual machine created on any of
the supported Hypervisor / Host OS on page 39-3.
Here is a step by step guide to deploy a liveCD image on a virtual machine, using
VMware 5.0:
1. Copy the .iso file for the live CD to the hypervisor datastore.
2. On the File menu, click New, and then click Virtual Machine (Ctrl+N hot-
key). The Configuration window appears as shown below.

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39 IxVM Live CD Installation
3. Select the type of configuration you want for the virtual machine, and then
click Next. The Name and Location window appears.
4. Type the name of the new virtual machine, and then click Next. The Storage
window appears.

IxVM
5. Select the destination storage for the virtual machine files, and then click
Next. The Guest Operating System window appears.
6. Select the Red Hat Enterprise Linux 6 (32-bit) guest operating system, and
then click Next. The Network window appears.

IxVM
7. Specify the network connections that will be used with the virtual machine,
and then click Next. The Create a Disk window appears.
8. Create the disk for the virtual machine by specifying the disk size and provi-
sioning policy, and then click Next. The Ready to Complete window
appears.

IxVM
9. Click Continue. The Virtual Machine Properties window appears.
Note: Select the Edit the virtual machine settings before completion check
box before clicking Continue.
10. In the Virtual Machine Propeties window, select CPUs from the list of
Hardware on the left. Add 2 CPU cores and 2 GB of memory to the VM.

IxVM
11. Next select New CD/DVD and define the following properties:
• Under Device Status, select the Connect at power on check box.
• Under Device Type, click Datastore ISO File.
• Click Browse, and then select the live CD .iso file from the local datastore.
12. Click Finish and localize the VM in the hypervisor inventory.

13. Power on the virtual machine. The following boot screen appears.

IxVM
14. After the booting is done, the setup utility tool appears as shown below.
15. Navigate to the Quit button by clicking Tab. The CentOS login screen
appears, where you have to log in with the root user (no password required).
Note:
• The LiveCD can only be used in the supported virtualized environments
(VMware, KVM, ESX).
• The LiveCD cannot be used on physical machines due to the custom Ixia
kernel.
• The LiveCD can be used only if there is at most one hard disk configured on
the virtual machine (it also works with no hard disk configured).

IxVM
39 Install IxOS and IxNetwork
Install IxOS and IxNetwork

From the Windows VM instance, download and install IxOS 6.60 EA and
IxNetwork 7.20 EA Patch1 (respectively). You will be asked to reboot after the
IxOS installation and once more after the IxNetwork 7.20 EA Patch1 installation.
In addition, please ensure that that the appropriate IxVM/IxNetwork licenses are
also installed.
Note: When installing IxOS, make sure Client, IxVMServer and Tcl Server are
selected to be installed. In the “Custom setup” dialog, you will be given a
choice over Demo Server or IxVM Server. Select IxVM Server.
Install and configure NTP server on the host
For this use case, we will be using the Linux host as the NTP server. To do this,
the NTP package should be installed:
[root@localhost ~]# yum install ntp
[root@localhost ~]# service ntpd start
Starting ntpd:[ OK ]
To allow the host to serve NTP requests, modify /etc/ntp.conf and append the
following line:
restrict 192.168.122.0 mask 255.255.255.0 nomodify notrap
Note: 192.168.122/24 is the default network for libvirt and since we have used
the default network for the management bridge, the entry for /etc/ntp.conf
should match.
Allow the NTP service to run at boot-time and manually restart the service for
the new modifications to take affect:
[root@localhost ~]# chkconfig ntpd on

[root@localhost ~]# service ntpd restart
Shutting down ntpd:[ OK ]
Starting ntpd:[ OK ]
Configuring DHCP Server
The DHCP server is required for a faster way to deploy IxVM Cards and attach
them to Virtual Chassis in an environment that is isolated from any automatic IP
address policy. This server provides IP addresses based on default configuration,

IxVM
and also has an interface that can be used as a tool to customize the DHCP
Server.
IxVM server needs to include DHCP server for accelerating card deployment in
private management networks.
Note: Open DHCP Server used by IxVM server only listens on Static
Interfaces that means the IP address is fixed and not obtained from another
DHCP Server. Any dynamic interfaces specified are ignored.
You can configure the DHCP server through the DHCP Configuration dialog box
that can be found in IxServer DHCP Configuration under under Tools. This
option is unavailable if you have not installed the IxVM component for IxServer.
This command starts a standalone application that configures the DHCP server.
The following image shows the IxDHCPConfig dialog box:
Figure 39-25.The IxDHCPConfig dialog box
• Network adapter: This section provides details of all available interfaces on

the system. Under Logging options, if you click All, server listens to all avail-
able interfaces. An interface is considered available if it has a static IP that
means the IP address is fixed and not obtained from another DHCP Server.
Any dynamic interfaces are ignored.

IxVM
• Enable DHCP Server: This section starts or stops the DHCP service.
• Adapter Name: Displays the name of the selected adapter.
• Adapter IP address and Network Mask: When you choose a network
adapter, the IP and Mask is automatically populated under Adapter IP address
and Network mask.
• Current configuration: This represents a short description of more impor-
tant configured information on DHCP Server.
• Network Adapter IP: This is an interface on which the DHCP Server lis-
tens after IP request.
• Dynamic address allocation: This shows all IP ranges that can be used for
dynamic allocation.
• Static address allocation: This shows all pair MAC :: IP configured for
static IP allocation.
General Tab:
• Viewing lease status: This option shows the used IPs offered by DHCP
Server. You can configure it on any interface (IP must be valid) to check the
IP allocation status on server by using an HTTP request on this IP:Port con-
figuration.
• Check lease status: This link shows the lease status that is set up by IP and
Port in the default browser.
• Loggings options: This option shows the levels of logging offered by DHCP
Server. By default, it is set to Normal.
Dynamic Address Allocation tab:
The following image shows the Dynamic Address Allocation tab:

IxVM
Figure 39-26.The Dynamic Address Allocation tab
• Dynamic Address allocation: This tab has a list of dynamic assigned IPs.
Each line represent one range, and each range can have its Mask, Gateway,
and Expire Time configured individually.
• Auto range: If no ranges exist in the configuration, the application adds one
auto generated range when you select the interface, on which the DHCP
Server listens. This auto range is generated from selected interface IP and
MAC, and the Gateway is set to the current interface, the Expire time is set
to 3600 seconds, and the Mask value is taken from the selected interface.
• Default range: If you add a new interface, this is autocompleated with a
default range. The default range is marked as invalid, and turned as valid
when you enter valid data.
• Range Start –Range End: The range start checks each item separately to
assure that it is a valid IP. If you change an item to invalid in a valid range
then that particular item change its background to red and the range becomes
invalid. If validation of IP is passed then, start IP must be smaller than end IP,
and if it does not pass then both items change their its background to red.
• Mask and Gateway: If valid IP address is not showing in these columns then
background changed to red.
• Status: The status shows current status of a range, and has the following val-
ues:
• Auto: The range is automatically added and is considered as a valid range
• Invalid: This range is not valid and is not in use.
• Valid: This specifies a valid range and is included in the configuration file.

IxVM
Static Address Allocation tab:
The following image shows the Static Address Allocation tab:
Figure 39-27.The Static Address Allocation tab
• Static Address allocation: This field shows the list of mandatory pair
options MAC and IP. This can be completed with other options as Host
Name, Domain Server and Gateway. Each line represents one MAC:IP
associations and they must be unique as Host Name.
• Default values: For static host default values are just MAC and IP these are
also mandatory fields.
Advanced Tab:
In its default state this tab is blank and needs to be configured with care as the
changes here have a global effect. More detailed information on all available
commands refer to List of DHCP Options.
The following image shows the Advanced tab:

IxVM
Figure 39-28.The Advanced tab
DHCP Server customization in Deployment Wizard
Deployment Wizard shows DHCP Server customization on both Install and

Upgrade flows.
The available options are to Enable or Disable DHCP Server on IxServer.
Deployment Wizard shows the same DHCP Server properties as in IxServer -

Dynamic Address Allocation tab.
Deployment Wizard provides the following options:

• The list with Network Adapters properties from the host machine.
• Support for updating IxDHCPServer.ini file with properties received from
Deployment Wizard.
The following image shows the DHCP server options dialog box under IxVM
Deployment wizard:

IxVM
Figure 39-29.The DHCP server option
IxOS Topology Transfer
The IxServer.ixs file contains all the information about card and port map,
chassis type, card types, stream configurations, and port properties. Using this
feature, the IxServer.ixs file gets copied from an older IxOS installation folder to
the newly installed IxOS folder. You can copy this file by using various methods
as follows:
• Use Deployment Wizard to select the required topology from the available
IxOS versions to transfer
• Use the IxOSTransferTopology importer application that is automatically run
at the end of any new IxOS installation to:
• Copy virtual chassis configuration from the latest version
• Copy virtual chassis configuration from the last run version
• Copy virtual chassis configuration from a specific IxOS version
• Copy virtual chassis configuration from a manually selected folder
Use Deployment Wizard to select the required topology from the

available IxOS versions to transfer
This option is available when using Deployment Wizard to upgrade an already

existing chassis.
In the Install Files page under Windows Virtual Controller, all the IxOS
versions that are detected on the chassis are shown in the right side pane.
You can select any of the available versions to have its IxServer.ixs file copied to
the installation folder of the new IxOS version.
Note: All the available versions are shown, which include the uninstalled
versions as well. If a version does not have the .ixs file available, it does not
appear in the pane.

IxVM
Use the IxOSTransferTopology importer application that is

automatically run at the end of any new IxOS installation
• Copy virtual chassis configuration from the latest version
In this option, the topology configuration file is copied from the latest installed
IxOS version. All installed IxOS versions are sorted and the latest version is
picked up.
Note: If the application cannot find the latest installed version, this option is
unavailable.
• Copy virtual chassis configuration from the last run version
In this option, the topology configuration file is copied from the most recently
run IxOS version. The latest version is taken from the registry.
Note: If the application cannot find the last run version or the last run version
does not have a valid .ixs file, this option is unavailable.
• Copy virtual chassis configuration from a specific IxOS version
When you select this option, the Select version page appears. This page contains
all the available versions, from which you can select one version (only the valid
versions appear).
Click Next again. The configuration file is imported from the selected version.
After the import configuration is done, the Finish page appears.
• Copy virtual chassis configuration from a manually selected folder
You need to manually identify the source folder, from where you want to copy
the file. This can be a backup folder for older IxOS versions, but you need to
have only one .ixs file in each sub-folder.
Select the folder from where the topology needs to be copied. You can copy the
topology either from installed or uninstalled versions that have a valid .ixs
configuration file.
• Clean install
If you select this option, the installer skips the topology transfer step. No
topology file is transferred and a new empty topology file is created at the first
IxServer start.
Note: If you want to manually run the IxOSTransferTopology tool between

various IxOS installations, you can find it at the following location:
C:\Program Files\Ixia\IxAdmin\bin\ IxOSTransferTopology.exe

IxVM
Instantiate IxVM test ports
Now that the Windows VM has been successfully established, it’s time to bring
up the IxVM ports. In the Virtual Machine Manager main GUI, right click on
IxVM_Port1 and click on Run (do the same for IxVM_Port2). This will take
about 2-5 minutes for the ports to boot up, initialize and obtain an IP address
from DHCP.
Figure 39-30.The VM Manager screen
Double-click on IxVM_Port1 (for console); login as root and make a note of the
IP address for eth0 (do the same for IxVM_Port2):
Figure 39-31.The console window
Note: At the time of writing, the password for root is ixia123.
Go back into VMM, double-click on the Windows VM and navigate to IxServer

-> Tools -> Options. Once you are in the IxServer Options menu, set the NTP
Master Server to 192.168.122.1 (the host):

IxVM
Figure 39-32.The IxServer screen
For the changes to take affect; restart IxServer, launch IxExplorer (by connecting
to the localhost). Stop the firewall:
[root@localhost ~]# /etc/init.d/iptables stop
Flushing firewall rules: [ OK ]
Setting chains to policy ACCEPT: filter [ OK ]
Unloading iptables modules: [ OK ]
[root@localhost ~]#
Right click on the chassis (should be in a green state) and click on “Add Ports to
Chassis”:
Figure 39-33.The screen showing Add Ports to Chassis option
The initial virtual ports dialog contains a default IxVM card/port; delete this by
highlighting it and clicking on the following button:

IxVM
Figure 39-34.The Chassis properties screen
Then add your new cards, apply and OK:
Figure 39-35.The Chassis properties screen showing the ass new card option
A successful IxVM connection should appear as the following:
Figure 39-36.The successful IxVM connection screen
Launch IxNetwork 7.0, use the localhost as the chassis, and add both IxVM
ports.

IxVM
Figure 39-37.The Port Selection screen
Create a back-to-back configuration by adding IPv4/IPv6 protocol interfaces on

each port and send some test traffic through at low-rates (for e.g. 100 pps) to
verify traffic:
Figure 39-38.The data plane port statistics screen
To look at the raw counters (vnet2 maps to -> IxVM_Port1:eth1 and vnet4 ->
IxVM_Port2:et1),
[root@localhost ~]# ifconfig vnet2
vnet2 Link encap:Ethernet HWaddr FE:16:3E:58:F0:42
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1

IxVM
RX packets:1561980 errors:0 dropped:0 overruns:0 frame:0

TX packets:1558030 errors:0 dropped:0 overruns:635040
carrier:0
collisions:0 txqueuelen:500
RX bytes:93718728 (89.3 MiB) TX bytes:92541680 (88.2
MiB)
[root@localhost ~]# ifconfig vnet4
vnet4 Link encap:Ethernet HWaddr FE:16:3E:58:74:0E
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:1882045 errors:0 dropped:0 overruns:0 frame:0
TX packets:1352794 errors:0 dropped:0 overruns:513842
carrier:0
collisions:0 txqueuelen:500
RX bytes:112922556 (107.6 MiB) TX bytes:80227696 (76.5
MiB)
[root@localhost ~]#
Use case 2 –
External
connectivity Prerequisites
Ensure that you have the following:

• Use-case 1 successfully working and IxVM ports established (back-to-
back).
• IxNetwork client installed on your Windows laptop (or an external AppS-
erver).
Introduction to xinet.d
In the open source Linux world, xinetd, the eXtended InterNET Daemon is a
process-daemon that provides services such as access control, logging, cron
services, and port forwarding. Since this service is a fast, secure and efficient
means of forwarding traffic from the Windows VM to the external client, xinetd
will suffice.
Discover the Windows VM IP
From the VMM GUI, navigate to the Windows VM console, enter the command
prompt (Start -> Run -> cmd) and make a note of the IPv4 address that it is
assigned (in the following case, the address is 192.168.122.149):

IxVM
Figure 39-39.The command prompt window
Enable remote desktop for IxVM User
Goto System Properties (from Start -> Run -> right click on “My Computer”),
navigate to the “Remote” tab and enable “Allow users to connect remotely to this
computer”.
Figure 39-40.The Remote Tab screen
Click on “Select Remote Users…” and add IxVM User:

IxVM
Figure 39-41.The Remote Desktop Users screen
Install xinetd on the host

[root@localhost init.d]# yum install xinetd
…
Installed:
xinetd.x86_64 2:2.3.14-13.el5
Configure common Ixia TCP ports as xinetd services
On the host, edit the /etc/services file and at the end of file (under “# Local
services”) add the following three entries:
ixostcl4555/tcp# IxOS TCL server.
ixnetclient6809/tcp# IxNetwork server.
ixnettcl8009/tcp# IxNetwork TCL server.
Create port-forwarding definition file for xinetd
Create a file called ixia in the /etc/xinetd.d directory with the following contents
(making a note of 192.168.122.149 as the destination for all services):
service ixostcl
{ flags = REUSE
socket_type = stream
wait = no
user = root
server = /usr/bin/nc
server_args = 192.168.122.149 4555
log_on_failure += USERID
}
service ixnetclient
{
flags = REUSE

IxVM
wait = no
user = root
server_args = 192.168.122.149 6809
}
service ixnettcl
{
flags = REUSE
wait = no
user = root
server_args = 192.168.122.149 8009
}
service ms-wbt-server
{
flags = REUSE
wait = no
user = root
server_args = 192.168.122.149 3389
}
Save and exit the editor, ensure executable permissions for the ixia file, allow
xinetd to be automatically restarted on boot-up and manually start the xinet.d
service:
[root@localhost init.d]# chmod +x ixia
[root@localhost init.d]# chkconfig xinetd on
[root@localhost init.d]# service xinetd start
Starting xinetd: [ OK ]
Test Microsoft Remote Desktop connection
From your laptop client, connect to your server, for example:

IxVM
Figure 39-42.Remote Desktop connection screen
Test IxNetwork TCL server
From your laptop client, connect to your server, for example:

IxVM
Xen Server Hypervisor Support

The Xen Server installation is very similar to the KVM one.
Hardware This document focuses on the Ixia Application controller (also known as
requirements “AppServer”) and the time of writing, this is a single-processor Intel Xeon (quad
core), 24GB of DDR2 RAM, two integrated GbE LAN ports, and one slim
VDROM drive.
After installing CentOS 5.6 x64 on the physical machine, install the xen kernel
and depending packages (yum install xen virt-manager kernel-xen) and set xend
to start at boot (chkconfig xend on ). After this, reboo the machine. To check that
the host has booted into the xen kernel, use the command „uname -a | grep xen”.
If the command returns an output, then the Xen hypervisor can be used.
Xen already provides a bridge that can be used for the management interface
(xenbr) and by connecting the virtual machines to this bridge, you should have
access to your local management network and DHCP server.
Create an IxVM Run the Xen script to create a virtual machine with all the IxVM components
machine installed already:
[root@localhost images]# ./VM_IxVM_XEN-2.0.0.228.sh
Host System: CentOS
NETWORKS_LIST
xenbr0
default
ixvm_bridge
Enter management network name: xenbr0
Management NIC: xenbr0

IxVM
39 Xen Server Hypervisor Support
########################################################
that #
########################################################
Note: Before powering on the virtual machine, make sure that SELinux is not
enabled on the host operating system. Edit the /etc/selinux/conf file and check
that the SELINUX= option is set to „disabled”. Reboot the host machine after
this change.
Create and Go back to the VMM GUI, highlight the qemu connection and click on “New” to
instantiate IxVM create a new VM instance:
management VM Figure 39-44.The VM instance screen
Note: The VM status for both instances is in the Shutoff state and while they
are in this state they will not consume any host CPU cycles as it will need all
available processing power to complete the following task of instantiating a
Windows VM as fast as possible.
Name: IxVM
Virtualization method: Fully virtualized (CPU architecture: x86_x64)
Hypervisor: KVM
Installation method: Local installation media.
OS Type:Windows
OS Variant:Microsoft Windows XP (x86_64)
Installation media:<Select ISO or CD-ROM>
Storage:File (disk image)

IxVM
Location:/nobackup/libvirt/images/IxVM.img
Size:60000 MB
Allocate:Uncheck (this option will allocate disk space on the fly as needed).
Network:Virtual Network -> Network: default.
Memory
Max memory:4000 MB
Startup mem.:1024 MB
Virtual CPUs:2
Click on “Finish” in the last dialog to create and launch the VM.
****For easy deployment of large setups on the open source Xen Server,
Discovery Server, and Chassis Builder, the Deployment Wizard includes support
for the Xen Hypervisor.
Discovery Server supports discovering Virtual Load Modules from XenServer by

using the following option:
• Manual Discovery
• New plugin for KVM and Xen discovery
Note: For the appliances to be discovered by using the Xen and KVM
discovery plugin, the virtual machines need to be created by using the Ixia self-
extracting file for the respective hypervisors.
Chassis Builder supports managing appliances from Xen Server when rebuilding
the chassis topology. It also offers support for restarting the Virtual Load
Modules created on a Xen Server.
Deployment Wizard supports deploying or updating Virtual Load Modules on

Xen Server. It has the following functionalities:
• Connects to Xen Hypervisor
• Retrieves datastores
• Retrieves vBridges
• Adds multiple interfaces
• Deploys Virtual Load Modules by using a .sh script
• Upgrades Virtual Load Modules that run on Xen Hypervisors
Xen support in When machines are discovered with discovery server and shown in chassis
Chassis Builder builder, the new type Xen is shown on the type column as shown in the following
image:

IxVM
39 Xen Server Hypervisor Support
Figure 39-45.The Type column showing the Xen details
In addition, when a new Xen virtual machine is added in the chassis topology, the
type of the VM can be seen in the following VM information:
Figure 39-46.The chassis topology details
We can also restart the Xen virtual machine in a similar way as Qemu, KVM, and
VmWare types of machine are restarted.
Right-click the machine name, and then click Reboot from the shortcut menu.
The following image shows the Reboot option:
Figure 39-47.The Reboot option

IxVM
Set the credentials for the host of the virtual machine, as shown in the following
image:
Figure 39-48.The Set Credentials window
The Restart process gets started.

IxVM
39 Bare-metal (RPM) Installation
Bare-metal (RPM) Installation

The sequence for a bare-metal installation of IxVM with RPMs is as follows:
1. Download one of the supported Linux OSes, and install it on your bare metal
server.
2. Download the IxVM RPMs, and install them on the bare metal server.
3. Install IxServer, Discovery Server, and IxAdmin on a Windows computer.
The following sections describe each of these steps.
After you have completed the steps, you can begin using the virtual Ixia ports
with your Ixia testing application.
Installing Linux Download one of the supported Linux distributions, and install it on your bare
metal server. See Requirements (see "Requirements" on page 2) or the release
notes for the list of supported Linux distributions.
For whichever distribution you choose, you must use the default (unpatched)
kernel.
Installing IxVM For a bare-metal Linux deployment, you install IxServer, IxExplorer, IxNetwork,
Server, IxExplorer, Discovery Server, and Deployment Wizard on a 32-bit Windows 7 computer that
and IxNetwork can access the bare-metal server.
• IxServer and IxExplorer are packaged with IxOS and are offered as options
during IxOS installation.
• IxNetwork, Discovery Server, and IxAdmin have their own installers, and
you install them as you would if you were going to use them with a physical
Ixia chassis.
All components can be downloaded from Ixia's website.
To install IxVM Server, IxExplorer, IxNetwork, Discovery Server, and IxAdmin:

1. Download the IxVM IxOS installer, and install IxOS on the Windows com-
puter. Make sure that you select the following two components:
• IxServer
• Client
2. Download the IxNetwork installer, and install IxNetwork on the Windows
computer. Select all the components, including the one marked IxVM Server
(an IxNetwork-specific component required for IxVM, not to be confused
with the IxOS IxVM Server component).
3. Download and install Ixia Discovery Server on the Windows computer.
4. Download and install IxAdmin Client on the Windows computer.

IxVM
Bare-metal (RPM) Installation
Installing the IxVM Three IxVM components must be installed on the bare metal server:
RPM Packages • IxOS-VM
• IxNetwork-VM
• IxAdminAgent-VM
All three components are supplied as RPM packages compiled for the supported
Linux distributions.
To install the IxVM RPM packages:

1. Log on to the bare-metal server under an account with admin privileges.
2. Download the IxVM RPM packages appropriate for the Linux distribution
installed on the bare metal server.
3. Type the following to install the IxOS-VM package:
rpm –i <ixvm>.rpm
where <ixvm> is the name of the IxOS-VM RPM package.
4. Type the following to install the IxNetwork-VM package:
rpm –i <ixnetwork>.rpm
where <ixnetwork> is the name of the IxNetwork-VM RPM package.
5. Type the following to install the IxAdminAgent-VM package:
rpm –i <ixadminagent>.rpm
where <ixadminagent> is the name of the IxAdminAgent-VM RPM package.
6. Start the software agent using either of the following methods:
• Reboot the machine
• Enter: /etc/init.d/ixvm start
7. Enter ps -e to verify that bin/InterfaceManager is running.
8. After installation, if you need to find the build numbers of the RPMs that are
installed, you can use the following commands:
• IxOS-VM: rpm –qa ixvm
• IxNetwork-VM: rpm –qa ixnetwork_ixvm
• IxAdminAgent-VM: rpm –qa ixadminagent
Note: The Ixia Kernel rpm install is only for advanced users and should not be
used in Bare-Metal scenarios.

IxVM
39 Configuring NTP
Configuring NTP
If you are using IxVM ports from different instances of IxVM Server, or you are
using a combination of IxVM ports and Ixia hardware ports, you must configure
a common NTP time source so that traffic can be synchronized among the ports.
The NTP time source must be configured in IxVM server (for IxVM ports) and in
IxOS server (for hardware ports).
To configure an NTP time source:

1. Open IxVM Server or IxServer.
2. On the menu bar, click TOOLS| OPTIONS | DIALOG.
3. In the NTP MASTER SERVER field, specify the NTP server.
4. Click OK.
Figure 39-49.The Dialog tab under IxServer Options

IxVM
Configuring NTP
NTP server options The IxVM-enabled version of IxServer supports a number of options for using an
for IxVM cards NTP time server. To configure NTP for IxVM:
1. Display the copy of IxServer running on the IxVM Windows controller host.
2. Click TOOLS| OPTIONS | DIALOG.
3. In the NTP Master Server field, enter one of the following:
• IP address of an NTP server that is reachable by the IxVM cards
• Hostname of an NTP server (the host name must be resolvable by DNS
and reachable by the IxVM cards)
• 0, to disable the IxVM cards from sourcing NTP through Ixia applications.
If you use this option, you must supply a time source to the IxVM cards by
some other means.

IxVM
39 Single-port vs. Multi-port Cards
Single-port vs. Multi-port Cards

There are two types of IxVM virtual load modules: single-port and multi-port.
• Single-port load modules have one interface (virtual port) for generating test
traffic.
• Multi-port load modules have multiple interfaces for generating test traffic.
All IxVM virtual load modules require one interface for management traffic, and
at least one interface to generate test traffic.
• Single-port modules are virtual appliances operating in a mode that supports
the management interface and one test traffic interface. On a single-port card,
all the resources are dedicated to a single test port, which can yield higher
per-port performance than on a multi-port card (because there is only one test
port). On a single-port card, the eth0 interface is the card management inter-
face, and eth1 is the single test traffic interface. With a single-port card, the
test traffic and the emulated routing topology traverse a single virtual net-
work.
• Multi-port modules are virtual appliances operating in a mode that supports
the management interface and one or more test traffic interfaces. On a multi-
port card, the resources are distributed across multiple test ports. On a multi-
port card, eth0 interface is the card management interface (same as a single-
port card), and eth1 through ethN are the multiple test interfaces. With a
multi-port card, the test traffic and the emulated routing topology may
traverse multiple virtual networks.
Some test traffic and routing protocols are only supported on single-port cards,
while others are supported on either type.
One virtual chassis can control up to 32 virtual cards.
Note: The IxVM test ports can also be TAP interfaces created on the Virtual
Machines.
Converting Single- You can convert a single-port card into a multi-port card, or add ports to an
port cards into Multi- existing multi-port card. There are three tasks required for this process:
port cards 1. For each test port that you want to add, create an additional test network.
2. Add the additional test ports to the VM card.
3. In the test application (IxExplorer, IxNetwork, or IxLoad), add or discover the
ports added to the card.
Step 1. Create the If you are adding ports to a multi-port card, each port should have its own
Additional Test network in vSphere. Use the procedure below to create an additional test
Networks network.

IxVM
Single-port vs. Multi-port Cards
To create an additional test network in vSphere:

1. Login to vSphere client.
2. Select the ESX(i) host.
3. Click the CONFIGURATION tab.
4. In the Hardware area, click NETWORKING.
5. Click ADD NETWORKING (upper right).
The Add Network Wizard displays, with the Connection Type set to Virtual
Machine.
6. Click NEXT.
The Network Access pane displays.
7. Select CREATE A VIRTUAL SWITCH, then click NEXT.
8. In the NETWORK LABEL field, enter a label for the additional test network,
then click NEXT, then click FINISH.
Step 2. Add Ports to To add ports to an IxVM card, use the procedure below.
the Card
To add ports to an IxVM card:
1. Login to vSphere client.
2. Select the VM you want to add ports to.
3. SHUT DOWN or POWER OFF the VM.
4. Select the VM, and then click EDIT VIRTUAL MACHINE on the Getting
Started tab.
The Virtual Machine Properties window displays.
5. On the Hardware tab, click ADD.
The Add Hardware wizard displays, with the Device Type pane selected.
6. Select Ethernet Adapter, then click NEXT.
The Network Connection pane displays.
7. In the Adapter Type field, select VMXNET3.
8. In the Network Label field, select the destination test network, then click
NEXT, then click FINISH.
9. Repeat steps 4-8 for any additional ports you want to add.
10. Click OK to close the window.
11. Power on the VM.
Step 3. (IxExplorer): In IxExplorer, after adding ports to a card, you must manually add (or re-add) a
Adding a Multi-port card to the card list.
Card
To manually add a multi-port card to an IxVM chassis:

IxVM
39 Single-port vs. Multi-port Cards
1. In vSphere client, select the chassis, click CONSOLE, and login to Windows.
2. Start IxExplorer.
3. Right-click the chassis, and then select PROPERTIES.
4. Select VIRTUAL PORTS.
5. If the card you added ports to is already in the card list, select the card, and
remove it.
6. Click the MULTI-ADD CARD (the +++Card) button.
IxExplorer adds the card as a multi-port card (the SINGLE-NIC checkbox is
not checked).
7. Select the card, then click ADD PORT. Repeat for each additional port you
are want to add.
8. Click OK.
In the chassis/card/port list, the card should now display multiple ports.
Step 4. (IxNetwork): In IxNetwork, after adding ports to a card, you use Discovery Server to
Discovering a Multi- automatically add the card and its ports to the chassis/card/port list.
port Card
To discover a card in IxNetwork:
1. After you have added ethernet adapters to the VM, you must rebuild the chas-
sis in IxNetwork, in order for Discovery Server to discover them.
2. In vSphere client, select the chassis, click CONSOLE, and login to Windows.
3. Start IxNetwork.
4. Select TEST CONFIGURATION.
5. Select PORT MANAGER.
6. Click ADD PORTS.
7. If the chassis is in the chassis list, select it. If the chassis is not in the list, add
it.
The Add Virtual Chassis window displays.
8. Make sure the PERFORM AUTOMATIC DISCOVERY is checked, then
click AUTOMATIC.
IxNetwork triggers Discovery Server to discover IxVM cards. After the

discovery process is complete, the card should now display multiple ports in the
chassis/card/port list.

IxVM
Sample Configuration
This section describes the steps in creating a sample IxVM configuration. You
can use the steps in this section as a guide in creating your own configuration.
Step 1. Install If you have not already installed vSphere, follow the procedure for installing
vSphere vSphere.
For details see Downloading and Installing vSphere on page 39-15.
Configuration Details
By default, VMware creates one virtual switch, vSwitch0, which is used to

access the ESX(i) server over the corporate LAN. VMware applies the name VM
Network to the network served by vSwitch0. In the IxVM Windows VM in this
example, this network is labeled Corporate Network.

IxVM
39 Sample Configuration
Step 1. Configure In vSphere, create two virtual switches (vSwitches): one to serve the network that
the Source and carries the IxVM card management traffic, and one for the network that carries
Destination the test traffic. In vSphere, these are named source and destination networks.
Networks For details see Creating the Source and Destination Networks on page 39-16.
Name the networks as follows:

• vSwitch1: IxVM Management Network
• vSwitch2: IxVM Test Network 1
Step 3. Deploy a In vSphere, create a Windows VM with two NICs. Refer to the IxOS release
Windows VM notes for the list of Windows versions that IxVM supports.
• Name the VM Chassis01.

IxVM
• Create two networks, named and mapped as follows:
vSphere Network Function
VM Network (default Access to the virtual chassis from the corporate LAN
name)
IxVM Management IxVM card virtual backplane

Network
Step 4. Deploy the Deploy two Linux VMs based on the Ixia kernel OVA.
Linux OVA Template
For details see Deploying the IxVM Appliances (OVAs) on page 39-17.
• Name the first VM Card01
• Name the second VM Card02

IxVM
• Map the networks as follows:
Source Network Destination Network
IxVM Test Network 1 IxVM Test Network 1
IxVM Management IxVM Management Network

Network
Step 5. Configure If you configured the IxVM cards (Card01, Card02, Linux OVAs) to use DHCP
the IxVM card addressing, skip this step.
(Linux OVA)
If you configured the IxVM cards to use static addressing, configure their
Addresses addresses.
For details see Configuring Static Addressing on page 39-18.
• Card01 addresses:

IxVM
eth0: 10.0.0.1
eth1: <no address>
• Card02 addresses:
eth0: 10.0.0.2
eth1: <no address>
Use the console to test connectivity by pinging card02 from card01 (or vice-
versa).
Step 6. Configure Configure the IxVM chassis controller (the Windows VM), and start IxVM and
the IxVM Chassis the supporting services on it.
Addresses 1. Login to the Windows VM, and go through the procedure to license Win-
dows.
2. Download and install the following components on the IxVM chassis control-
ler.
• IxVM Server
• Discovery Server

IxVM
3. Rename the two local area connections as follows:

• Local Area Connection 1: VM network
• Local Area Connection 2: IxVM Management Network
4. If you configured the IxVM chassis controller to use static addressing, config-
ure its addresses as follows:
VM network: 10.200.27.250/24 (Default gateway: 10.200.27.1)
IxVM Management Network = 10.0.0.250/24 (Default gateway: none)
Step 7. Discover Start the Windows services, and discover the IxVM cards:
the IxVM Cards 1. Start IxServer.
2. Start Discovery Server.
3. In Discovery Server, uncheck CORPORATE NETWORK (10.200.x.x, there
are no VMs on this network).
4. Click SERVER | START BROADCAST to start Broadcast Discovery.

IxVM
5. Click the AUTODISCOVERY tab. This tab should indicate that two end-
points (the IxVM cards) have been discovered.
6. Close the Discovery Server window.
The Discovery Server minimizes and continues to run.
The IxVM cards are ready for use. Start IxExplorer, IxNetwork, or IxLoad
and add them to your list of ports.

IxVM
39 What to do Next
What to do Next
After you have installed IxVM, you can begin using it. There are two things you
need to do to use IxVM with an Ixia testing application:
• Confirm that IxVM supports the protocols that you want to use.
• Find the IxVM virtual load modules running on your test network, and add
them to your test configuration.
Supported Protocols
To confirm that IxVM supports the protocols you want to use in a test, check the
list of supported protocols in the the test application's user guide.
Finding and Adding IxVM Load Modules
To find and add IxVM load modules, use the Discovery Server. Directions for
using Discovery Server are included in the test application's user guide.
Deployment Wizard
As IxVM continues to be adopted by more users, software based test assets will
keep on multiplying. The user will take considerable time to deploy large scale
systems manually. This could be error prone when port counts reach thousands.
The IxVM Deployment Wizard allows for mass deployment of IxVM software
test assets into large scale test environments. It also automates the upgrade of an
existing mass deployment to a new version of the software. This facilitates the
deployment and upgrade of Windows Virtual Controllers and Virtual Load
Modules.You can perform the following actions by using Deployment Wizard:
• Upgrade Virtual Chassis
• Install New Virtual Chassis
Upgrade Virtual You can upgrade an existing virtual chassis using the Deployment Wizard.To
Chassis upgrade an existing chassis, do the following:
1. Open the Deployment Wizard.
2. In the Start Wizard, click Upgrade Virtual Chassis.
3. Click Next. The Chassis Info window appears.
4. In the Hostname/IPbox, type the IP address of the virtual chassis.
Note: You can select the IP address by clicking Previously used. The IP
addresses of the chassis that were previously used appears. You can select the
IP address of the chassis that you want to upgrade.

IxVM
Deployment Wizard
Click Next. The Source Files dialog box appears.
Click to select the path of each Ixia software installed on the Windows Virtual
Controller computer.
Select each Ixia software you want to uninstall.
You can select the following source files:

• IxServer file
• Discovery Server file
• IxNetwork file
Upgrade the load modules by performing the following actions:
Upgrade Appliances
The Upgrade Appliances window shows a list of virtual load modules that you
want to update.The following table describes the properties of the virtual load
modules:
Field/Control Description
State If the virtual load module is available, the

check box is selected. In this case, the virtual
load module is not assigned to another virtual
chassis.
Type Shows the type of appliance, for example, PC,

Qemu,or Vmware.
Appliance Shows the name of the virtual load module

that you want to update.
IP Address Shows the IP address of the virtual load mod-

ule.
Info Shows the list of installed Ixia software on the

virtual load module.
NICs No Shows the number of virtual interfaces that

are defined for each virtual load module.
Select Source Files
The Select Source Files window allows you to select the source files to upgrade
an existing VM quest OS or IxNetwork to the new version of Ixia software.
1. Click to select the source files needed to upgrade the installed Ixia software
(.rpm, .zip).

• IxOS package or .rpm file

IxVM
39 Deployment Wizard
• IxNetwork package or .rpm file
Install New Virtual You can install a new virtual chassis using the Deployment Wizard.To install a
Chassis new chassis, do the following:
• Configure Windows Virtual Controller Settings
• Configure Virtual Load Module Settings
Xen support in Deployment Wizard offers support for deploying Virtual Load Modules on a Xen
Deployment Wizard host.
The following image shows the Host Type in Deployment Wizard:
Figure 39-50.The Host Type in Deployment Wizard
After testing Xen Host connection with the given credentials, on the next page
the Host Settings window shows as follows:

IxVM
Deployment Wizard
Figure 39-51.The Host Settings window
1. Type the No. of Virtual Load Modules to be created.

2. Type the Virtual Load Module Name.
3. Select the Host Datastore.
4. Select the virtual bridges for IxVM Card Management Network and IxVM
Test Network.
The self-extracting image (.sh file) used for Virtual Load Module deployed on
Xen is different from the Qemu/KVM .sh file (the .sh file name contains the
hypervisor name).
The summary page shows the options selected by you on the Install new Virtual
Load Module workflow as shown in the following figure:

IxVM
Figure 39-52.The Virtual Load Module workflow
To deploy a virtual load module manually on a Xen hypervisor you can use the
following example:
[root@10-205-15-55 OVAs]# chmod +x VM_IxVM_XEN-2.0.0.218.sh
[root@10-205-15-55 OVAs]# ./VM_IxVM_XEN-2.0.0.218.sh
Configure Windows You can configure the settings for Windows Virtual Controller.To configure the
Virtual Controller settings, do the following:
Settings 1. Open the Deployment Wizard.
2. In the Start Wizard window, click Install New Virtual Chassis and Virtual
Load Modules.
3. Click Next. The Chassis Info window appears.
4. Enter the host details for the existing Windows Virtual Machine or Windows
computer. For more information, see Configure Host Details.
5. Click Next. The Source Files window appears.
6. Click to select the source files needed to install a Virtual Controller on an
existing OS.

• IxServer file
• Discovery Server file
• IxNetwork file
• Configure Host Details

IxVM
Deployment Wizard
The following table describes the host details that you need to enter for an
existing Windows Virtual Machine or Windows computer:
Host Info Click Previously used to select the IP

address. The IP addresses of the chassis that
were previously installed appears. You can
select the IP address of the chassis that you
want to install.
IP/Name Type the IP address of the existing Windows

computer where you want to install the virtual
chassis.
User Name Type the name of the existing Windows

computer.
Password Type the password of the existing Windows

computer.
Domain Select the check box next to the Domain box

to make it available. You can enter the domain
name of the existing Windows computer.
Test Connection Click Test Connection to validate the input

credentials.
Configure Virtual You can configure the settings for the characteristics of the Virtual Load Module
Load Module you create. The characteristics include hypervisor type, virtual machine name,
Settings number of virtual machines, datastore and virtual network interfaces
assignments.To configure the settings, do the following:
1. Open the Deployment Wizard.
2. Configure the Windows Virtual Controller settings. For more information, see
Configure Windows Virtual Controller Settings.
3. Click Host Type. The Host Type window appears.
4. Enter the host details for the Virtual Load Module. For more information, see
Configure Host Details.
5. Click Next. The Host Settings window appears.
6. Configure the host settings. For more information, see Configure Host Set-
tings.
7. Click Next. The Source Files window appears.
8. Click to select the source files needed to install a new guest OS (.ova, .sh).
9. Click Start to run the upgrade or installation process.

IxVM
Configure Host Details
The following table describes the host details for the Virtual Load module:
Select Virtual Load Click the relevant host OS information:

Modules Host Options include the following:
Server • Sphere
• QEMU
• Bare-Metal
Find Previous Click to find the information of hosts that you

have used previously. Selecting a host from
the list automatically shows the following host
information:
• IP/Name
• User Name
• Password
IP/Name Type the IP address of the host server.
User Name Click to find the host network.
Password Type the password of the host server.
Domain Select the check box to include the domain to

which the host server belongs.
Test Connection Click Test Connection to validate the input

credentials.
Configure Host Settings
The following table describes the host settings that you need to configure for the
Virtual Load Module:
Guest Machine Enter the desired name for the guest

Name machines based on which it will automatically
increment for new installation selections.
Note: The name of the guest machine will be
followed by an incremental number from 1 to
the Number of Guests per Host.
Number of Guests Enter the numbers of guests you need to

per Host create on the host. The maximum number of
guests per host is 32.
Find Host Click to show the available datastores for the

Datastores selected hypervisor.
Host Datastore Click the list to select the data store from the
ones available on the host.

IxVM
Deployment Wizard
Find Host Click to show the available virtual switches/

Networks bridges for the selected hypervisor.
IxVM Card Click to select the Card Management Network

Management information.
Network
IxVM Test Network Click to select the test network information for
both Linux and Bare metal sources.
Jobs Manager Jobs Manager is a component of IxVM’s Deployment Wizard and it shows a
multi-level progress log and thermometers indicating relative progress as the
virtual chassis are built or upgraded.
Jobs Manager is a Windows application that appears in the notification area. It

gets started on the host on startup and is used for the following activities:
• To obtain feedback on the progress and the status of jobs that are running and
the previously run jobs.
• To monitor the IxVM JobInstaller service status and to start the service.
• To show the list of current jobs with their statuses and to allow you to retry,
continue, or abort a job.
The Jobs Manager notification area contains the following icons as the status of
the IxVM JobInstaller service or the status of the current job that is being
processed:

IxVM
Figure 39-53.The Jobs Manager icons in the notification area
In addition to this, a notification balloon appears for the following most

important operations that take place while using Jobs Manager:
• A new job was added to the job queue
• An in progress job returned an error
• Waiting for manual intervention
• A job has finished
• Chassis rebuild has finished
The Continue, Retry, Abort, Remove, and Rebuild chassis commands are
available or unavailable depending on the selected job’s current status. For
example, you can only rebuild the chassis if the jobs have finished without errors.
The Show log command refers to the currently selected job and creates a .csv file
that shows the message exchange that took place between IxVM’s JobInstaller
service and the computer that is upgraded or built.
The following image shows the current progress of jobs:
Figure 39-54.The The Jobs Manager List Window

IxVM
Troubleshooting and Tips

Following are some of the troubleshooting tips:
• IxNetwork fails to connect to Virtual Chassis (Retrying…)
Symptoms: IxServer is running and VM is IP reachable.
Attempts to restart Hardware Manager still do not resolve the issue.
Verify that the IP Address present in the file C:\Program
Files\Ixia\IxOS\<IxOS_Version>\IxiaChassisIpEntry.txt matches the valid
IP address of the interface used to communicate with the IxNetwork cli-
ent.
• IxVM RPM fails to install on Bare-Metal RHEL or CentOS machine
Symptoms: rpm –ivh command fails with error messages indicating that
dependencies are missing.
Before you install the IxVM RPMs, download and install the compat-lib-
stdc++-33-* RPM that matches your version of Linux.
• Management network connectivity issues in a Bare-Metal Linux Installa-

tion
Try using the following settings:

IxVM
39 Troubleshooting and Tips
Firewall Configuration -> Security Level, try using Disabled

Firewall Configuration -> SELinux, try using Disabled
Figure 39-56.The Firewall Configuration screen
• Statistics De-synchronization and Clock Synchronization

Symptoms: Stats in the IxNetwork stat views are intermittently vanishing
and re-appearing.
VM-VM scenarios
Ensure that all of your VMs are synchronized to the same NTP server, by
calling "ntpq –p" on the linux console, and ensure that the server listed is
the name/IP address of the system running IxServer VM.
If your VMs which are connected to one instance of IxServer are not syn-
chronized to the same time source, then you may have a third party appli-
cation updating your local NTP time. See below as to how to customize
your NTP Server configuration.
In order to customize the NTP Server being used to synchronize each VM,
you can specify the NTP Server used to synchronize all VMs connected to
an instance of IxServer with the "NTPServerLocation" registry string,
located in the "HKEY_LOCAL_MACHINE\Software\Ixia Communica-
tions\IxServer\Debug" registry key.
Set to the IP Address of a valid NTP Server.
Set to "0" to prevent IxVM from managing any synchronization with NTP
(if you would like to manage it for each VM on your own).

IxVM
In case you have multiple instances of IxServer VM managing all of your

VMs, set the value on all machines running IxServer VM to the same IP
address.
VM-HW scenarios
In order to synchronize IxVM cards between VMs and Ixia HW, the fol-
lowing steps are needed.
The NTPServerLocation registry key (see 10.1.2.2) needs to be set to an
external NTP server based off of UTC time (see pool.ntp.org for more
information) and the VMs need external internet connectivity to be able to
communicate with those IP addresses.
The hardware-based ports need to be synchronized to use an AFD1 GPS
server as their time source.
• One Way Latency Measurement
Symptoms: User sees negative min/max/average latency in the IxNetwork
traffic flow views, and IxExplorer’s latency view.
When running traffic between multiple different VM cards, IxVM is using
software to synchronize the VM cards with each other, which does not
give enough precision and leads to one VM card having a local time ahead
of the other VM card. Inter Arrival time does not have this issue.
• Cannot run Control Plane Traffic over MPLS
In IxNetwork, one of the the default settings for MPLS (LDP) is to run
Control Plane traffic over MPLS. The RedHat/CentOS kernel does not
support this; the Ixia kernel does.
Tips • IxVM virtual ports cannot be attached to multiple IxVM Servers. You should
disconnect the virtual port from one server, reboot the virtual port’s host OS
and reconnect to the port from the other server.
• Latency measurement in software is low-precision. You should expect to see
typical accuracy of tens of milliseconds, and will occasionally see negative
latency values.
• Latency statistics are only available from one IxExplorer or TCL client per
port. Two IxExplorer users (or an IxExplorer user and a TCL client session)
cannot access latency stats simultaneously for the same virtual port.
• The IxVM Server must be on the same network as the virtual ports – no fire-
walls or NAT devices should be placed between the IxVM Server and virtual
ports.
• Firewalls and SELinux policies should be disabled on the virtual port
OS.Active iptables firewall on host.
• In order for some protocols like DHCP, PPP, L2TP, that require unique identi-
fication based on the MAC address, the ports should be added to the chassis
with promiscuous mode enabled.

IxVM
39 Troubleshooting and Tips
Active iptables IxServer and IxVM communicates through TCP or UDP ports, and if there is a
firewall on host firewall on the host computer, you need to add some additional rules to allow
traffic from IxServer.
If the Linux VM communicates with the host through a bridge, the iptables
firewall should not affect the communication between the Windows VM and
Linux VM.
If the traffic between the Windows VM and Linux VM is blocked, following are
some examples of how to add new rules so that IxVM works properly.
The examples show how to allow the traffic for the udp port 123, which is
required for NTP.
iptables -A INPUT -p udp --dport 123 -j ACCEPT
When there is no more need to run IxVM, you can delete
this rule by typing the following iptables command:
iptables -D INPUT -p udp --dport 123 -j ACCEPT
The iptables rules order is important because the first rule has precedence. If one
iptable rule matches the incoming traffic, the rest of them are ignored. Hence, the
iptable rule that accepts the traffic should be added before the iptable rule that
drops or rejects the traffic.
For viewing the iptable filtering rules, use the following command:
iptables –nvL.
The following output represents an example output of the iptables –nvL

command:
Figure 39-57.The example output of the iptables –nvL command
This output shows that there are two ports and protocols that are accepted by the
iptable firewall and the last rule shows that everything else is rejected.
If you want to add another iptable rule to accept additional traffic, you need to
add it before the REJECT rule.
The following command adds the rule to accept the NTP traffic before the reject
rule.
iptables -I INPUT 1 -p udp --dport 123 -j ACCEPT
The preceding command adds the iptable rule on the first position. You can
specify the position of the iptable rule by modifying the parameter.
iptables -I INPUT x … (x represents the rule number)

IxVM
To delete such a rule, the rule number must be specified:

iptables -D INPUT x (x-represents the rule number)
You should add the same rules for all the required ports. All the ports that are
needed for communication between Windows VM and Linux VM are listed in
the ‘TCP/UDP Ports Required’ section.
In addition, the firewall should allow the outgoing traffic from the Linux VMs.
One way for doing this is to allow all the traffic that comes from the Linux VMs.
iptables -I OUTPUT 1 -p tcp --src a.b.c.d -j ACCEPT,
where a.b.c.d is the Linux VM ip.
Note that this ip should be internet-routable.

IxVM
39 TclAPI Support
TclAPI Support
This section describes the IxOS TclAPI commands and statistics that you can use
with an IxVM virtual load module.
In this section:
IxOS Tcl API Commands
IxOS Statistics
IxOS Tcl API You can use the following IxOS TclAPI commands with IxVM virtual load
Commands modules:
• arp
• arpServer
• autoDetectInstrumentation
• byte2IpAddr
• card
• chassis
• chassisChain
• cleanUp
• clearAllMyOwnership
• dectohex
• errorMsg
• filter
• filterPallette
• hextodec
• host2addr
• ip
• ipAddressTable
• ixCheckLinkState
• ixCheckOwnership
• ixCheckTransmitDone
• ixClearArpTable
• ixClearOwnership
• ixClearPacketGroups
• ixClearPerStreamStats

IxVM
TclAPI Support
• ixClearPortPacketGroups
• ixClearScheduledTransmitTime
• ixClearStats
• ixClearTimeStamp
• ixCollectStats
• ixConnectToChassis
• ixConnectToTclServer
• ixDisconnectFromChassis
• ixDisconnectTclServer
• ixEnableArpResponse
• ixErrorInfo
• ixGetChassisID
• ixGlobalSetDefault
• ixInitialize
• ixLogin
• ixLogout
• ixPortClearOwnership
• ixPortTakeOwnership
• ixPuts
• ixRequestStats
• ixSetAdvancedStreamSchedulerMode
• ixSetPacketStreamMode
• ixSetPortPacketGroupMode
• ixSetPortPacketStreamMode
• ixSetScheduledTransmitTime
• ixSource
• ixStartPacketGroups
• ixStartPortPacketGroups
• ixStartPortTransmit
• ixStartTransmit
• ixStopPacketGroups
• ixStopPortPacketGroups
• ixStopPortTransmit
• ixStopTransmit
• ixTakeOwnership

IxVM
39 TclAPI Support
• ixTransmitArpRequest
• ixWriteConfigToHardware
• ixWritePortsToHardware
• logMsg
• logOff
• logOn
• map
• mpexpr
• packetGroup
• port
• portGroup
• protocol
• showCmd
• stat
• stream
• streamTransmitStats
• tableUdf
• tableUdfColumn
• tcp
• udf (udf set 2/3 not supported)
• user
• version
• vlan
IxOS Statistics You can use the following IxOS statistics IxVM virtual load modules:
Note: Some statistics may only work if the protocol or feature they measure is
enabled. For example, bgpTotalSessions only returns a valid value if BGP is
enabled. This is the same behavior as for physical load module.
• asynchronousFramesSent
• bfdAutoConfiguredSessionsUp
• bfdRoutersConfigured
• bfdRoutersRunning
• bfdSessionFlap

IxVM
TclAPI Support
• bfdSessionsAutoConfigured
• bfdSessionsConfigured
• bfdSessionsUp
• bgpSessionFlap
• bgpTotalSessions
• bgpTotalSessionsEstablished
• bitsReceived
• bitsReceivedSStream
• bitsSent
• bitsSentSStream
• bytesReceived
• bytesReceivedSStream
• bytesSent
• bytesSentSStream
• captureFilter
• captureTemperature
• cfmBridgesConfigured
• cfmBridgesRunning
• cfmMasConfigured
• cfmMasRunning
• cfmMepsConfigured
• cfmMepsRunning
• cfmRemoteMepsLearned
• cfmSessionFlap
• cfmTrunksConfigured
• cfmTrunksRunning
• droppedFrames
• egressDroppedFrames
• eigrpNeighborDeleted
• eigrpNeighborsLearned
• eigrpRoutersConfigured
• eigrpRoutersRunning
• enableArpStats
• enableBfdStats
• enableBgpStats

IxVM
39 TclAPI Support
• enableCfmStats
• enableEigrpStats
• enableIgmpStats
• enableIsisStats
• enableLdpStats
• enableMldStats
• enableMplsTpStats
• enableNeighborSolicitStats
• enableOamStats
• enableOspfStats
• enableOspfV3Stats
• enablePimsmStats
• enableProtocolServerStats
• enableRsvpStats
• enableStpStats
• framesReceived
• framesReceivedSStream
• framesSent
• framesSentSStream
• isisIpV4GroupRecordsLearned
• isisIpV6GroupRecordsLearned
• isisL1DBSize
• isisL2DBSize
• isisMacGroupRecordsLearned
• isisNeighborsL1
• isisNeighborsL2
• isisRBridgesLearned
• isisSessionFlapL1
• isisSessionFlapL2
• isisSessionsConfiguredL1
• isisSessionsConfiguredL2
• isisSessionsUpL1
• isisSessionsUpL2
• ldpBasicSessionsUp
• ldpSessionFlap

IxVM
TclAPI Support
• ldpSessionsConfigured
• ldpSessionsUp
• link
• mode
• portCpuBytesReceived
• portCpuFramesReceived
• portCPUFramesSent
• portCpuStatus
• protocolServerRx
• protocolServerTx
• protocolServerVlanDroppedFrames
• rxArpReply
• rxArpRequest
• rxNeighborAdvertisements
• rxNeighborSolicits
• rxPingReply
• rxPingRequest
• scheduledFramesSent
• scheduledTransmitTime
• sequenceErrors
• sequenceFrames
• streamTrigger1
• streamTrigger2
• transmitDuration
• transmitState
• txArpReply
• txArpRequest
• txNeighborAdvertisements
• txNeighborSolicits
• txPingReply
• txPingRequest
• userDefinedStat1
• userDefinedStat2
• vlanTaggedFramesRx

IxVM
39 TclAPI Support
List of DHCP These are option names used in Open DHCP Server. These are based on IANA
Options names less spaces and dashes. Please refer to http://www.iana.org/assignments/
bootp-dhcp-parameters/bootp-dhcp-parameters.xml for more info. You can also
use options not listed here using tag names directly.
Tag Option Name IANA Name Meaning

in
Open DHCP
Server
1 SubnetMask Subnet Mask Subnet Mask Value

2 TimeOffset Time Offset Time Offset in Seconds from UTC (note:
deprecated by 100 and 101)
3 Router Router N/4 Router addresses
4 TimeServer Time Server N/4 Timeserver addresses
5 NameServer Name Server N/4 IEN-116 Server addresses
6 DomainServer Domain Server N/4 DHCP Server addresses
7 LogServer Log Server N/4 Logging Server addresses
8 QuotesServer Quotes Server N/4 Quotes Server addresses
9 LPRServer LPR Server N/4 Printer Server addresses
10 ImpressServer Impress Server N/4 Impress Server addresses
11 RLPServer RLP Server N/4 RLP Server addresses
12 Hostname Hostname Hostname string
13 BootFileSize Boot File Size Size of boot file in 512 byte chunks
14 MeritDumpFile Merit Dump Client to dump and name the file to dump it to
File
15 DomainName Domain Name The DNS domain name of the client
16 SwapServer Swap Server Swap Server address
17 RootPath Root Path Path name for root disk
18 ExtensionFile Extension File Path name for more BOOTP info
19 ForwardOn/Off Forward On/ Enable/Disable IP Forwarding

Off
20 SrcRteOn/Off SrcRte On/Off Enable/Disable Source Routing
21 PolicyFilter Policy Filter Routing Policy Filters
22 MaxDGAssem Max DG Max Datagram Reassembly Size

bly Assembly

IxVM
TclAPI Support

in
Open DHCP
Server
23 DefaultIPTTL Default IPTTL Default IP Time to Live
24 MTUTimeout MTU Timeout Path MTU Aging Timeout
25 MTUPlateau MTU Plateau Path MTU Plateau Table
26 MTUInterface MTU Interface Interface MTU Size
27 MTUSubnet MTU Subnet All Subnets are Local
28 BroadcastAddr Broadcast Broadcast Address

ess Address
29 MaskDiscovery Mask Perform Mask Discovery

Discovery
30 MaskSupplier Mask Supplier Provide Mask to Others
31 RouterDiscover Router Perform Router Discovery

y Discovery
32 RouterRequest Router Request Router Solicitation Address
33 StaticRoute Static Route Static Routing Table
34 Trailers Trailers Trailer Encapsulation
35 ARPTimeout ARP Timeout ARP Cache Timeout
36 Ethernet Ethernet Ethernet Encapsulation
37 DefaultTCPTT Default Default TCP Time to Live

L TCPTTL
38 KeepaliveTime Keepalive Time TCP Keepalive Interval
39 KeepaliveData Keepalive Data TCP Keepalive Garbage
40 NISDomain NIS Domain NIS Domain Name
41 NISServers NIS Servers NIS Server Addresses
42 NTPServers NTP Servers NTP Server Addresses
44 NETBIOSName NETBIOS NETBIOS Name Servers
Srv Name Srv
45 NETBIOSDistSr NETBIOS Dist NETBIOS Datagram Distribution

v Srv
46 NETBIOSNode NETBIOS Node NETBIOS Node Type

Type Type
47 NETBIOSScop NET BIOS NETBIOS Scope

e Scope

IxVM
39 TclAPI Support

in
Open DHCP
Server
48 XWindowFont XWindow Font X Window Font Server

49 XWindowMana XWindow X Window Display Manager
ger Manager
51 AddressTime Address Time IP Address Lease Time

58 RenewalTime Renewal Time DHCP Renewal (T1) Time
59 RebindingTime Rebinding Time DHCP Rebinding (T2) Time
62 NetWare/ NetWare/IP NetWare/IP Domain Name
IPDomain Domain
63 NetWare/ NetWare/IP NetWare/IP sub Options

IPOption Option
64 NIS-Domain- NIS-Domain- NIS+ v3 Client Domain Name

Name Name
65 NIS-Server- NIS-Server- NIS+ v3 Server Addresses

Addr Addr
66 TFTPServerNa Server Name TFTP Server Name

me
67 BootFileOption BootFile-Option Boot File Name
68 HomeAgentAdd Home-Agent- Home Agent Addresses

rs Addrs
69 SMTPServer SMTP-Server Simple Mail Server Addresses
70 POP3Server POP3-Server Post Office Server Addresses
71 NNTPServer NNTP-Server Network News Server Addresses
72 WWWServer WWW-Server WWW Server Addresses
73 FingerServer Finger-Server Finger Server Addresses
74 IRCServer IRC-Server Chat Server Addresses
75 StreetTalkServe StreetTalk- StreetTalk Server Addresses

r Server
76 STDAServer STDA-Server ST Directory Assist. Addresses
78 DirectoryAgent Directory Agent directory agent information
79 ServiceScope Service Scope service location agent scope
83 iSNS iSNS Internet Storage Name Service
85 NDSServers NDS Servers Novell Directory Services
86 NDSTreeName NDS Tree Novell Directory Services

Name

IxVM
TclAPI Support

in
Open DHCP
Server
87 NDSContext NDS Context Novell Directory Services
95 LDAP LDAP Lightweight Directory Access Protocol
100 PCode PCode IEEE 1003.1 TZ String
101 TCode TCode Reference to the TZ Database
112 NetinfoAddress Netinfo Address NetInfo Parent Server Address
113 NetinfoTag Netinfo Tag NetInfo Parent Server Tag
114 URL URL URL

IxVM
39 TclAPI Support

Chapter 40: XAir™ XM Module
40
Ixia’s new XAir™ is the next generation hardware for LTE UE emulation. It
delivers the unparalleled LTE performance in the smallest footprint providing the
industry highest UE density. This module will allow LTE Advanced feature
support. The XM/XG platform can easily expand to support additional sectors.
With the XAir module, complex subscriber modeling can be achieved with the
following parameters:
• 1000 UEs per sector
• Voice (VoLTE), Video and Data Traffic Support
• QoE analysis and scoring of each traffic stream
• Mobility over multiple sectors
• Channel Modeling per UE
Each XAir board supports one sector, with 1 Gbps Ethernet ports connected to
the IxLoad Xcellon NP or IxCatapult m500/p250 chassis. It also supports up to 4
CPRI interfaces to an eNB or to Ixia’s Remote Radio Head r10 units that cover
all FDD & TDD frequency bands.

XAir™ XM Module
40 Key Features
Key Features
• Highest density LTE UE emulation starting at 1000 connected active UEs per
board
• Board has its own high accuracy 10MHz clock for eNB synchronization
• Based on Ixia’s NP technology for line-rate traffic through a large number of
connections
• Fully compatible with the Ixia XM/XG chassis and load modules for seam-
less testing with other Ixia hardware and test applications.
Specifications
Table 40-1. XAir Module Specifications
Hardware Specification
Number of Ports 3x 1 Gbps Ethernet ports, 1x 10 Gbps Ethernet port,

4x Optical SFP+ CPRI ports, 1x Serial port, SMA
Clock In/Out and Analog Out
Physical
Form Factor 1U Module for insertion into Ixia XM/XG chassis
Height 12.00” (304.8mm)
Width 1.28” (32.5mm)
Depth 15.95” (405.1mm)
Gross Weight 7.5 lbs (3.4kg)
Power Consumption 184 Watts

XAUI Connector
Appendix A:
A Specifications
Description
The following cable and accessories for the 10GE XAUI cards are described in
this appendix. These include the following:
• Standard Connector Specifications: The signals carried on the Load Module’s
XAUI connector.
• Front Panel Loopback Connector: A connector used to loopback XAUI
signals at the external connector.
• Standard Cable Specification: The CAB10GE500S1 (20”) and
CAB10GE500S2 (40”) cables.
• SMA Break-Out Box: The BOB10GE500 SMA break-out box.
• XAUI Fujitsu to XENPAK Adapter: An adapter used with Ixia XENPAK load
modules to create a XAUI interface.
• XAUI Tyco Interoperability Backplane HM-Zd Adapter: An adapter used to
connect to the Tyco Interoperability Backplane.
Ixia Platform Reference Guide, Release 6.60 EA Patch1 A-1

A Standard Connector Specifications
Standard Connector
Specifications
The Ixia XAUI Load Module’s front panel connector is the Fujitsu MicroGiGa.
This connector can be mounted on the Device Under Test (DUT), eliminating the
need for SMA cables. This part is also available directly from Fujitsu as part
number FCN-268D008-G/1D-/2D.
The connector as mounted on the Ixia load module is shown in Figure A-1, along
with the signal names, functional description, and connector pin assignments.
The same pinouts apply to XENPAK load modules which use the XENPAK to
XAUI adapter.
Figure A-1. Fujitsu MicroGiGa Connector Mounted on Load Module
The XAUI Cable plugs into the load module and transposes the transmit and
receive signals, as shown in the following figure.
A-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Standard Connector Specifications
Figure A-2. XAUI Cable Pinouts

A Front Panel Loopback Connector
Front Panel Loopback

Connector
In order to verify that the Ixia XAUI Load Module is operational, a loopback
connector may be used to test external loopback on the front panel. You can
remove the connector by pulling back on the blue handle, releasing the
connection to the Fujitsu MicroGiGa connector. The loopback connector (Ixia P/
N LPG10GE500) is shown in the following figure.
Figure A-3. XAUI Front Panel Loopback Connector

Standard Cable Specification
Standard Cable Specification

The same connector and pin assignments used on the Load Module can also be
used on the Device Under Test (DUT). Ixia supplies a 20-inch cross-pinned cable
assembly (CAB10GE500S1) that allows a straight connection as shown in Figure
A-5. This cable can also be used for loopback testing on an Ixia chassis equipped
with two or more XAUI ports. Longer cable assemblies can be made on request,
but we do not recommend that the cable length exceed 2 meters, because losses
and skew may become unacceptable. Ixia makes a 40” cable available as part
number CAB10GE500S2. The 40” cable is shown in Figure A-4.
Figure A-4. Ixia XAUI Cable (CAB10GE500S2)
Note: The 50cm maximum length suggested in the XAUI section of 802.3ae is a
rough guideline for keeping the losses on PCB traces under 7.5 dB. Well
designed cables usually have much lower losses per meter than PCB traces, so
cables can be much longer than 50cm.

A Standard Cable Specification
Figure A-5. Direct XAUI Interface Using Ixia Supplied Cable

SMA Break-Out Box
SMA Break-Out Box
If the DUT uses coaxial connectors for the XAUI interface, a special break-out
box (BOB10GE500) is required in addition to the XAUI cable, as shown in
Figure A-6. You must provide the sixteen 50 ohm coaxial cables with a male
SMA connector on the end that mates to the BOB. The actual break-out box is
shown in Figure A-6.
Figure A-6. XAUI SMA Break-Out Box
Figure A-7. XAUI SMA Break-Out Box
When using coaxial cables for the XAUI interface, extreme care should be taken
to match the electrical lengths of the two cables in each pair. The pairs can be of
different lengths, since the XAUI SerDes should automatically correct for skew
between lanes. Skew between the ‘P’ and ‘N’ lines within a pair, however, can
introduce bit errors. The XAUI edge-rates can be as short as 60ps. Therefore, the
total in-pair skew should be kept below 30 ps to avoid bit-errors. Some of this in-
pair skew must be budgeted to the Load Module, Ixia XAUI cable, BOB, and the
DUT. Allocating 10ps of in-pair skew to the coax cables would require length

A XAUI Fujitsu to XENPAK Adapter
matching them to within about 0.08” (for RG-174). The propagation velocity of
coax can vary slightly between manufacturers, lots, and as it is bent or stretched.
Therefore, we recommend that coax cables be kept as short as possible.
Table A-1. XAUI Electrical Interface Performance
Impedance 100 ohm balanced differential, AC coupled.

Tx
Amplitude 1.2Vpp minimum (with 0 pre-emphasis)
Outputs
Pre-emphasis Software selectable (0, 18%, 38% or 75%)
Jitter 0.35 UI max. (UI is Unit Interval = 320ps nominal).
Impedance 100 ohm differential, AC coupled.

Rx
Amplitude 0.2 to 2.3 Vpp.
Inputs
Jitter tolerance 0.55 UI.
XAUI Fujitsu to XENPAK

Adapter
The electrical interface to XENPAK is XAUI, which uses an industry standard
70-pin connector. Ixia’s XAUI Load Module, however, uses a Fujitsu
MicroGiGa connector to both transmit and receive four XAUI lanes through
eight twisted pairs through a 20” cable. Ixia offers an adapter (part number
FXN10GE500) that routes the XAUI lanes from the Fujitsu connector to the pins
on the XENPAK connector.
This enables a XENPAK Load Module to act as a XAUI Load Module.

However, the XENPAK Load Module can only run in Ethernet mode and
transmit and verify Layer 2 or 3 traffic. Furthermore, there is an FD D-sub
connector for MDIO on the front panel of the XENPAK Load Module (shown in
Figure A-9 on page A-9). Both the MDIO and power are available through pins
on the adapter and serve the same function as the D-sub connector on the XAUI
Load Module.
The adapter is shown in Figure A-8.

XAUI Tyco Interoperability Backplane HM-Zd Adapter
Figure A-8. Fujitsu to XENPAK Adapter
MDIO Pins 70-pin connector
Fujitsu Connector
Figure A-9. CX4 and XAUI MDIO Pinouts
XAUI Tyco Interoperability

Backplane HM-Zd Adapter
XAUI interoperability testing has been conducted using a Tyco built simulated
backplane. Each XAUI vendor has been required to build a line card to connect
to the backplane through the Tyco HM-Zd connector. Tyco had also built an
SMA adapter to connect to the backplane, but it is too time-consuming and

A XAUI Tyco Interoperability Backplane HM-Zd Adapter
difficult to connect through SMAs. Ixia has built an HM-Zd adapter (P/N
FTY10GE500), which allows direct connection to the backplane through the
Fujitsu connector, saving significant setup time. This is shown in Figure A-10.
Figure A-10. Tyco Interoperability Backplane HM-Zd Adapter

Appendix B: Available Statistics
B
This appendix covers the available statistics for the following different card
types:
• Statistics for 10/100 Cards. These cards include the following:
• 10/100 TX (LM100TX)
• 10/100 TX3 (LM100TX3)
• 10/100 MII (LM100MII)
• 10/100 Reduced MII
• 100 Base FX MultiMode (LM100FX)
• 100 Base FX SingleMode (LM100FXSM)
• Copper 10/100/1000 running at 10/100 Mbps (LM1000T-5)
• Statistics for 10/100 TXS Modules. These cards include the following:
• 10/100 TX8 (LM100TX8)
• 10/100 TXS8 (LM100TXS8)
• Statistics for 10/100/1000 TXS, 10/100/1000 XMS(R)12, 1000 SFPS4, and
1000STXS24 Cards. These cards include the following:
• 10/100/1000 TX4 (LM1000TX4)
• 10/100/1000 TXS4 (LM1000TXS4)
• 10/100/1000 STX2, STX4, STX24 (LM1000STX2/4, OLM1000STX24)
• 10/100/1000 STXS2, STXS4, STXS24 (LM1000STXS2/4,
OLM1000STXS24)
• 10/100/1000 XMS12, XMSR12 (LSM1000XMS12, LSM1000XMSR12)
• 1000 SFP4 (LM1000SFP4)
• 1000 SFPS4 (LM1000SFPS4)
• Statistics for 10/100/1000 LSM XMV(R)4/8/12/16, and 10/100/1000 ASM
XMV12X Cards. These cards include the following:
Ixia Platform Reference Guide, Release 6.60 EA Patch1 B-1

B
• 10/100/1000 XMV4/8/12/16, XMVR4/8/12/16 (LSM1000XMV4/8/12/16,
LSM1000XMVR4/8/12/16)
• 10/100/1000 ASM XMV12X
• Statistics for Gigabit Modules. These cards include the following:
• 1000 Base SX MultiMode (LM1000SX)
• 1000 Base SX SingleMode (LM1000SX3)
• GBIC (LM1000GBIC)
• Statistics for OC12c/OC3c Modules. These cards include the following:
• OC12c/OC3c (LMOC12c, LMOC3c)
• Statistics for OC48c Modules with BERT, Statistics for OC48c Modules with
SRP and DCC, and Statistics for OC48c Modules with RPR and DCC. These
cards include the following:
• OC48c POS (LMOC48cPOS, LMOC48cPOS-M)
• OC48 POS VAR (LMOC48VAR)
• OC48c BERT (LMOC48cBERT)
• OC48c BERT Rx
• OC48c POS/BERT (LMOC49POS/BERT)
• Statistics for 2.5G MSM POS modules. These cards include the following:
• 2.5 Gigabit MSM POS OC-48c modules (MSM2.5G1-01)
• Statistics for OC192c Modules with BERT, Statistics for OC192c Modules
with SRP and DCC, and Statistics for OC192c Modules with RPR and DCC.
These cards include the following:
• OC192c with optional BERT and 10 Gigabit Ethernet.
(LMOC192cPOS+BERT, LMOC192cPOS+BERT+WAN)
• OC192c VSR. Note that all VSR cards have available all of the VSR
statistics listed in the VSR section of Table B-6 on page B-25.
(LMOC192cVSR-POS, LMOC192cVSR-BERT, LMOC192cVSR-
POS+BERT)
• Statistics for 10GE Modules with BERT. These cards include the following:
• 10 Gigabit Ethernet with optional BERT. (LM10GELAN, LM10GELAN-
M, LM10GEWAN, LM10GEXAUI+BERT, LM10GEXAUI BERT only,
LM10GEXENPAK+BERT, LM10GEXENPAK-M+BERT,
LM10GEXENPAK BERT only)
• Statistics for 10G UNIPHY Modules with BERT. These cards include the
following:
• 10 Gigabit UNIPHY with optional LAN/WAN, POS and BERT. (LM10G)
• Statistics for 10GE LSM Modules (except NGY). These cards include the
following:
• 10 Gigabit LSM modules using XFP, XENPAK, or X2 carrier cards.
(LSM10GL1-01, LSM10G1-01)
B-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Table Organization
• 10 Gigabit LSM modules supporting MACSec. (LSM10GMS-01)

See also Table B-32 on page B-161 for MACSec statistics.
• 10 Gigabit LSM XL6 modules (for Optixia X16). (LSM10GXL6-01)
• 10 Gigabit LSM XM3, XMR3 (LSM10GXM3, LSM10GXMR3)
• NGY LSM10GXM(R)8(XP)(S)-01, LSM10GXM(R)4(XP)(S)-01,
LSM10GXM2XP-01, LSM10GXMR2(S)-01, LSM10GXM2S-01,
including 10GBASE-T versions LSM10GXM(R)2/4/8GBT-01
• Statistics for NGY Modules. These cards include the following:
• NGY LSM10GXM(R)8(XP)(S)-01, LSM10GXM(R)4(XP)(S)-01,
LSM10GXM2XP-01, LSM10GXMR2(S)-01, LSM10GXM2S-01,
including 10GBASE-T versions LSM10GXM(R)2/4/8GBT-01
• Statistics for 10G MSM modules. These cards include the following:
• 10 Gigabit Ethernet MSM modules. (MSM10G1)
• Statistics for ATM Modules. These include the following:
• ATM 622 Multi-Rate (LM622MR, LM622MR-512)
• Statistics for PoE Modules. These include the following:
• Power over Ethernet (PLM1000T4-PD, LSM1000POE4-02)
• Statistics for 10/100/1000 AFM. These include the following:
• 10/100/1000 AFM Stream Extraction Module. (AFM1000SP-01)
• Statistics for IxNetwork. These statistics are common to all cards that support
IxNetwork.
• Statistics for 1GbE and 10GbE Aggregation Load Modules. These include
the following:
• ASM1000XMV12X-01 (in 1GbE Aggregated Mode or 10GbE
Aggregated Mode)
• ALM, ELM and CPM Statistics. These include the following:
• ALM1000T8, ELM1000ST2, and CPM1000T8-01 load modules
• 40/100 GE Statistics. These include the following:
• 40GE LSM XMV1 and 100GE LSM XMV1 load modules
• Lava 40/100GE load modules
Table Organization
Each of the following tables details the statistics available for that set of cards.
Available statistics are controlled by three sets of controls.
IxExplorer Statistics Modes
From the IxExplorer pane, select a port and select Filter, Statistics, Receive
Mode from the right-hand pane. Select the tab at the top labelled Statistics. This

B Table Organization
is shown here for a Gigabit module with the statistics modes highlighted. The
choices here are mutually exclusive. In most cases, when one is selected new
statistics are available at the expense of others.
Figure B-1. Statistics Mode Selection
Statistics Mode Extra Statistics Check boxes Area
Extra Statistics Check Boxes
Additional statistics are selected through a set of check boxes located on the
same Statistics tab, in the Additional Statistics section. These statistics are
always in addition to those in the Statistics Mode section.
Receive Mode
From the IxExplorer pane, select a port and select Filter, Statistics, Receive
Mode from the right-hand pane. Select the tab at the top labelled Receive Mode.
This is shown here for a 10GE LAN module. The check boxes generally result in
additional statistics.
Figure B-2. Receive Mode Selection

Table Organization
Key to Tables
Table B-1 lists the headings that appear in the tables in this appendix and their
correspondence to IxExplorer dialogs and selections.
Table B-1. Key for Statistics Table
Heading Item IxExplorer Dialog IxExplorer Label
Statistics Mode
UDS 5&6 Statistics User Defined Statistics 5

and 6
QoS Statistics Quality of Service
Normal Statistics Normal
Checksum Errors Statistics IP/TCP/UDP Checksum

Verification
Data Integrity Statistics Data Integrity
Extra Statistics Check

boxes
IxRouter Statistics IxRouter Stats
ARP STATS Statistics ARP Stats
ICMP STATS Statistics ICMP Stats
BGP STATS Statistics BGP Stats
OSPF STATS Statistics OSPF Stats
ISIS STATS Statistics ISIS Stats
RSVP-TE STATS Statistics RSVP-TE Stats
LDP STATS Statistics LDP Stats
POS Ext Statistics POS Extended Stats
DHCPv4 Statistics DHCPv4 Stats
DHCPv6 Statistics DHCPv6 Stats
Temp Sensors Statistics Temperature Sensor

Stats
OAM Stats Statistics Ethernet OAM Stats
PTP Stats Statistics Ptp Stats
Receive Mode
Rx Capture Receive Mode Capture
Rx Seq Checking Receive Mode Sequence Checking
Rx Data Integrity Receive Mode Data Integrity
Rx Packet Group Receive Mode Packet Group

Table B-1. Key for Statistics Table
Heading Item IxExplorer Dialog IxExplorer Label
Rx Mode Bert Receive Mode Mode Bert
Rx Mode ISL Receive Mode Mode ISL
Rx Bert Channelized Receive Mode Bert Channelized
Rx Mode Echo Receive Mode Mode Echo
Rx Mode DCC Receive Mode Mode DCC
Rx Wide Packet Group Receive Mode Wide Packet Groups
Rx Mode PRBS Receive Mode PRBS
Rx Rate Monitoring Receive Mode Rate Monitoring
Rx Per Flow Error Stats Receive Mode Per PGID Checksum

Error Stats
TCL Development Statistics Mode
The statistics mode is controlled by the use of the Tcl stat mode command.
Table B-2 lists the available choices and their correspondence to IxExplorer
choice .
Table B-2. Tcl Stat Mode Options
Option IxExplorer Choice
statNormal (0) (default) Normal
statQos (1) Quality of Service
statStreamTrigger (2) User Defined Statistics 5 and 6
statModeChecksumErrors (3) IP/TC@/UDP Checksum Verification
statModeDataIntegrity (4) Data Integrity
Access to Statistics
Most statistics are accessed through the use of stat command. VSR statistics are
access through the use of the vsrStat command.

Table Organization
Receive Mode
The receive mode is controlled through the use of the port receiveMode option.
The choices available are or’d together and list the bits available to control the
receive mode.
Table B-3. Tcl Port Receive Options
Option IxExplorer Choice
portCapture (1) Capture
portPacketGroup (2) Packet Groups
portRxTcpSessions (4) Does not affect statistics.
portRxTcpRoundTrip (8) Does not affect statistics.
portRxDataIntegrity (16) Data Integrity
portRxFirstTimeStamp (32) Does not affect statistics.
portRxSequenceChecking (64) Sequence Checking
portRxModeBert (128) BERT Mode
portRxModeBertChannelized (128) Channelized BERT Mode
portRxModeIsl ISL Mode
portRxModeEcho Echo Mode
portRxModeDcc DCC Mode
portRxModeWidePacketGroup Wide Packet Groups
portRxModePrbs PRBS Mode
portRxModeRateMonitoring Rate Monitoring
portRxModePerFlowErrorStats Per PGID Checksum Error Stats
C++ Development Statistics Mode
The statistics mode is controlled by the use of the stat.mode member. Table B-1
on page B-4 lists the available choices and their correspondence to IxExplorer
choices and the labels used in the tables in this appendix.
Table B-4. C++ Stat Members
Member Value IxExplorer Choice
statNormal (0) (default) Normal
statQos (1) Quality of Service
statStreamTrigger (2) User Defined Statistics 5 and 6
statModeChecksumErrors (3) IP/TCP/UDP Checksum Verification
statModeDataIntegrity (4) Data Integrity

Access to Statistics
Most statistics are accessed through the use of TCLStatistics class. VSR
statistics are accessed through the use of the TCLvsrStat class.
Receive Mode
The receive mode is controlled through the use of the port.receiveMode

member. The choices available are or’d together and list the bits available to
control the receive mode.
Table B-5. Tcl Port Receive Options
Member Value IxExplorer Choice
portCapture (1) Capture
portPacketGroup (2) Packet Groups
portRxTcpSessions (4) Does not affect statistics.
portRxTcpRoundTrip (8) Does not affect statistics.
portRxDataIntegrity (16) Data Integrity
portRxFirstTimeStamp (32) Does not affect statistics.
portRxSequenceChecking (64) Sequence Checking
portRxModeBert (128) BERT Mode
portRxModeBertChannelized (128) Channelized BERT Mode
portRxModeIsl ISL Mode
portRxModeEcho Echo Mode
portRxModeDcc DCC Mode
portRxModeWidePacketGroup Wide Packet Groups
portRxModePrbs PRBS Mode
portRxModeRateMonitoring Rate Monitoring
portRxModePerFlowErrorStats Per PGID Checksum Error Stats

Description of Statistics
Table B-6 lists all of the available statistics, along with an explanation of those
statistics.The following three columns are used:
• Counter: the name of the statistics as it appears in IxExplorer. These are
organized by general category, as used in the remaining tables in this
appendix.
• Interpretation: the description of the statistics.
• Internal Baseame: the internal basename used to describe the statistics in the
TCL and C++ API. The base name is used to form other names:
• TCL stat command options: the basename is the name of the option.
• TCL stat command get sub-command counterType argument : the
counterType name needed to fetch a particular statistic is formed by
prepending the letters stat to the basename, while capitalizing the first
letter of the statistic. For example, for basename alignmentErrors, the
counterType name is statAlignmentErrors.
• C++ statistic class members: the basename is the name of the member.
• C++ statistic command get method counterType argument: the
counterType name needed to fetch a particular statistic is formed by
prepending the letters stat to the basename, while capitalizing the first
letter of the statistic. For example, for basename alignmentErrors, the
counterType name is statAlignmentErrors.
.
Table B-6. Statistics Counters
Counter Interpretation Internal Basename
Optixia X16 Chassis
Opix Power Supply 1 Status The status of the #1 (left most) power Not available.
supply.
Opix Power Supply 2 Status The status of the #2 power supply. Not available.
Opix Power Supply 1 Current The current of the #1 power supply. This Not available.
should be within 3 amps of other installed
power supplies.
power supplies.
power supplies.

B Description of Statistics
power supplies.
Opix Fan Bank 1 Status The status of the #1 bank of fans, located in Not available.
the fan tray.
the fan tray.
the fan tray.
the fan tray.
Optixia X16 Load Modules A variable number of the statistics in this

category are available for OLM load
modules.
5V Power Status Indicates that the 5VDC bus A rail is on and Not available.
valid.
3.3V Power Status Indicates that the 3.3VDC bus A rail is on Not available.
and valid.
3.3V/5V Power Status Indicates that either the bus A 5VDC or Not available.
3.3VDC rail had an overcurrent event and
shut down.
LM Other Power Output Indicates that power is good for the Not available.
miscellaneous power supplies.
LM 48V Power Output Indicates that the -48VDC input is on. Not available.
LM Temperature 1 Status LM 83 programmable interrupt - over Not available.

temperature alarm.
LM Temperature 2 Status LM 83 critical temperature alarm. Not available.
LM Bus B 5V Power Status Indicates that the 5VDC bus B rail is on and Not available.
valid.
LM Bus B 3.3V Power Status Indicates that the 3.3VDC bus B rail is on Not available.
and valid.
LM Bus B 3.3V/5V Power Status Indicates that either the bus B 5VDC or Not available.
3.3VDC rail had an overcurrent event and
shut down.
LM Temperature Central FPGA Nominal board temperature in area 3. Not available.
LM Temperature LM83 Nominal board temperature in area 1. Not available.
LM Temperature LM87 Nominal board temperature in area 2. Not available.

LM -48VDC Status Indicates that the -48VDC input is in the Not available.
valid input range.
LM System V1 Dependent on each Optixia Load Module. Not available.

Monitors one of several system buses.
LM SMBUS 3.3V Measures the SM bus. This value should Not available.
be 3.3VDC =/- 10%.






User Configurable
User Defined Stats 1 and 2 & Rate Counters that increment each time the userDefinedStat1
statistics conditions are met. The user- userDefinedStat2
defined statistics conditions are set up in
the Capture Filter window.
Capture Trigger (UDS3) & Rate A counter that increments each time the captureTrigger
capture trigger conditions are met, as
defined in the Capture Filter window.
Capture Filter (UDS4) & Rate A counter that increments each time the captureFilter
capture filter conditions are met, as defined
in the Capture Filter window.
User Defined Stats 5 and 6 & Rate Counters that increment each time the streamTrigger1
statistics conditions are met. The user- streamTrigger2
defined statistics conditions are set up in
the Capture Filter window. (N/A to OC192
modules.)
States
Link State ‘Up’ when a link is established with another link

device, ‘Loopback’ when the port has
loopback enabled, ‘Down’ when there is no
connection to another device. (See note 2
in Notes.)

Line Speed ‘10,’ ‘100,’ or ‘1000’ (denoting Mbps) and lineSpeed

OC-12, OC-3 or OC-48 for POS modules.
(See note 6 in Notes.)
Duplex Mode ‘Half’ or ‘Full.’ Half duplex only applies to duplexMode

10/100 Load Modules. (See note 7 in
Notes.)
Transmit State Not shown in IxExplorer. The current transmitState

transmit state of the port. See the stat
command in the Tcl Development Guide
and C++ Development Guide.
Capture State Not shown in IxExplorer. The current captureState

capture state of the port. See the stat
command in the Tcl Development Guide
and C++ Development Guide.
Pause State Not shown in IxExplorer. The current pause pauseState

state of the port. See the stat command in
the Tcl Development Guide and C++
Development Guide.
Common
Frames Sent & Rate A counter that increments only when a framesSent
frame is successfully transmitted. This
counter does not count collision attempts.
Valid Frames Received & Rate The valid frame size is from 64 bytes to framesReceived
1518 bytes inclusive of FCS, exclusive of
preamble and SFD and must be an integer
number of octets. This 32 bit counter only
counts frames with good FCS. VLAN
tagged frames that are greater than 1518
but less than 1522 bytes in size are also
counted by this counter.
Bytes Sent & Rate A counter that counts the total number of bytesSent
bytes transmitted.
Bytes Received & Rate A counter that counts the total number of bytesReceived
bytes received.
Bits Sent & Rate A counter that counts the total number of bitsSent
bits transmitted.
Bits Received & Rate A counter that counts the total number of bitsReceived
bits received.
Scheduled Transmit Time The scheduled transmit time associated scheduledTransmitTime

with the port.
CPU Status The status of the port’s CPU. portCpuStatus
CPU DoD Status The status of the port’s DoD process. portCpuDodStatus

Transmit Duration
Transmit Duration Reserved for future use transmitDuration
Quality of Service
Quality of Service 0 - 7 & Rate Counters which increment each time a qualityOfService0
frame with that particular QoS setting is qualityOfService1
received. ...
(N/A to OC192-3)
Framer Stats
Framer CRC Errors CRC errors detected by the POS framer. framerFCSErrors
Framer Abort POS frames aborted by the Framer. framerAbort
Framer Min Length & Rate POS frames received with less than the framerMinLength
minimum length.
Framer Max Length & Rate POS frames received with more than the framerMaxLength
maximum length.
Extended Framer Stats
Framer Frames Sent Reserved for future use. framerFramesTx
Framer Frames Received Reserved for future use. framerFramesRx
Checksum Stats
IP Packets Received The number of IP packets received. ipPackets
UDP Packets Received The number of UDP packets received. udpPackets
TCP Packets Received The number of TCP packets received. tcpPackets
IP Checksum Errors The number of IP checksum errors ipChecksumErrors

detected.
UDP Checksum Errors The number of UDP checksum errors udpChecksumErrors

detected.
TCP Checksum Errors The number of TCP checksum errors tcpChecksumErrors

detected.
Data Integrity
Data Integrity Frames The number of data integrity frames dataIntegrityFrames

received.
Data Integrity Errors The number of data integrity errors dataIntegrityErrors

detected.
Sequence Checking
Sequence Frames The number of sequence checking frames sequenceFrames

received.

Sequence Errors The number of sequence checking errors sequenceErrors

detected.
Small Sequence Errors The number of times when the current smallSequenceErrors
sequence number minus the previous
sequence number is less than or equal to
the error threshold and not negative, or
when the current sequence number is
equal to the previous sequence number.
Big Sequence Errors The number of times when the current bigSequenceErrors
sequence number minus the previous
sequence number is greater than the error
threshold.
Reverse Sequence Errors The number of times when the current reverseSequenceErrors
sequence number is less than the previous
sequence number.
Total Sequence Errors The sum of the small, bug and reverse totalSequenceErrors
sequence errors.
Packet Group Mode
Packets Skipped In Packet Group The number of packets which were not packetsSkippedIn
Mode assigned to a packet group. This can occur PacketGroupMode
if the packet contains the anticipated packet
group signature, but is too short to hold the
group ID.
IxRouter Stats
General
IxRouter Server Transmit Packets transmitted by the protocol protocolServerTx

handler.
IxRouter Receive Packets received by the protocol handler. protocolServerRx
VLAN Dropped Frames The number of VLAN frames dropped by protocolServerVlan

the IxRouter. DroppedFrames
ARP
Transmit Arp Reply Number of ARP replies generated. txArpReply
Transmit Arp Request Number of ARP requests generated. txArpRequest
Receive Arp Reply Number of ARP replies received. rxArpReply
Receive Arp Request Number of ARP requests received. rxArpRequest
ICMP
Receive Ping Reply Number of Ping replies received. (N/A to rxPingReply

OC192-3)

Receive Ping Request Number of Ping requests generated. (N/A rxPingRequest

to OC192-3)
Transmit Ping Reply Number of Ping replies generated. (N/A to txPingReply

OC192-3)
Transmit Ping Request Number of Ping requests received. (N/A to txPingRequest

OC192-3)
Asynchronous Frames Sent The number of frames sent as a result of asynchronousFramesSent

user request
Scheduled Frames Sent The number of frames originating from the scheduledFramesSent
stream engine.
Port CPU Frames Sent The number of frames originating from the portCPUFramesSent
port’s CPU as opposed to the stream
engine.
DHCPv4
DHCPv4 Discovered Messages Sent The number of Discovered messages sent dhcpV4Discovered
MessagesSent
DHCPv4 Offers Received The number of Offer messages received. dhcpV4OffersReceived
DHCPv4 Requests Sent The number or Request messages sent. dhcpV4RequestsSent
DHCPv4 ACKs Received The number or ACK messages received. dhcpV4AcksReceived
DHCPv4 NACKs Received The number of NACK messages received dhcpV4NacksReceived
DHCPv4 Releases Sent The number of Release messages sent. dhcpV4ReleasesSent
DHCPv4 Enabled Interfaces The number of enabled interfaces. dhcpV4EnabledInterfaces
DHCPv4 Addresses Learned The number of address learned. dhcpV4Addresses

Learned
DHCPv6
DHCPv6 Solicits Sent The number of DHCPv6 Solicits Sent dhcpV6SolicitsSent
DHCPv6 Advertisements Received The number of DHCPv6 Advertisements dhcpV6Advertisements

Received. Received
DHCPv6 Requests Sent The number of DHCPv6 Requests Sent. dhcpV6RequestsSent
DHCPv6 Declines Received The number of DHCPv6 Declines dhcpV6DeclinesSent

Received.
DHCPv6 Replies Received The number of DHCPv6 Replies Received. dhcpV6RepliesReceived
DHCPv6 Releases Sent The number of DHCPv6 Releases Sent. dhcpV6ReleasesSent
DHCPv6 Enabled Interfaces The number of DHCPv6 Enabled dhcpV6EnabledInterfaces

Interfaces.
DHCPv6 Addresses Learned The number of DHCPv6 Addresses dhcpV6Addresses

Learned. Learned

Ethernet OAM Stats
EOAM Information PDUs Sent The number of OAM Information PDUs ethernetOAMInformation
Sent PDUs Sent
EOAM Information PDUs Received The number of OAM Information PDUs ethernetOAMInformation
Received PDUs Received
EOAM Event Notification PDUs The number of OAM Event Notification ethernetOAMEventNotifi
Received PDUs Received cation PDUsReceived
EOAM Loopback Control PDUs The number of OAM Loopback Control ethernetOAMLoopback
Received PDUs Received Control PDUsReceived
EOAM Organization PDUs Received The number of OAM Organization PDUs ethernetOAMOrgPDUs
Received Received
EOAM Variable Request PDUs The number of OAM Variable Request ethernetOAMVariable
Received PDUs Received Request PDUsReceived
EOAM Variable Response PDUs The number of OAM Variable Response ethernetOAMVariable
Received PDUs Received Response PDUsReceived
EOAM Unsupported PDUs Received The number of OAM Unsupported PDUs ethernetOAMUnsupported
Received PDUs Received
BGP
BGP Sessions Configured The number of BGP4 sessions that were bgpTotalSessions
configured.
BGP Sessions Established The number of configured BGP4 sessions bgpTotalSessionsEstab

that established adjacencies. lished
IGMP
Received IGMP Frames The number of IGMP frames received by all rxIgmpFrames
logical hosts after being internally
broadcast (For newer IGMPv3 emulation).
Transmitted IGMP Frames The number of IGMP frames transmitted. txIgmpFrames

(For newer IGMPv3 emulation).
ISIS
ISIS L1 Sessions Configured The total number of level 1 configured isisSessionsConfiguredL1

sessions.
ISIS L2 Sessions Configured The total number of level 2 configured isisSessionsConfiguredL2

sessions.
ISIS L1 Sessions Up The total number of level 1 configured isisSessionsUpL1

sessions that are fully up.
ISIS L2 Sessions Up The total number of level 2 configured isisSessionsUpL2

sessions that are fully up.
MLD

MLD Frames Received The number of MLD frames received by all rxMldFrames
logical hosts after being internally
broadcast.
MLD Frames Transmitted The number of MLD frames transmitted. txMldFrames
OSPF
OSPF Total Sessions The number of OSPF sessions that were ospfTotalSessions
configured.
OSPF Neighbors in Full State The number of OSPF neighbors that are ospfFullNeighbors
fully up.
OSPFv3
OSPFv3 Sessions Configured The number of OSPFv3 sessions that were ospfV3SessionsConfig
configured. ured
OSPFv3 Neighbors in Full State The number of OSPFv3 neighbors that are ospfV3SessionsUp
fully up.
PIM-SM
PIM-SM Routers Configured The number of configured PIM-SM routers. pimsmRoutersConfigured
PIM-SM Routers Running The number of PIM-SM routers in the run pimsmRoutersRunning
state.
PIM-SM Learned Neighbors The number of learned PIM-SM neighbors. pimsmNeighborsLearned
RSVP
RSVP Ingress LSPs Configured The number of ingress LSPs configured. rsvpIngressLSPsConfig
ured
RSVP Ingress LSPs Up The number of ingress LSPs configured rsvpIngressLSPsUp

and running.
RSVP Egress LSPs Up The number of egress LSPs configured and rsvpEgressLSPsUp
running.
LDP
LDP Sessions Configured The number of LDP sessions configured for ldpSessionsConfigured
targeted peers.
LDP Sessions Up The number of LDP sessions configured ldpSessionsUp

and running with targeted peers.
LDP Basic Sessions Up The number of LDP sessions up for ldpBasicSessionsUp

broadcast peers.
Ethernet
Fragments & Rate A counter that counts the number of frames fragments
less than 64 bytes in size with a bad FCS.

Undersize & Rate A counter that counts the number of frames undersize
less than 64 bytes in size with a good FCS.
Oversize & Rate A counter that counts the number of frames oversize
greater than 1518 bytes in size. The
following modules count oversize packets
with both good and bad FCSs: 10/100 TX,
and 10/100 MII. All other modules include
oversize packets with a good FCSs only.
CRC Errors & Rate A counter that counts all valid size frames fcsErrors
that have CRC errors.
Vlan Tagged Frames & Rate A counter that counts the number of VLAN vlanTaggedFrames
tagged frames. Received
Line Errors & Rate A counter that counts the number of 4B/5B symbolErrors
(100Mbps) or 8B/10B (Gigabit) symbol
errors.
Flow Control Frames & Rate A counter that counts the number of flowControlFrames
PAUSE frames received. This counter only
increments when Flow Control is enabled
for that port (using the port properties
dialog).
10/100
Alignment Errors & Rate A counter that counts all frames that are alignmentErrors
not an integer multiple of 8 bits and have
an invalid FCS. The frame is truncated to
the nearest octet and then the FCS is
validated. If the FCS is bad, then this frame
is counted as an alignment error.
Dribble Errors & Rate A counter that counts all frames that are dribbleErrors
not an integer multiple of 8 bits and have a
valid FCS. The frame is truncated to the
nearest octet and then the FCS is
validated. If the FCS is good, then this
frame is counted as a dribble bit error.
Collisions & Rate A counter that counts all occurrences (only collisions
one count per frame or fragment) of the
Collision Detect signal from the physical
layer controller that are not late collisions.
Late Collisions & Rate A counter that counts all collisions that lateCollisions
occur after the 512th bit time (preamble
included) or after the 56th byte.
Collision Frames & Rate A counter that counts the number of frames collisionFrames
that were retransmitted due to one or more
collisions.

Excessive Collision Frames & Rate A counter that counts the number of frames excessiveCollisionFrames
that were attempted to be sent but had 16
or more consecutive collisions.
Gigabit
Oversize and CRC Errors & Rate A counter that counts the number of frames oversizeAndCrcErrors
greater than 1518 bytes in size with a bad
FCS.
Line Error Frames & Rate A counter that counts the number of frames symbolErrorFrames
received that contain symbol errors.
Byte Alignment Error & Rate A counter that counts the number of times synchErrorFrames
that a comma character is detected to be
out of alignment.
POS
Section LOS ‘OK’ or ‘ALARM’ during loss of signal. (See sectionLossOfSignal

note 3 in Notes.)
Section LOF ‘OK’ or ‘ALARM’ during loss of frame. (See sectionLossOfFrame

note 3 in Notes.)
Section BIP(B1) & Rate The number of section bit interleaved parity sectionBip
errors.
Line AIS ‘OK’ or ‘ALARM’ during a line alarm lineAis

indication signal condition. (See note 3 in
Notes.)
Line RDI ‘OK’ or ‘ALARM’ during a remote defect lineRdi

indication. (See note 3 in Notes.)
Line REI(FEBE) & Rate A count of the number of remote error lineRei
indicate conditions.
Line BIP(B2) & Rate The number of line bit interleaved parity lineBip
errors.
Path AIS ‘OK’ or ’ALARM’ during a path alarm pathAis

indication signal condition. (See note 3 in
Notes.)
Path RDI ‘OK’ or ‘ALARM’ during a path remote pathRdi

defect indication. (See note 3 in Notes.)
Path REI(FEBE) & Rate A count of the number of path remote error pathRei
indicate conditions.
Path BIP(B3) & Rate The number of path bit interleaved parity pathBip
errors.
Path LOP ‘OK’ or ‘ALARM’ during a loss of pointer pathLossOfPointer

condition. (See note 3 in Notes.)

Path PLM(C2) Either ‘OK’ or ‘ALARM’ along with the pathPlm

current received path signal label byte.
‘ALARM’ occurs when a path signal label
mismatch occurs. (See note 5 in Notes.)
Section BIP Errored Seconds A count of the number of seconds during sectionBipErroredSecs
which (at any point during the second) at
least one section layer BIP was detected.
Section BIP Severely Errored A count of the number of seconds during sectionBipSeverlyErrored
Seconds which K or more Section layer BIP errors Secs
were detected, where K = 2,392 for OC-48
(per ANSI T1.231-1997).
Section LOS Seconds A count of the number of seconds during sectionLossOfSignalSecs

which (at any point during the second) at
least one section layer LOS defect was
present.
Line BIP Errored Seconds A count of the seconds during which (at any lineBipErroredSecs
point during the second) at least one Line
layer BIP was detected.
Line REI Errored Seconds A count of the seconds during which at lineReiErroredSecs
least one line BIP error was reported by the
far end.
Line AIS Alarmed Seconds A count of the seconds during which (at any lineAisAlarmSecs
point during the second) at least one Line
layer AIS defect was present.
Line RDI Unavailable Seconds A count of the seconds during which the lineRdiUnavailableSec
line is considered unavailable at the far
end.
Path BIP Errored Seconds A count of the seconds during which (at any pathBipErroredSecs
point during the second) at least one Path
BIP error was detected.
Path REI Errored Seconds A count of the seconds during which (at any pathReiErroredSecs
point during the second) at least one STS
Path error was reported by the far end.
Path AIS Alarmed Seconds A count of the seconds during which (at any pathAisAlarmSec
point during the second) an AIS defect was
present)
Path AIS Unavailable Seconds A count of the seconds during which the pathAisUnavailableSecs
STS path was considered unavailable.
Path RDI Unavailable Seconds A count of the seconds during which the pathRdiUnavailableSec
STS path was considered unavailable at
the far end.
Input Signal Strength (dB) (OC-192) This statistic monitors the receive inputSignalStrength
optical input power. (See note 8 in Notes)

POS K1 Byte Monitors the k1 status byte in SONET posK1byte

Headers.
POS K2 Byte Monitors the k1 status byte in SONET posK2byte

Headers.
SRP
SRP Data Frames Received The number of data frames received. IPv4 srpDataFramesReceived
frames fall in this category.
SRP Discovery Frames Received The number of discovery type frames srpDiscoveryFrames
received. Received
SRP IPS Frames Received The number of IPS type frames received. srpIpsFramesReceived
SRP Header Parity Errors The number of SRP frames received with srpParityErrors
SRP header parity error. This includes all
frame types.
SRP Usage Frames Received The number of usage frames received with srpUsageFrames
good CRC, good header parity, and only Received
those that match the MAC address set for
the SRP’s port. Bad CRC frames, frames
with header errors or those with other MAC
addresses are received but not counted.
SRP Usage Frames Sent The number of usage frames sent.These srpUsageFramesSent
are sent periodically to keep the link alive.
SRP Usage Status If the number of consecutive timeouts srpUsageStatus

exceeds the Keep Alive threshold, this
status changes to FAIL. Otherwise shows
OK.
SRP Usage Timeouts The number of times a usage frame was srpUsageTimeouts
not received within the time period.
RPR
RPR Discovery Frames Received The number of RPR discovery frames rprDiscoveryFrames
received. Received
RPR Data Frames Received The number of RPR encapsulated data rprDataFramesReceived
frames received.
RPR Fairness Frames Received The number of RPR fairness frames rprFairnessFrames
received. Received
RPR Fairness Frames Sent The number of RPR fairness frames sent. rprFairnessFramesSent
RPR Timeout Events The number of timeouts that occurred rprFairnessTimeouts

waiting for RPR fairness frames.
RPR Header CRC Errors The number of RPR frames received with rprHeaderCrcErrors
header CRC errors.
RPR OAM Frames Received The number of RPR OAM frames received. rprOamFramesReceived

RPR Payload CRC Errors The number of RPR frames received with rprPayloadCrcErrors
payload CRC errors.
RPR Protection Frames Received The number of RPR protection frames rprProtectionFrames
received. Received
RPR Idle Frames Received The number or RPR idle frames received. rprIdleFramesReceived
GFP
GFP Idle Frames The number of GFP idle frames received. gfpIdleFrames
GFP Sync State The GFP sync state. gfpSyncState
GFP SYNC/HUNT Transitions The number of Sync/Hunt state transition gfpSyncHuntTransitions

frames received.
GFP eHEC Errors Number of GFP extension header HEC gfpeHecErrors

errors detected.
GFP Payload FCS Errors Number of payload FCS errors detected. gfpPayloadFcsErrors
GFP Receive Bandwidth The measured receive GFP bandwidth, in gfpRxBandwidth

Mbps.
GFP tHEC Errors Number of GFP type header HEC errors gfptHecErrors
detected.
BERT
BERT Status For BERT: The status of the connection. bertStatus

‘Locked’ when the receiving interface locks
onto the data pattern. (See note 1 in Notes)
BERT Bits Sent For BERT, it is the total number of bits sent. bertBitsSent
BERT Bits Received For BERT, it is the total number of bits bertBitsReceived
received.
BERT Bit Errors Sent For BERT, it is the total number of bit errors bertBitErrorsSent
sent.
BERT Bit Errors Received For BERT, it is the total number of bit errors bertBitErrorsReceived
received.
BERT Bit Error Ratio For BERT, it is the ratio of the number of bertBitErrorRatio
errored bits compared to the total number
of bits transmitted.
BERT Errored Blocks For BERT—(EB) Number of blocks bertErroredBlocks

containing at least one errored second.
BERT Errored Seconds For BERT—(ES) Number of seconds bertErroredSeconds

containing at least one errored block or a
defect.
BERT Errored Second Ratio For BERT—(ESR) the ratio of Errored bertErroredSecondRatio
Seconds (ES) to the total seconds.

BERT Severely Errored Seconds For BERT—(SES) Number of seconds with bertSeverelyErrored
30% or more of the errored blocks or a Seconds
defect.
BERT Severely Errored Second For BERT—(SESR) the ratio of Severely bertSeverelyErrored
Ratio Errored Seconds (SESs) to the total SecondsRatio
seconds in available time.
BERT Error Free Seconds For BERT—(EFS) Number of seconds with bertErrorFreeSeconds
no errored blocks or defects.
BERT Available Seconds For BERT—(AS) Number of seconds which bertAvailableSeconds

have occurred during Available Periods.
BERT Unavailable Seconds For BERT—(UAS) Number of seconds bertUnavailableSeconds

which have occurred during Unavailable
Periods.
BERT Block Error State For BERT—Available Period or Unavailable bertBlockErrorState

Period, determined according to the
running count and calculation of seconds in
various error conditions. A min. of 10 non-
SESs must pass for the state to change
from Unavailable to Available. A min. of 10
SESs must pass for the state to change
from Available to Unavailable. (See note 4
in Notes.)
BERT Background Block Errors For BERT—(BBE) The number of errored bertBackgroundBlock
blocks not occurring as part of a Severely Errors
Errored Second.
BERT Background Block Error Ratio For BERT—(BBER) the ratio of bertBackgroundBlockError
Background Block Errors (BBEs) to the Ratio
total number of blocks in available time.
BERT Elapsed Test Time For BERT—the elapsed test time, bertElapsedTestTime
expressed in seconds.
BERT Number Mismatched Zeros The number of expected zeroes received bertNumberMismatched
as ones. Zeros
BERT Mismatched Zeros Ratio The ratio of the number of expected zeroes bertismatchedZerosRatio
received as ones to all bits.
BERT Number Mismatched Ones The number of expected ones received as bertNumberMismatched
zeroes. Ones
BERT Mismatched Ones Ratio The ratio of the number of expected ones bertMismatchedOnes
received as zeroes to all bits. Ratio

Service Disruption A service disruption is the period of time

during which the service is unavailable
while switching rings. The SONET spec
calls for this to be less than 50 ms.
Last Service Disruption Time (ms) The length of the last service disruption that bertLastServiceDisruption
occurred, expressed in milliseconds. Time
Min Service Disruption Time (ms) The shortest service disruption that bertMinServiceDisruption
Max Service Disruption Time (ms) The longest service disruption that bertMaxServiceDisruption
Cumulative Service Disruption Time The total service disruption time bertServiceDisruption
(ms) encountered, expressed in milliseconds. Cumulative
DCC
DCC Bytes Received The number of DCC bytes received. dccBytesReceived
DCC Bytes Sent The number of DCC bytes sent. dccBytesSent
DCC CRC Receive Errors The number of DCC CRC errors received. dccCrcErrorsReceived
DCC Frames Received The number of DCC frames received. dccFramesReceived
DCC Frames Sent The number of DCC frames sent. dccFramesSent
DCC Framing Errors Received The number of DCC framing errors dccFramingErrors
received. Received
Link Fault Signalling
Insertion State The current state of link fault insertion. 0 = insertionState

not inserting, 1 = inserting.
Link Fault State The current state of link fault detection on a linkFaultState
port. 0 = no fault, 1 = local fault, 2 = remote
fault.
Local Faults The number of local faults detected. localFaults
Remote Faults The number of remote faults detected. remoteFaults
CDL Converged Data Layer
CDL Error Frames Received The number of CDL error frames received. cdlErrorFramesReceived
CDL Good Frames Received The number of good CDL frames received. cdlGoodFramesReceived.
FEC Forwarding Error Correction
FEC Corrected 0s Count Number of 0 errors (1s changed to 0s) that fecCorrected0sCount
have been corrected.
FEC Corrected 1s Count Number of 1 errors (0s changed to 1s) that fecCorrected1sCount
have been corrected.

FEC Corrected Bits Count Number of flipped bits errors (0s changed fecCorrectedBitsCount
to 1s and vice versa) that have been
corrected.
FEC Corrected Bytes Count Number of bytes that have had errors fecCorrectedBytesCount
corrected.
FEC Uncorrectable Subrow Count Number of subrows that have had fecUncorrectableSubrow
uncorrectable errors. Count
OC192
Temperature
DMA Chip Temperature (C) (OC-192 - Temperature Sensors Stats) dMATemperature

Temperature of the DMA chip.
Capture Chip Temperature (C) (OC-192 - Temperature Sensors Stats) captureTemperature

Temperature of the Capture chip.
Latency Chip Temperature (C) (OC-192 - Temperature Sensors Stats) latencyTemperature

Temperature of the Latency chip.
Background Chip Temperature (C) (OC-192 - Temperature Sensors Stats) backgroundTemperature

Temperature of the Background chip.
Overlay Chip Temperature (C) (OC-192 - Temperature Sensors Stats) overlayTemperature

Temperature of the Overlay chip.
Front End Chip Temperature (C) (OC-192 - Temperature Sensors Stats) frontEndTemperature
Temperature of the Front End Chip.
Scheduler Chip Temperature (C) (OC-192 - Temperature Sensors Stats) scheduleTemperature

Temperature of the Scheduler Chip.
Plm Internal Chip Temperature 1 (C) (OC-192 - Temperature Sensors Stats) plmDevice1Internal
Internal temperature of temperature Temperature
measuring device #1.
Plm Internal Chip Temperature 2 (C) (OC-192 - Temperature Sensors Stats) plmDevice2Internal
Plm Internal Chip Temperature 3(C) (OC-192 - Temperature Sensors Stats) plmDevice3Internal
Fom Port Temperature (C) (OC-192 - Temperature Sensors Stats) fobPort1FpgaTemperature

Temperature for one of the sensors on the fobPort2FpgaTemperature
Fiber optic module (Fom).
Fom Board Temperature (C) (OC-192 - Temperature Sensors Stats) fobBoardTemperature

Temperature for one of the sensors on the
Fom Internal Temperature (C) (OC-192 - Temperature Sensors Stats) fobDevice1Internal

Temperature for one of the sensors on the Temperature

VSR The statistics in this sub-section relate to all

VSR channels. See VSR per Channel
statistics for further per-channel statistics.
Rx Channel Protection Disabled The status of the channel protection on the rxChannelProtection
receiving interface. Disabled8
Rx Channel Skew Error The status of the channel skew error rxChannelSkewError8
detection on the receiving interface.
RX Channel Skew First The channel number of the earliest channel rxChannelSkewFirst8
to arrive on the receiving interface. If more
than one channel arrives at the same time,
Channel #1 has the highest priority and so
on.
Rx Channel Skew Last The channel number of the latest channel rxChannelSkewLast8
to arrive on the receiving interface. If more
than one channel arrives at the same time,
Channel #1 has the highest priority, and so
on.
Rx Channel Skew Max This counter increments every time the rxChannelSkewMax8
channel skew is equal to or greater than the
maximum channel skew.
Rx Channel Swapped Indicates one or more channel swap errors. rxChannelSwapped8
Rx Code Word Violation Error Indicates one or more 8b/10b code word rxCodeWordViolation
violation errors. Error8
Rx CRC Corrected Errors The number of corrected CRC block errors rxCrcCorrectedError
accumulated on the receiving interface. Counter8
Rx CRC Correction Disabled Indicates the status of the CRC correction rxCrcCorrectionDisabled8
on the receiving interface.
Rx CRC Error Indicates one or more detected CRC rxCrcError8

errors.
Rx CRC Uncorrected Errors The number of uncorrected CRC block rxCrcUnCorrectedError

errors accumulated on the receiving Counter8
interface.
Rx Hardware Error The number of hardware errors detected on rxHardwareError8

the receive side.
Rx Loss Of Synchronization Counter Indicates the number of times that a rxLossOfSynchronization

protection channels was in the loss of Counter8
synchronization state.
Rx Multi-loss Of Synchronization Indicates the number of times that two or rxMultiLossOfSynchroniza

Counter more data or protection channels were in tionCounter8
the Loss of Synchronization state.

Rx Multi-loss Of Synchronization Indicates that two or more data or rxMultiLossOfSynchroniza

Status protection channels are in the Loss of tionStatus8
Synchronization state.
Rx Out of Frame Counter Indicates the number of frame errors for the rxOutOfFrameCounter8
receiving interface.
Rx Out of Frame Status Indicates one or more out of frame errors rxOutOfFrameStatus8
for the receiving interface.
Rx Section BIP Error Counter The number of Section BIP errors detected rxSectionBipError
on the receiving interface. Counter8
Tx Hardware Error Counter The number of hardware errors detected on txHardwareError8

the transmit side.
Tx Out Of Frame Counter The number of out of frame errors detected txOutOfFrameCounter8
on the transmit side.
Tx Out of Frame Status Indicates one or more out of frame errors txOutOfFrameStatus8
for the transmit interface.
Tx Section BIP Error Counter The number of Section Bit Interleaved txSectionBipError
Parity (BIP) errors which have been Counter8
detected on the transmit interface.
VSR per Channel The statistics in this sub-section relate to a

specific VSR channel.
Rx Code Word Violation Counter This per-channel statistic indicates the rxCodeWordViolation
number of codeword violations detected on Counter9
the receiving channel interface. Codeword
violations include running disparity errors,
undefined codewords, and any control
characters besides K28.5.
Rx CRC Error Counter This per-channel statistic indicates the rxCrcErrorCounter9

number of corrected and uncorrected errors
on the receive interface.
Rx Loss Of Synchronization Status This per-channel statistic indicates the loss rxLossOfSynchronization9
of synchronization status of the receiving
interface.
Rx Out of Frame Status This per-channel statistic indicates the out rxOutOfFrame9
of frame status of the receiving interface for
a particular channel.
10 Gig
LSM
Local Ordered Sets Sent The number of local ordered sets sent. localOrderedSetsSent
Ordered sets are part of Link Fault
Signaling, and can be configured in the Link
Fault Signaling tab.

Local Ordered Sets Received The number of local ordered sets received. localOrderedSets
Ordered sets are part of Link Fault Received
Remote Ordered Sets Sent The number of remote ordered sets remoteOrderedSetsSent
sent.Ordered sets are part of Link Fault
Remote Ordered Sets Received The number of remote ordered sets remoteOrderedSets
received.Ordered sets are part of Link Fault Received
Custom Ordered Sets Sent The number of custom ordered sets customOrderedSetsSent
sent.Ordered sets are part of Link Fault
Custom Ordered Sets Received The number of custom ordered sets customOrderedSets
received.Ordered sets are part of Link Fault Received
Frames Received with Coding Errors The number of frames received with coding codingErrorFrames
errors. Received
Frames Received with /E/ error The number of frames received with DUT eErrorCharacterFrames
Character labeled errors received. Received
Dropped Frames The number of dropped frames. droppedFrames
Pause Frame
Pause Acknowledge The number of clocks for which transmit pauseAcknowledge

has been paused.
Pause End Frames The number of pause frames received with pauseEndFrames
a quanta of 0.
Pause Overwrite The number of pause frames received pauseOverwrite

while transmit was paused with a quanta
not equal to 0.
Temperature
Lan Transmit FPGA Temperature For the 10Gig LAN board, the temperature 10GigLanTxFpga
at the transmit FPGA. Temperature
Lan Receive FPGA Temperature For the 10Gig LAN board, the temperature 10GigLanRxFpga
at the receive FPGA. Temperature
ATM and ATM/POS
ATM AAL5 Bytes Received The number of AAL5 bytes received. atmAal5BytesReceived
ATM AAL5 Bytes Sent The number of AAL5 bytes sent. atmAal5BytesSent

ATM AAL5 CRC Error Frames The number of AAL5 frames received with atmAal5CrcErrorFrames
CRC errors.
ATM AAL5 Frames Received The number of AAL5 frames received. atmAal5FramesReceived
ATM AAL5 Frames Sent The number of AAL5 frames sent. atmAal5FramesSent
ATM AAL5 Length Error Frames The number of AAL5 frames received with atmAal5LengthError
length errors. Frames
ATM AAL5 Timeout Error Frames The number of AAL5 frames received with atmAal5TimeoutError
timeout errors. Frames
ATM Cells Received The number of ATM cells received. atmCellsReceived
ATM Cells Sent The number of ATM cells sent. atmCellsSent
ATM Corrected HCS Error Count The number of AAL5 frames received with atmCorrectedHcsError
HCS errors that were corrected. Count
ATM Idle Cell Count The number of idle ATM cells sent. atmIdleCellCount
ATM Scheduled Cells Sent The number of scheduled (non-idle) ATM atmScheduledCellsSent
cells sent.
ATM Uncorrected HCS Error Count The number of AAL5 frames received with atmUncorrectedHcsError
HCS errors that were not corrected. Count
ATM Unregistered Cells The number of unregistered ATM cells that atmUnregisteredCells
were received. Received
OAM Tx Cells Number of ATM OAM cells transmitted. atmOamTxCells
OAM Tx Bytes Number of ATM OAM bytes transmitted. atmOamTxBytes
OAM Tx Fault Management AIS Number of ATM OAM Fault Management atmOamTxFaultMgmtAIS
AIS cells transmitted.
OAM Tx Fault Management RDI Number of ATM OAM Fault Management atmOamTxFaultMgmtRDI
RDI cells transmitted.
OAM Tx Fault Management CC Number of ATM OAM Fault Management atmOamTxFaultMgmtCC

CC cells transmitted.
OAM Tx Fault Management LB Number of ATM OAM Fault Management atmOamTxFaultMgmtLB

LB cells transmitted.
OAM Tx Fault ActDeact CC Number of ATM OAM ActDeact cells atmOamTxActDeactCC

transmitted.
OAM Rx Good Cells Number of ATM OAM good cells received. atmOamRxGoodCells
OAM Rx Bytes Number of ATM OAM bytes received. atmOamRxBytes
OAM Rx Fault Management AIS Number of ATM OAM Fault Management atmOamRxFaultMgmtAIS
AIS cells received.
OAM Rx Fault Management RDI Number of ATM OAM Fault Management atmOamRxFaultMgmtRDI
RDI cells received.

OAM Rx Fault Management CC Number of ATM OAM Fault Management atmOamRxFaultMgmtCC

CC cells received.
OAM Rx Fault Management LB Number of ATM OAM Fault Management atmOamRxFaultMgmtLB

LB cells received.
OAM Rx Bad Cells Number or ATM OAM bad cells received. atmOamRxBadCells
OAM Rx ActDeact CC Number of ATM OAM ActDeact cells atmOamRxActDeactCC

transmitted.
Ethernet CRC The Ethernet CRC, representing AAL5 ethernetCrc

CRCs.
Power Over Ethernet
PoE Status The PoE status. poeStatus
PoE Input Voltage The PoE input voltage. poeInputVoltage
PoE Input Current The PoE input current. poeInputCurrent
PoE Input Power The PoE input power. poeInputPower
PoE Amplitude Arm Status The state of the current signal acquisition poeAmplitudeArmStatus
arming for amplitude measurements.
PoE Amplitude Done Status Indicates whether the signal acquisition of poeAmplitudeDoneStatus
the amplitude measurement has occurred.
PoE Amplitude Time Status The state of the current signal acquisition poeTimeArmStatus
arming for time measurements.
PoE Amplitude Time Status Indicates whether the signal acquisition of poeTimeDoneStatus
the time measurement has occurred.
PoE Trigger Amplitude DC Amps The DC amps of the measured PoE poeTriggerAmplitudeDC
amplitude measurements. Amps
PoE Trigger Amplitude DC Volts The DC voltage of the measured PoE poeTriggerAmplitudeDC
amplitude measurements. Volts
PoE Active Input Displays the type of PSE in use, Alt. A or poeActiveInput
Alt B.
PoE Temperature The temperature of the PoE port, in poeTemperature

Celsius.
PoE AutoCalibration The stage in the port diagnostic test. poeAutocalibration
Stream Extraction Module
Bytes from Application The number of bytes received on either port bytesFromApplication
2 or 3 from the application.
Packets from Application The number of packets received on either packetsFromApplication

port 2 or 3 from the application.

Bytes from Port 2 The number of bytes received on the monitorBytesFromPort2

monitor port from port 2.
Bytes from Port 3 The number of bytes received on the monitorBytesFromPort3

Packets from Port 2 The number of packets received on the monitorPacketsFromPort2

Packets from Port 3 The number of packets received on the monitorPacketsFromPort3


Notes
Table B-7. Notes for Statistics Counters
NOTE Choices Displayed for Statistic
1 Locked - All Ones
Locked - Inverted Alternating One/Zero
Locked - Inverted User Defined Pattern
Locked - Inverted 2^31 Linear Feedback Shift Reg
Locked - All Zero
Locked - Alternating One/Zero
Locked - User Defined Pattern
Locked - 2^11 Linear Feedback Shift Reg
Not Locked
2 Demo Mode
Link Up
Link Down
Loopback
WriteMii
Restart AutoNegotiate
End RestartAutoNegotiate
AutoNegotiate
WriteMii Failed
No Transceiver
Invalid PHY Address
Read LinkPartner
No LinkPartner
FPGA Download Failed

Table B-7. Notes for Statistics Counters
No GBIC Module
Fifo Reset
Fifo Reset Compete
PPP Off
PPP Up
PPP Down
PPP Init
PPP WaitForOpen
PPP AutoNegotiate
PPP Close
PPP Connect
Loss of Frame
Loss of Signal
StateMachine Failure
PPP RestartNegotiation
PPP RestartNegotiation Init
PPP RestartNegotiation WaitForOpen
PPP RestartNegotiation WaitForClose
PPP RestartNegotiation Finish
LP Boot Failed
PPP Disabled - LOF
Ignore Link
Temperature Alarm
PPP Closing
PPP LCP Negotiate
PPP Authenticate
PPP NCP Negotiate
3 OK
Alarm
‘-’
Defect

B
B-34 Table B-7. Notes for Statistics Counters
4 Unavailable Period
Available Period
5 OK
OK (%)
Alarm (%)
‘-’
6 OC-3c
OC-12c
OC-48c
Ixia Platform Reference Guide, Release 6.60 EA Patch1
OC-192c
10GE WAN
10 Mbps
100 Mbps
1000 Mbps
7 Full
Half
8 Loss of Signal
[-] %d.%d
B
B-35 Table B-7. Notes for Statistics Counters
8 The statistics in this section must be accessed using the vsrStat

command in TCL and the TCLvsrStat class in C++.
9 The statistics in this section must be accessed using the vsrStat

command in TCL and the TCLvsrStat class in C++. In addition, the
desired channel must be set with the getChannel sub-command (TCL)
or method (C++).
Table B-8. Statistics for 10/100 Cards

Normal Qos StreamTrigger
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
PacketGroup
PacketGroup
Capture
Capture
Capture
Type: User Configurable
UserDefinedStat1 X X X X X X X X
CaptureTrigger X X X X
CaptureFilter X X X X
StreamTrigger1 X
StreamTrigger2 X
Type: States
Link X X X X X X X X X
LineSpeed X X X X X X X X X
DuplexMode X X X X X X X X X
TransmitState X X X X X X X X X
B
B-36 Table B-8. Statistics for 10/100 Cards
Normal Qos StreamTrigger
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
PacketGroup
PacketGroup
Capture
Capture
Capture
CaptureState X X X X X X X X X
PauseState X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X
FramesReceived X X X X X X X X X
BytesSent X X X X X X X X X
BytesReceived X X X X X X X X
FcsErrors X X X X X X X X X
BitsReceived X X X X X X X X
BitsSent X X X X X X X X X
PortCpuStatus
PortCpuDodStatus
Type: Transmit Duration
TransmitDuration X X X X X X X
Type: Quality of Service
QualityOfService0 X
Type: Ethernet
Fragments X X X X X X X X X
Undersize X X X X X X X X X
Oversize X X X X X X X X X
VlanTaggedFramesRx X X X
FlowControlFrames X X X X X X X X X
Type: 10/100
AlignmentErrors X X X X X X X X X
Table B-9.
UserDefinedStat2
UserDefinedStat1
X
X
Capture
X
X
PacketGroup
Normal
X
X
RxTcpRoundTrip
Table B-8.
Collisions
X
X
RxDataIntegrity
DribbleErrors
SymbolErrors
LateCollisions
Statistics for 10/100 TXS Modules

CollisionFrames
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
OversizeAndCrcErrors
Type: 10/100 + Gigabit
X
X
RxModeWidePacketGroup
ExcessiveCollisionFrames
Capture
X
X
X
X
X
X
Capture
Qos
PacketGroup
Normal
RxFirstTimeStamp
Statistics for 10/100 Cards
X
X
X
X
X
PacketGroup
X
X
Capture
X
X
X
X
X
RxTcpRoundTrip
X
X
PacketGroup
X
X
RxTcpRoundTrip
X
X
RxDataIntegrity
X
X
X
X
X
RxFirstTimeStamp
StreamTrigger
X
X RxFirstTimeStamp
X
X
RxSequenceChecking
X
X
X
X
Capture
Qos
X
X
s
Capture
X
X
X
X
X
Capture
X
PacketGroup
X
X
RxDataIntegrity
X
X
X
X
X
PacketGroup
X
RxFirstTimeStamp
StreamTrigger
X
X
RxSequenceChecking
ModeChecksumError
X
X
X
X
X
RxModeWidePacketGroup RxTcpRoundTrip
X
X
Capture
X
X
PacketGroup
X
X
X
X
X
RxFirstTimeStamp
X
X
RxDataIntegrity
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
ModeDataIntegrity
X
X
Description of Statistics B
B
B-38 Table B-9. Statistics for 10/100 TXS Modules
Normal Qos StreamTrigger ModeChecksumError ModeDataIntegrity
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
CaptureTrigger X X X X X X X X X X X X X X X X X X
CaptureFilter X X X X X X X X X X X X X X X X X X
StreamTrigger1 X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X X
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X

QualityOfService0 X X X X
Type: Checksum Stats
IpPackets X X X X
UdpPackets X X X X
TcpPackets X X X X
IpChecksumErrors X X X X
UdpChecksumErrors X X X X
TcpChecksumErrors X X X X
Type: Data Integrity
DataIntegrityFrames X X X X
DataIntegrityErrors X X X X
Type: Sequence
Checking
SequenceFrames X X X X
SequenceErrors X X X X
Type: Ethernet
Fragments X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
Undersize X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Oversize X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
VlanTaggedFramesRx X X X X X X X X X X
FlowControlFrames X X X X X X X X X X X X X X X X X X
Type: 10/100
AlignmentErrors X X X X X X X X X X
DribbleErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Collisions X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LateCollisions X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CollisionFrames X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
ExcessiveCollisionFrames X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
SymbolErrors
OversizeAndCrcErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Table B-10. Statistics for 10/100/1000 TXS, 10/100/1000 XMS(R)12, 1000 SFPS4, and 1000STXS24 Cards
Statistics Mode Normal Qos StreamTrigger ModeChecksum ModeData
Errors Integrity
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
Type: User
Configurable
UserDefinedStat1 X X X X X X X X X X X X X X X X X X X X
UserDefinedStat2 X X X X X X X X X X X X X X X X X X
CaptureTrigger X X X X X X X X X X X X X X
CaptureFilter X X X X X X X X X X X X X X
StreamTrigger1 X X
StreamTrigger2 X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X X X X X X X X X X X X X X X X X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X
B-41
BytesSent X X X X X X X X X X X X X X X X X X X X X X X
B
B-42 Table B-10. Statistics for 10/100/1000 TXS, 10/100/1000 XMS(R)12, 1000 SFPS4, and 1000STXS24 Cards
Errors Integrity
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
BytesReceived X X X X X X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X
PortCpuDodStatus X X X X X X
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X
QualityOfService0 X X X
IPv4Packets X X
UdpPackets X X
TcpPackets X X
IPv4ChecksumErrors X X
UdpChecksumErrors X X
TcpChecksumErrors X X
Errors Integrity
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
Type: Sequence
Checking
Type: Ethernet
Fragments X X X X X X X X X X X X X X X X X X X X X X X
Undersize X X X X X X X X X X X X X X X X X X X X X X X
Oversize X X X X X X X X X X X X X X X X X X X X X X X
VlanTaggedFramesRx X X X X X X X X
FlowControlFrames X X X X X X X X X X X X X
Type: 10/100
AlignmentErrors X X
DribbleErrors X X X X X X
Collisions X X X X X X
LateCollisions X X X X X X
CollisionFrames X X X X X X
ExcessiveCollisionFrame X X X X X X
s
Type: Gigabit
SymbolErrorFrames X X X X X X X X X X X X X X X
B-43
SynchErrorFrames X X X X X X X X
Table B-11.
SymbolErrors
Receive Mode
Receive Mode
Statistics Mode
Statistics Mode
UserDefinedStat2
UserDefinedStat1

X
X
Capture
X
X
Capture
X
X
PacketGroup
X
X
PacketGroup
Normal
Normal
X
RxDataIntegrity
X
X
RxDataIntegrity
X
RxSequenceChecking
X
X
RxSequenceChecking
X
X
X
X
Capture
Capture
Qos
PacketGroup
Qos
PacketGroup
X
X
Capture
X
X
Capture
X
X
PacketGroup
X
X
PacketGroup
X
RxDataIntegrity
X
X
RxDataIntegrity
X
RxSequenceChecking
StreamTrigger
X
X
RxSequenceChecking
StreamTrigger
X
X
X
X
Capture
X
X
Capture
X
X
PacketGroup
Errors
X
X
PacketGroup
X
RxDataIntegrity
Integrity
X
X
RxDataIntegrity
ModeData
X
RxSequenceChecking
X
X
RxSequenceChecking
ModeChecksum
Statistics for 10/100/1000 LSM XMV(R)4/8/12/16, and 10/100/1000 ASM XMV12X Cards
X
X
X
X
X
Capture
X
X
PacketGroup
Integrity
RxDataIntegrity
ModeData
RxSequenceChecking
X
Table B-11. Statistics for 10/100/1000 LSM XMV(R)4/8/12/16, and 10/100/1000 ASM XMV12X Cards
Statistics Mode Normal Qos StreamTrigger ModeData
Integrity
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
UserDefinedStatNByteCou X X X X X X X X X X X X X X X
nt1
(supported only on
ASM1000XMV12X
UserDefinedStatNByteCou X X X X X X X X X X X X X X X
nt2
(supported only on
ASM1000XMV12X
CaptureTrigger X X X X X X X X X X
CaptureFilter X X X X X X X X X X
StreamTrigger1 X X
StreamTrigger2 X X
Type: States
Link X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X
DuplexMode X X X X X X X X X X X X X X X X X X
TransmitState X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X
B-45
FramesReceived X X X X X X X X X X X X X X X X X X
B
B-46 Table B-11. Statistics for 10/100/1000 LSM XMV(R)4/8/12/16, and 10/100/1000 ASM XMV12X Cards
Integrity
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
BytesSent X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X
PortCpuDodStatus X X X X X
TransmitDuration X X X X X X X X X X X X X X X X X X
QualityOfService0 X X X
IPv4Packets X X X X X X X X X X X X X X X X X X
UdpPackets X X X X X X X X X X X X X X X X X X
TcpPackets X X X X X X X X X X X X X X X X X X
IPv4ChecksumErrors X X X X X X X X X X X X X X X X X X
UdpChecksumErrors X X X X X X X X X X X X X X X X X X
TcpChecksumErrors X X X X X X X X X X X X X X X X X X
DataIntegrityFrames X X X
Table B-11. Statistics for 10/100/1000 LSM XMV(R)4/8/12/16, and 10/100/1000 ASM XMV12X Cards
Integrity
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
DataIntegrityErrors X X X
Type: Sequence
Checking
SequenceFrames X X X
SequenceErrors X X X
Type: Ethernet
Fragments X X X X X X X X X X X X X X X X X X
Undersize X X X X X X X X X X X X X X X X X X
Oversize X X X X X X X X X X X X X X X X X X
VlanTaggedFramesRx X X X X X X X
FlowControlFrames X X X X X X X X X X X X
Type: 10/100
AlignmentErrors X X
DribbleErrors X X X X X
Collisions X X X X X
LateCollisions X X X X X
CollisionFrames X X X X X
ExcessiveCollisionFrames X X X X X
Type: Gigabit
B-47
SymbolErrorFrames X X X X X X X X X X X X
UserDefinedStat1
X
Capture
X
PacketGroup
Normal
X
RxTcpRoundTrip
Table B-12. Statistics for Gigabit Modules

Table B-11.
X
RxDataIntegrity
SymbolErrors
Receive Mode
Statistics Mode
X
RxFirstTimeStamp
SynchErrorFrames
X
RxSequenceChecking
X
Capture
X
X
X
Capture
Qos
PacketGroup
X
X
X
PacketGroup
Normal
RxFirstTimeStamp
X
RxDataIntegrity
X
RxSequenceChecking
X
Capture
X
X
PacketGroup
X
X
Capture
X
Qos
RxTcpRoundTrip
X
PacketGroup
X
RxDataIntegrity
StreamTrigger
X
X
RxFirstTimeStamp
X
X
X Capture
RxSequenceChecking
X
X
X
PacketGroup
X
X
RxDataIntegrity
s
Capture
X
RxSequenceChecking
StreamTrigger
PacketGroup
X
X
RxDataIntegrity
X
X
X
Capture
X
RxFirstTimeStamp
X
X
X
PacketGroup
X
RxSequenceChecking
Integrity
RxDataIntegrity
ModeData
ModeChecksumError
X
RxSequenceChecking
Statistics for 10/100/1000 LSM XMV(R)4/8/12/16, and 10/100/1000 ASM XMV12X Cards
Capture
X
X
PacketGroup
X
RxDataIntegrity
X
RxFirstTimeStamp
X
RxSequenceChecking
ModeDataIntegrity
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
UserDefinedStat2 X X X X X X X X X X X X X X X X X X X X X X X X
CaptureTrigger X X X X X X X X X X X X X X X X
CaptureFilter X X X X X X X X X X X X X X X X
StreamTrigger1 X X
StreamTrigger2 X X
Type: States
DuplexMode X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
B-49
B
B-50 Table B-12. Statistics for Gigabit Modules
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
PortCpuStatus X X X X X X X
PortCpuDodStatus X X X X X X X
IpPackets X X
UdpPackets X X
TcpPackets X X
IpChecksumErrors X X
Type: Sequence
Checking
Type: Ethernet
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
VlanTaggedFramesRx X X X X X X X X X X X X X X
FlowControlFrames X X X X X X X X X X X X X X X X X X X X
Type: 10/100
AlignmentErrors X X X X
DribbleErrors X X X X X X X X X
Collisions X X X X X X X X X
LateCollisions X X X X X X X X X
CollisionFrames X X X X X X X X X
ExcessiveCollisionFrames X X X X X X X X X
Type: Gigabit
SymbolErrorFrames X X X X X X X X X X X X X X X X X X X
SynchErrorFrames X X X X X X X X X X X X
SymbolErrors X X X X X X X X X X
B-51
B
B-52
Table B-13. Statistics for OC12c/OC3c Modules
Normal Qos StreamTrigger ModeChecksum ModeDataIntegrity Add’l
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
UserDefinedStat1 X X X X X X X X X X X X X X X X X X X X X X X X X X
StreamTrigger1 X X X
StreamTrigger2 X X X
Type: States
DuplexMode X X X X X X X X X X X X
Type: Common
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
PortCpuStatus X X X X X X
PortCpuDodStatus X X X X X X
Type: Framer
FramerFCSErrors
FramerAbort X
FramerMinLength X
FramerMaxLength X
IpPackets X X
UdpPackets X X
TcpPackets X X
B-53
B
B-54 Table B-13. Statistics for OC12c/OC3c Modules
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
Type: Sequence
Checking
Type: Ethernet
Fragments X X X X X X X X X X X X
Undersize X X X X X X X X X X X X
Oversize X X X X X X X X X X X X
FlowControlFrames X X X X X X X X X X X
Type: 10/100
DribbleErrors X X X X X X X X
Collisions X X X X X X X X
LateCollisions X X X X X X X X
CollisionFrames X X X X X X X X
ExcessiveCollisionFrames X X X X X X X X
LineAis
LineBip
LineRei
LineRdi
PathAis
PathBip
PathRei
PathRdi
PathPlm
SectionBip
Type: POS
SymbolErrors
Type: Gigabit
SynchErrorFrames
PathLossOfPointer
SymbolErrorFrames
SectionLossOfSignal
SectionLossOfFrame
Capture
PacketGroup
Normal
RxTcpRoundTrip
RxDataIntegrity
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
X RxModeWidePacketGroup
Capture
Qos
PacketGroup
X
RxFirstTimeStamp
X
Capture
PacketGroup
RxTcpRoundTrip
RxDataIntegrity
StreamTrigger
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
X
Capture
PacketGroup
Errors
RxDataIntegrity
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
ModeChecksum
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
ModeDataIntegrity
X
X
X
X
X
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
B
B-56 Table B-13. Statistics for OC12c/OC3c Modules
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
Capture
Capture
Capture
Capture
Capture
SectionBipErroredSecs
SectionBipSeverlyErrored
Secs
SectionLossOfSignalSecs
LineBipErroredSecs
LineReiErroredSecs
LineAisAlarmSecs
LineRdiUnavailableSecs
PathBipErroredSecs
PathReiErroredSecs
PathAisAlarmSecs
PathAisUnavailableSecs
PathRdiUnavailableSecs
InputSignalStrength
PosK1Byte
PosK2Byte
SrpDataFramesReceived
SrpDiscoveryFrames
Received
SrpIpsFramesReceived
SrpParityErrors
CaptureTrigger
SrpUsageStatus
UserDefinedStat2
UserDefinedStat1
SrpUsageTimeouts

SrpUsageFramesReceived
X
Capture Capture
PacketGroup PacketGroup
Normal
Normal
X
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking RxFirstTimeStamp
RxModeBert RxSequenceChecking
Table B-14. Statistics for OC48c Modules with BERT
X
X X X X X X X X
X X X X X X X X
RxModeWidePacketGroup RxModeWidePacketGroup
Capture Capture
Qos
PacketGroup
Qos
PacketGroup
RxFirstTimeStamp
RxSequenceChecking RxFirstTimeStamp
RxModeBert RxModeWidePacketGroup
RxModeWidePacketGroup Capture
X
Capture PacketGroup
PacketGroup
RxTcpRoundTrip
X
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
StreamTrigger
RxFirstTimeStamp RxFirstTimeStamp
StreamTrigger
RxSequenceChecking RxSequenceChecking
X X X X X X X X RxModeWidePacketGroup
Capture
X X Capture
PacketGroup
Errors
PacketGroup
Errors
RxDataIntegrity RxDataIntegrity
X X X X
ModeChecksum
ModeChecksum
Capture
X X X
Capture
ModeDataIntegrity
RxModeBert
ModeDataIntegrity
X
X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X
PosExtendedStats
PosExtendedStats
Add’l
Add’l
B
B-58 Table B-14. Statistics for OC48c Modules with BERT
Normal Qos StreamTrigger ModeChecksum ModeDataIntegrity
Errors Add’l
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
Capture
Capture
Capture
Capture
Capture
StreamTrigger1 X X X X X
StreamTrigger2 X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X X X X X X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X X
Errors Add’l
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
Capture
Capture
Capture
Capture
Capture
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
QualityOfService0 X X X X X X
IpPackets X X X
UdpPackets X X X
TcpPackets X X X
IpChecksumErrors X X X
UdpChecksumErrors X X X
TcpChecksumErrors X X X
Type: Sequence
Checking
SequenceFrames X X X X X
SequenceErrors X X X X X
Type: Ethernet
B-59
Fragments X X X X X X X X X X X X
B
B-60 Table B-14. Statistics for OC48c Modules with BERT
Errors Add’l
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
Capture
Capture
Capture
Capture
Capture
Undersize X X X X X X X X X X X X
Oversize X X X X X X X X X X X X
FlowControlFrames X X X X X X X X X X X
Type: 10/100
DribbleErrors X X X X X X X X
Collisions X X X X X X X X
LateCollisions X X X X X X X X
CollisionFrames X X X X X X X X
ExcessiveCollisionFrames X X X X X X X X
Type: Gigabit
SymbolErrorFrames X X X X
SynchErrorFrames X X X X
SymbolErrors X X X X
OversizeAndCrcErrors X X X X X X X X X X
Type: POS
SectionLossOfSignal X
SectionLossOfFrame X
Errors Add’l
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
Capture
Capture
Capture
Capture
Capture
SectionBip X
LineAis X
LineRdi X
LineRei X
LineBip X
PathAis X
PathRdi X
PathRei X
PathBip X
PathLossOfPointer X
PathPlm X
SectionBipErroredSecs X X X X X X X X X X X X X X X X X X X X X X X X
SectionBipSeverlyErrored X X X X X X X X X X X X X X X X X X X X X X X X
Secs
SectionLossOfSignalSecs X X X X X X X X X X X X X X X X X X X X X X X X
LineBipErroredSecs X X X X X X X X X X X X X X X X X X X X X X X X
LineReiErroredSecs X X X X X X X X X X X X X X X X X X X X X X X X
LineAisAlarmSecs X X X X X X X X X X X X X X X X X X X X X X X X
LineRdiUnavailableSecs X X X X X X X X X X X X X X X X X X X X X X X X
B-61
PathBipErroredSecs X X X X X X X X X X X X X X X X X X X X X X X X
Received
PosK2Byte
PosK1Byte
SrpParityErrors
SrpUsageStatus
PathAisAlarmSecs
SrpUsageTimeouts
InputSignalStrength
PathReiErroredSecs
SrpDiscoveryFrames
Capture
X X
X X
X X
X X
PacketGroup
Normal
RxTcpRoundTrip
X
X
X
X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X X
X X
X X
X X
RxModeBert
Capture
Qos
X X
X X
X X
X X
PacketGroup
RxFirstTimeStamp
RxSequenceChecking
X X
X X
X X
X X
RxModeBert
Capture
X X
X X
X X
X X
PacketGroup
RxTcpRoundTrip
X
X
X
X
RxDataIntegrity
RxFirstTimeStamp
StreamTrigger
RxSequenceChecking
X X
X X
X X
X X
RxModeBert
Capture
PacketGroup
Errors
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
ModeChecksum
X X
X X
X X
X X
RxModeBert
Capture
PacketGroup
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X X
X X
X X
X X
RxModeBert
ModeDataIntegrity
PosExtendedStats
Add’l
Table B-15. Statistics for OC48c Modules with SRP and DCC
Normal Qos StreamTrigger ModeChecksumError ModeDataIntegrity Add’l
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
UserDefinedStat2 X X X X X X X X X X X X X X X X X X X X X X
CaptureTrigger X X X X X X
CaptureFilter X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X
B-63
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B
B-64 Table B-15. Statistics for OC48c Modules with SRP and DCC
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X
IpPackets X X
UdpPackets X X
TcpPackets X X
Type: Sequence
Checking
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
Type: Ethernet
Fragments X X X X
Undersize X X X X
Oversize X X X X
VlanTaggedFramesRx X X X X
FlowControlFrames X X X X
Type: Gigabit
OversizeAndCrcErrors X X X X
Type: POS
SectionBip X
LineAis X
LineRdi X
LineRei X
LineBip X
B-65
PathAis X
B
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
PathRdi X
PathRei X
PathBip X
PathLossOfPointer X
PathPlm X
Secs
PathReiErroredSecs X X X X X X X X X X X X X X X X X X X X X X X X
PathAisAlarmSecs X X X X X X X X X X X X X X X X X X X X X X X X
PathAisUnavailableSecs X X X X X X X X X X X X X X X X X X X X X X X X
PathRdiUnavailableSecs X X X X X X X X X X X X X X X X X X X X X X X X
InputSignalStrength
PosK1Byte X X X X X X X X X X X X X X X
PosK2Byte X X X X X X X X X X X X X X X
SrpDataFramesReceived X X X X X X X X X X X X X X X
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
SrpDiscoveryFrames X X X X X X X X X X X X X X X
Received
SrpIpsFramesReceived X X X X X X X X X X X X X X X
SrpParityErrors X X X X X X X X X X X X X X X
SrpUsageFramesReceived X X X X X X X X X X X X X X X
SrpUsageStatus X X X X X X X X X X X X X X X
SrpUsageTimeouts X X X X X X X X X X X X X X X
Type: DCC
DccBytesReceived X X X X X
DccBytesSent
DccCrcErrorsReceived X X X X X
DccFramesReceived X X X X X
DccFramesSent
DccFramingErrors
Received
B-67
B
B-68
Table B-16. Statistics for OC48c Modules with RPR and DCC
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
UserDefinedStat2 X X X X X X X X X X X X X X X X X X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X
IpPackets X X
UdpPackets X X
TcpPackets X X
Type: Sequence
Checking
B-69
B
B-70 Table B-16. Statistics for OC48c Modules with RPR and DCC
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
Type: Ethernet
Fragments X X X X
Undersize X X X X
Oversize X X X X
VlanTaggedFramesRx X X X X
FlowControlFrames X X X X
Type: Gigabit
OversizeAndCrcErrors X X X X
Type: POS
SectionBip X
LineAis X
LineRdi X
LineRei X
LineBip X
PathAis X
PathRdi X
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
PathRei X
PathBip X
PathLossOfPointer X
PathPlm X
Secs
PathReiErroredSecs X X X X X X X X X X X X X X X X X X X X X X X X
PathAisAlarmSecs X X X X X X X X X X X X X X X X X X X X X X X X
PathAisUnavailableSecs X X X X X X X X X X X X X X X X X X X X X X X X
PathRdiUnavailableSecs X X X X X X X X X X X X X X X X X X X X X X X X
InputSignalStrength
PosK1Byte
PosK2Byte
B-71
B
s
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
SrpDiscoveryFrames
Received
SrpParityErrors
SrpUsageStatus
SrpUsageTimeouts
Type: DCC
DccBytesSent
DccFramesSent
DccFramingErrors
Received
Type: RPR
RprDiscoveryFrames X X X X X X X X X X X X X X X
Received
RprDataFramesReceived X X X X X X X X X X X X X X X
RprFairnessFrames X X X X X X X X X X X X X X X
Received
RprFairnessFramesSent X X X X X X X X X X X X X X X
RprFairnessTimeouts X X X X X X X X X X X X X X X
Received
CaptureTrigger
UserDefinedStat2
UserDefinedStat1
RprHeaderCrcErrors
RprProtectionFrames
RprPayloadCrcErrors
RprOamFramesReceived

X
X
X
X
Capture Capture
PacketGroup
X
X
X
X
PacketGroup
X X X
RxDataIntegrity
Normal
Normal
X
X
X
X
RxFirstTimeStamp RxDataIntegrity
X
X X X X X
X X X X X
RxSequenceChecking
RxFirstTimeStamp
RxModeBert
X
X
X
RxModeBertChannelized RxSequenceChecking
Table B-17. Statistics for 2.5G MSM POS modules

RxModeDcc
X
X
X
RxModeDcc
Capture Qos Capture
Qos
PacketGroup
PacketGroup
RxDataIntegrity
X X X X X
X X X X X X X
X X X X X X X
RxModeBert
RxModeDcc
RxModeBertChannelized
RxModeDcc
X
X
X
Capture
X
X
X
PacketGroup
Capture
PacketGroup
X
X
X
RxDataIntegrity
X X X X
RxDataIntegrity
RxFirstTimeStamp
StreamTrigger
RxFirstTimeStamp
X
X X X X X X
X X X X X X
RxSequenceChecking
X
X
X
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
RxModeBertChannelized RxModeDcc
s
X X X RxModeDcc Capture
X X
Capture PacketGroup
PacketGroup RxDataIntegrity
Errors
RxDataIntegrity
RxFirstTimeStamp
X
RxFirstTimeStamp
X X X X X X X X
RxModeBert
ModeChecksum
ModeChecksumError
RxModeDcc RxModeDcc
Capture
X
X
X
Capture
PacketGroup
X
X
X
PacketGroup
X X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
X
RxDataIntegrity
X
RxSequenceChecking
RxModeBert RxFirstTimeStamp
X
X
X
RxSequenceChecking
ModeDataIntegrity
ModeDataIntegrity
RxModeDcc
X
X
X
RxModeDcc
X
X X X X X X X X X
X X X X X X X X X X
PosExtendedStats PosExtendedStats
TemperatureSensorsStats
Add’l
Add’l
B
B-74 Table B-17. Statistics for 2.5G MSM POS modules
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
CaptureFilter X X X X X X X X X X X X X X X X X X X X X
StreamTrigger1 X X X X X X X X X X X X X X X X X X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
IpPackets
Checking
Fragments
TcpPackets
UdpPackets
Type: Ethernet
SequenceErrors
Type: Sequence
TransmitDuration
SequenceFrames
QualityOfService0
IpChecksumErrors
DataIntegrityErrors
TcpChecksumErrors
DataIntegrityFrames
UdpChecksumErrors
Capture
PacketGroup
X
X
RxDataIntegrity
Normal
X
RxFirstTimeStamp
X
X
X X X X X
RxSequenceChecking
RxModeBert
X
RxModeDcc
Capture
Qos
PacketGroup
X
X
RxDataIntegrity
X
X
RxSequenceChecking
RxModeBert
X X
RxModeDcc
X X X X X X X X
Capture
X PacketGroup
X
RxDataIntegrity
X
RxFirstTimeStamp
X
X
X X X X X X X X X X X X X X X X
RxSequenceChecking
StreamTrigger
RxModeBert
X
RxModeDcc
Capture
PacketGroup
Errors
X X X
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
X
RxFirstTimeStamp
X
X
X
X
X
X
X X X X X X X X
RxSequenceChecking
RxModeBert
ModeChecksum
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
X
X
RxDataIntegrity
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
X X
ModeDataIntegrity
RxModeDcc
X X X X X X X X X X
PosExtendedStats
Add’l
LineAis
LineBip
LineRei
LineRdi
PathAis
PathRdi
Oversize
Undersize
SectionBip
Type: POS
SymbolErrors
Type: Gigabit
SynchErrorFrames
FlowControlFrames
SymbolErrorFrames
SectionLossOfSignal
SectionLossOfFrame
VlanTaggedFramesRx
Capture
PacketGroup
RxDataIntegrity
Normal
X
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
X
RxModeBert
X
X
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X X
X X
X X
X X
X X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
X
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X
X X
X X
X X
X X
ModeDataIntegrity
RxModeDcc
X
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
Secs
PathBip
PathRei
PathPlm
PosK2Byte
PosK1Byte
LineAisAlarmSecs
PathAisAlarmSecs
PathLossOfPointer
InputSignalStrength
LineBipErroredSecs
LineReiErroredSecs
PathBipErroredSecs
PathReiErroredSecs
Capture
PacketGroup
X X X
X X X
RxDataIntegrity
Normal
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
X X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
X X X X X
X X X X X
RxSequenceChecking
RxModeBert
X X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
X X X X
X X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
RxSequenceChecking
StreamTrigger
RxModeBert
X X
RxModeDcc
X
X
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X X X
RxModeDcc
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
B
B-78 Table B-17. Statistics for 2.5G MSM POS modules
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
SrpDataFramesReceived X X X X X X X X X X X X X X X X X X X X
SrpDiscoveryFrames X X X X X X X X X X X X X X X X X X X X
Received
SrpIpsFramesReceived X X X X X X X X X X X X X X X X X X X X
SrpParityErrors X X X X X X X X X X X X X X X X X X X X
SrpUsageFramesReceived X X X X X X X X X X X X X X X X X X X X
SrpUsageStatus X X X X X X X X X X X X X X X X X X X X
SrpUsageTimeouts X X X X X X X X X X X X X X X X X X X X
Type: DCC
DccBytesSent
DccFramesSent
DccFramingErrors
Received
Type: BERT
BertStatus X X X
BertBitsSent X X X
BertBitsReceived X X X
BertBitErrorsSent X X X
Ratio
Ones
Zeros
Errors
Seconds
SecondRatio
BertBitErrorRatio
BertErroredBlocks
BertSeverlyErrored
BertBlockErrorState
BertSeverelyErrored
BertErroredSeconds
BertBackgroundBlock
BertAvailableSeconds
BertBitErrorsReceived
BertErrorFreeSeconds
BertNumberMismatched
BertErroredSecondRatio
BertUnavailableSeconds
BertBackgroundBlockError
BertMismatchedOnesRatio
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
PosExtendedStats
Add’l
Rate
Time
Frame
Frames
Frames
Frames
Frames
Strength
BertTriggerCount
BertElapsedTestTime
BertRxDeskewLossOf
BertTxDeskewErrored
BertRxDeskewErrored
BertTxDeskewBitErrors
BertTimeSinceLastError
BertDeskewPatternLock
BertTxDeskewErrorFree
Type: Service Disruption

BertRxDeskewErrorFree
BertLastServiceDisruption
BertUnframedOutputSignal
BertMismatchedZerosRatio
BertUnframedDetectedLine
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
X
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
PosExtendedStats
Add’l
Time
Time
Cumulative
Temperature
Temperature
Temperature
Temperature
Type: OC192 -
DMATemperature
PlmDevice3Internal
PlmDevice2Internal
PlmDevice1Internal
OverlayTemperature
LatencyTemperature
CaptureTemperature
BertServiceDisruption
FrontEndTemperature
SchedulerTemperature
BackgroundTemperature
BertMinServiceDisruption
BertMaxServiceDisruption
FobPort1FpgaTemperature
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
X
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
PosExtendedStats
X
X
X
X
X
X
Add’l
Received
Received
Signaling
LocalFaults
Temperature
Temperature
Temperature
Type: 10 Gig
RemoteFaults
LinkFaultState
PauseOverwrite
DroppedFrames
Type: Link Fault
10GigLanTxFpga
10GigLanRxFpga
PauseEndFrames
FobDevice1Internal
CodingErrorFrames
PauseAcknowledge
FobBoardTemperature
EErrorCharacterFrames
FobPort2FpgaTemperature Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X
X
X
X X
X X
X X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X RxModeBert
X
X
X
X
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
X X
X X
X X
ModeDataIntegrity
RxModeDcc
PosExtendedStats
Add’l
Received
Received
Received
Type: RPR
RprFairnessFrames
RprHeaderCrcErrors
RprDiscoveryFrames
RprFairnessTimeouts
RprProtectionFrames
RprPayloadCrcErrors
RprFairnessFramesSent
RprDataFramesReceived
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
X
X
X
X
X
X
RxModeDcc
PosExtendedStats
Add’l
B
B-84
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
UserDefinedStat1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
UserDefinedStat2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureFilter X X X X X X X X
StreamTrigger1 X X X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxTcpRoundTrip
RxTcpRoundTrip
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
QualityOfService0 X X X X X X X X
IpPackets X X X X
UdpPackets X X X X
TcpPackets X X X X
IpChecksumErrors X X X X
UdpChecksumErrors X X X X
TcpChecksumErrors X X X X
B-85
Oversize
Collisions
Undersize
Checking
Fragments
DribbleErrors
Type: 10/100
LateCollisions
Type: Gigabit
Type: Ethernet
CollisionFrames
AlignmentErrors
SequenceErrors
Type: Sequence
SequenceFrames
SynchErrorFrames
FlowControlFrames
SymbolErrorFrames
VlanTaggedFramesRx

ExcessiveCollisionFrames
Capture
PacketGroup
X
X
X
X
X
X
X
X
X
X
X
RxTcpRoundTrip
Normal
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
X
X
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
X
X
X
X
X
X
X
X
X
X
X
RxTcpRoundTrip
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
StreamTrigger
X
X
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
ModeChecksum
RxModeDcc
X
X
X
X
X
X
X
X
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
PosExtendedStats
Add’l
Secs
LineAis
LineBip
LineRei
LineRdi
PathAis
PathBip
PathRei
PathRdi
PathPlm
SectionBip
Type: POS
SymbolErrors
PathLossOfPointer
SectionLossOfSignal
SectionLossOfFrame
Capture
PacketGroup
RxTcpRoundTrip
Normal
RxDataIntegrity
X
X
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
X
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
Capture
PacketGroup
RxTcpRoundTrip
RxDataIntegrity
X
X
RxFirstTimeStamp
StreamTrigger
RxSequenceChecking
RxModeBert
X RxModeBertChannelized
X
X
RxModeDcc
Capture
PacketGroup
Errors
X X X
X X X
X X X
RxDataIntegrity
X
X
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
X X X
X X X
X X X
RxModeDcc
X
Capture
PacketGroup
RxDataIntegrity
X
X
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
X
RxModeDcc
X
X
X
X
X
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
Received
PosK2Byte
PosK1Byte
Type: DCC
SrpParityErrors
SrpUsageStatus
LineAisAlarmSecs
PathAisAlarmSecs
SrpUsageTimeouts
InputSignalStrength
LineBipErroredSecs
LineReiErroredSecs
PathBipErroredSecs
PathReiErroredSecs
SrpDiscoveryFrames
Capture
X X
PacketGroup
RxTcpRoundTrip
Normal
X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
X X X
Qos
PacketGroup
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
X X X
PacketGroup
RxTcpRoundTrip
X
RxDataIntegrity
RxFirstTimeStamp
StreamTrigger
RxSequenceChecking
RxModeBert
X X X
X
X
X
X
X
X
X
X
X
RxModeDcc
X
Capture
PacketGroup
Errors
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
RxModeDcc
Capture
PacketGroup
X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X X
ModeDataIntegrity
X
X
X
X
X
X
X
X
X
RxModeDcc
X
PosExtendedStats
Add’l
Received
Temperature
Temperature
Temperature
Temperature
DccBytesSent
Type: OC192 -
DccFramesSent
DMATemperature
DccFramingErrors
DccBytesReceived
PlmDevice3Internal
PlmDevice2Internal
PlmDevice1Internal
OverlayTemperature
LatencyTemperature
CaptureTemperature
DccFramesReceived
FrontEndTemperature
DccCrcErrorsReceived
Capture
PacketGroup
RxTcpRoundTrip
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
RxModeDcc
Capture
PacketGroup
RxTcpRoundTrip
RxDataIntegrity
RxFirstTimeStamp
StreamTrigger
RxSequenceChecking
RxModeBert
X
X
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
RxModeDcc
PosExtendedStats
X
X
X
X
X
X
X
X
X
Add’l
Temperature
UserDefinedStat2
UserDefinedStat1
FobDevice1Internal
FobBoardTemperature

Capture FobPort1FpgaTemperature Capture
RxTcpRoundTrip
Normal
Normal
RxModeBert
RxModeBert RxModeBertChannelized
RxModeDcc RxModeDcc
X X X X X X X X
X X X X X X X X
Capture
Capture
Qos
PacketGroup
Qos
PacketGroup RxFirstTimeStamp
RxModeBert
RxModeDcc RxModeBertChannelized
Capture RxModeDcc
PacketGroup RxModeWidePacketGroup
Capture
RxDataIntegrity PacketGroup
RxFirstTimeStamp RxTcpRoundTrip
StreamTrigger
RxSequenceChecking RxDataIntegrity
RxFirstTimeStamp
RxModeBert
StreamTrigger
RxSequenceChecking
RxModeDcc RxModeBert
X X X X X X X X
RxModeDcc
Capture
rors
PacketGroup Capture
Errors
RxDataIntegrity
RxFirstTimeStamp
RxFirstTimeStamp
X X X X
RxModeBert
ModeChecksumEr
RxModeDcc
ModeChecksum
RxModeDcc
Capture
PacketGroup Capture
RxDataIntegrity
RxFirstTimeStamp
RxFirstTimeStamp
ModeDataIntegrity
RxModeBert RxModeBert
ModeDataIntegrity
RxModeDcc
RxModeDcc
X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X
X
X
X
Add’l
Add’l
Normal Qos StreamTrigger ModeChecksumEr ModeDataIntegrity Add’l
rors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
StreamTrigger1 X X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B-91
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X
B
rors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X

IpPackets X X
UdpPackets X X
TcpPackets X X
Type: Sequence
Checking
Type: Ethernet
Fragments X X X X
LineAis
LineBip
LineRei
LineRdi
PathAis
PathRdi
Oversize
Undersize
SectionBip
Type: POS
SymbolErrors
Type: Gigabit
SynchErrorFrames
FlowControlFrames
SymbolErrorFrames
SectionLossOfSignal
SectionLossOfFrame
VlanTaggedFramesRx
Capture
PacketGroup
Normal
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
StreamTrigger
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
rors
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
ModeChecksumEr
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
ModeDataIntegrity
RxModeBert
RxModeDcc
X
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
B
rors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
PathRei X
PathBip X
PathLossOfPointer X
PathPlm X
SectionBipErroredSecs X X X X X X X X X
SectionBipSeverlyErrored X X X X X X X X X
Secs
SectionLossOfSignalSecs X X X X X X X X X
LineBipErroredSecs X X X X X X X X X
LineReiErroredSecs X X X X X X X X X
LineAisAlarmSecs X X X X X X X X X
LineRdiUnavailableSecs X X X X X X X X X
PathBipErroredSecs X X X X X X X X X
PathReiErroredSecs X X X X X X X X X
PathAisAlarmSecs X X X X X X X X X
PathAisUnavailableSecs X X X X X X X X X
PathRdiUnavailableSecs X X X X X X X X X
InputSignalStrength X X X X X X X X X X X X X X X X X X X X X
PosK1Byte X X X X X X X X X X X X X X X X X X X X X
PosK2Byte X X X X X X X X X X X X X X X X X X X X X
SrpDataFramesReceived X X X X X X X X X X X X X X X X X X X X X
rors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
SrpDiscoveryFrames X X X X X X X X X X X X X X X X X X X X X
Received
SrpIpsFramesReceived X X X X X X X X X X X X X X X X X X X X X
SrpParityErrors X X X X X X X X X X X X X X X X X X X X X
SrpUsageFramesReceived X X X X X X X X X X X X X X X X X X X X X
SrpUsageStatus X X X X X X X X X X X X X X X X X X X X X
SrpUsageTimeouts X X X X X X X X X X X X X X X X X X X X X
Type: DCC
DccBytesReceived X X X X X X X X
DccBytesSent
DccCrcErrorsReceived X X X X X X X X
DccFramesReceived X X X X X X X X
DccFramesSent
DccFramingErrors
Received
Type: OC192 -
Temperature
DMATemperature X
CaptureTemperature X
LatencyTemperature X
B-95
Temperature
Temperature
Temperature
Temperature
PlmDevice3Internal
PlmDevice2Internal
PlmDevice1Internal
FobDevice1Internal
OverlayTemperature
FrontEndTemperature
FobBoardTemperature
Capture
PacketGroup
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
StreamTrigger
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
rors
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
ModeChecksumEr
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
ModeDataIntegrity
RxModeBert
RxModeDcc
PosExtendedStats
X
X
X
X
X
X
X
X
X
Add’l
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
UserDefinedStat1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
UserDefinedStat2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B-97
B
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X
PortCpuDodStatus X X X X X X X X X X X X X X X X X X X X X X X X X X X
IpPackets X X
UdpPackets X X
TcpPackets X X
Type: Sequence
Checking
LineAis
LineRdi
Oversize
Undersize
Fragments
SectionBip
Type: POS
SymbolErrors
Type: Gigabit
Type: Ethernet
SequenceErrors
SequenceFrames
SynchErrorFrames
FlowControlFrames
SymbolErrorFrames
SectionLossOfSignal
SectionLossOfFrame
VlanTaggedFramesRx
Capture
PacketGroup
Normal
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
X
X
RxSequenceChecking
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
StreamTrigger
X
X
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
ModeDataIntegrity
RxModeBert
RxModeDcc
X
X
X
X
X
PosExtendedStats
Add’l
B
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
LineRei X
LineBip X
PathAis X
PathRdi X
PathRei X
PathBip X
PathLossOfPointer X
PathPlm X
SectionBipErroredSecs X X X X X X X X X
SectionBipSeverlyErrored X X X X X X X X X
Secs
SectionLossOfSignalSecs X X X X X X X X X
LineBipErroredSecs X X X X X X X X X
LineReiErroredSecs X X X X X X X X X
LineAisAlarmSecs X X X X X X X X X
LineRdiUnavailableSecs X X X X X X X X X
PathBipErroredSecs X X X X X X X X X
PathReiErroredSecs X X X X X X X X X
PathAisAlarmSecs X X X X X X X X X
PathAisUnavailableSecs X X X X X X X X X
PathRdiUnavailableSecs X X X X X X X X X
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
InputSignalStrength X X X X X X X X X X X X X X X X X X X X X
PosK1Byte
PosK2Byte
SrpDiscoveryFrames
Received
SrpParityErrors
SrpUsageStatus
SrpUsageTimeouts
Type: DCC
DccBytesReceived X X X X X X X X
DccBytesSent
DccCrcErrorsReceived X X X X X X X X
DccFramesReceived X X X X X X X X
DccFramesSent
DccFramingErrors
Received
B-101
Type: OC192 -
Temperature
B
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
DMATemperature X
CaptureTemperature X
LatencyTemperature X
OverlayTemperature X
FrontEndTemperature X
SchedulerTemperature X
PlmDevice1Internal X
Temperature
PlmDevice2Internal X
Temperature
PlmDevice3Internal| X
Temperature
FobPort1FpgaTemperature X
FobBoardTemperature X
FobDevice1Internal X
Temperature
Type: RPR
RprDiscoveryFrames X X X X X X X X X X X X X X X X X X X X X
Received
RprDataFramesReceived X X X X X X X X X X X X X X X X X X X X X
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
RprFairnessFrames X X X X X X X X X X X X X X X X X X X X X
Received
RprFairnessFramesSent X X X X X X X X X X X X X X X X X X X X X
RprFairnessTimeouts X X X X X X X X X X X X X X X X X X X X X
RprHeaderCrcErrors X X X X X X X X X X X X X X X X X X X X X
RprOamFramesReceived X X X X X X X X X X X X X X X X X X X X X
RprPayloadCrcErrors X X X X X X X X X X X X X X X X X X X X X
RprProtectionFrames X X X X X X X X X X X X X X X X X X X X X
Received
B-103
B
B-104
Table B-21. Statistics for 10GE Modules with BERT
Normal Qos StreamTrigger ModeChecksu ModeDataIntegrity Add’l
mErrors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
UserDefinedStat2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
mErrors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
QualityOfService0 X X X X X X X
IpPackets X X
UdpPackets X X
TcpPackets X X
B-105
B
B-106 Table B-21. Statistics for 10GE Modules with BERT
mErrors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
Type: Sequence
Checking
Type: Ethernet
Fragments X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Undersize X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Oversize X X X X X X X X X X X X X X X X X X X X X X X X X X X X
VlanTaggedFramesRx X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FlowControlFrames X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Gigabit
Type: POS
SectionBip X
LineAis X
Secs
LineBip
LineRei
LineRdi
PathAis
PathBip
PathRei
PathRdi
PathPlm
LineAisAlarmSecs
PathAisAlarmSecs
PathLossOfPointer
LineBipErroredSecs
LineReiErroredSecs
PathBipErroredSecs
PathReiErroredSecs
Capture
PacketGroup
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
RxModeDcc
Capture
PacketGroup
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
mErrors
RxFirstTimeStamp
RxSequenceChecking
ModeChecksu
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
X
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
Received
Received
Type: DCC
PosK2Byte
PosK1Byte
DccBytesSent
SrpParityErrors
DccFramesSent
SrpUsageStatus
DccFramingErrors
DccBytesReceived
SrpUsageTimeouts
InputSignalStrength
DccFramesReceived
SrpDiscoveryFrames
Capture
PacketGroup
X
X
X
X
X
X
X
X
X
X X X
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeBert
X X X X X X X X X X
X
X
X
X
RxModeDcc
Capture
PacketGroup
X
X
X
X
X
X
X
X
X
X X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
X X X X X
Capture
PacketGroup
X X X
X X X
RxDataIntegrity
mErrors
RxFirstTimeStamp
RxSequenceChecking
ModeChecksu
X
X X
X X
RxModeDcc
Capture
PacketGroup
X
X
X
X
X
X
X
X
X
X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
X X X X X
PosExtendedStats
Add’l
Temperature
Temperature
Temperature
Temperature
Type: 10 Gig
Temperature
Type: OC192 -
DMATemperature
PlmDevice3Internal
PlmDevice2Internal
PlmDevice1Internal
FobDevice1Internal
PauseAcknowledge
OverlayTemperature
LatencyTemperature
CaptureTemperature
FrontEndTemperature
FobBoardTemperature
Capture
X X
PacketGroup
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X X
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeBert
X X X X X X
RxModeDcc
Capture
X X X
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X X X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
mErrors
RxFirstTimeStamp
RxSequenceChecking
ModeChecksu
RxModeDcc
Capture
X X
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X X X
RxModeDcc
X
PosExtendedStats
X
X
X
X
X
X
X
X
X
X
X
X
Add’l
Received
Received
Signaling
LocalFaults
Temperature
Temperature
RemoteFaults
LinkFaultState
PauseOverwrite
DroppedFrames
Type: Link Fault
10GigLanTxFpga
10GigLanRxFpga
PauseEndFrames
CodingErrorFrames
Capture
X X
X X
X X
X X
X X
PacketGroup
Normal
RxDataIntegrity
RxFirstTimeStamp
X
X
X
RxSequenceChecking
RxModeBert
X
X
X
X X X
X X X
RxModeDcc
Capture
Qos
PacketGroup
X X X X
X X X X
X X X X
RxSequenceChecking
RxModeBert
X
X
X
X X X X X X
X X X X X X
RxModeDcc
Capture
X X X
X X X
X X X
X X X
X X X
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
X
X
X
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
X X X
X X X
RxModeDcc
X
X
X
X
X
Capture
PacketGroup
RxDataIntegrity
mErrors
RxFirstTimeStamp
RxSequenceChecking
ModeChecksu
RxModeDcc
Capture
X X
X X
X X
X X
X X
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
X
X
X
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
X
X X X
X X X
RxModeDcc
X
X
X
X
X
PosExtendedStats
Add’l
Table B-22. Statistics for 10G UNIPHY Modules with BERT

Normal Qos StreamTrigger ModeCheck ModeDataIntegrity Add’l
sumErrors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
CaptureTrigger X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B-111
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B
B-112 Table B-22. Statistics for 10G UNIPHY Modules with BERT
Normal Qos StreamTrigger ModeCheck ModeDataIntegrity Add’l
sumErrors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
QualityOfService0 X X X X X X X
IpPackets X X
UdpPackets X X
TcpPackets X X
Type: Sequence
Checking
LineAis
LineRdi
Oversize
Undersize
Fragments
SectionBip
Type: POS
SymbolErrors
Type: Gigabit
Type: Ethernet
SequenceErrors
SequenceFrames
SynchErrorFrames
FlowControlFrames
SymbolErrorFrames
SectionLossOfSignal
SectionLossOfFrame
VlanTaggedFramesRx
Capture
PacketGroup
Normal
RxDataIntegrity
X
X
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
X X
X X
X X
X X
X X
X X
RxModeDcc
Capture
Qos
PacketGroup
X
X
RxSequenceChecking
RxModeBert
X X X X X
X X X X X
X X X X X
X X X X X
X X X X X
X X X X X
RxModeDcc
X
X
X
X
X
X
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
StreamTrigger
RxModeBert
X X
X X
X X
X X
X X
X X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
sumErrors
ModeCheck
X
X
RxSequenceChecking
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
X
X
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X X
X X
X X
X X
X X
X X
RxModeDcc
X
X
X
X
X
PosExtendedStats
Add’l
Secs
LineBip
LineRei
PathAis
PathBip
PathRei
PathRdi
PathPlm
LineAisAlarmSecs
PathAisAlarmSecs
PathLossOfPointer
LineBipErroredSecs
LineReiErroredSecs
PathBipErroredSecs
PathReiErroredSecs
Capture
PacketGroup
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
RxModeDcc
Capture
PacketGroup
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
sumErrors
ModeCheck
RxSequenceChecking
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
Received
Received
PosK2Byte
PosK1Byte
Type: DCC
Temperature
DccBytesSent
Type: OC192 -
SrpParityErrors
DccFramesSent
SrpUsageStatus
DccFramingErrors
DccBytesReceived
SrpUsageTimeouts
InputSignalStrength
DccFramesReceived
SrpDiscoveryFrames
Capture
PacketGroup
X X X
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeBert
X X X X X X X X X X
X
X
X
RxModeDcc
Capture
PacketGroup
X X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
RxModeDcc
X X X X X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
sumErrors
ModeCheck
RxSequenceChecking
X
X
RxModeDcc
Capture
PacketGroup
X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
RxModeDcc
X X X X X
PosExtendedStats
Add’l
Temperature
Temperature
Temperature
Temperature
Type: 10 Gig
PauseOverwrite
DMATemperature
PauseEndFrames
PlmDevice3Internal
PlmDevice2Internal
PlmDevice1Internal
FobDevice1Internal
PauseAcknowledge
OverlayTemperature
LatencyTemperature
CaptureTemperature
FrontEndTemperature
FobBoardTemperature
Capture
PacketGroup
Normal
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X
X X
X X
RxModeDcc
Capture
Qos
PacketGroup
RxSequenceChecking
RxModeBert
X X X X X
X X X X X
X X X X X
RxModeDcc
X
X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X X
X X
X X RxModeBertChannelized
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
sumErrors
ModeCheck
RxSequenceChecking
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X X
X X
X X
RxModeDcc
PosExtendedStats
X
X
X
X
X
X
X
X
X
X
X
X
Add’l
Received
Received
Received
Received
Signaling
Type: RPR
LocalFaults
Temperature
Temperature
RemoteFaults
LinkFaultState
DroppedFrames
Type: Link Fault
10GigLanTxFpga
10GigLanRxFpga
CodingErrorFrames
RprFairnessFrames
RprDiscoveryFrames
RprFairnessTimeouts
Capture
PacketGroup
X X X
X X X
X X X
X X X
X X X
Normal
RxDataIntegrity
RxFirstTimeStamp
X
X
X
X
X
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
X X
X X
X X
X X
X X
Capture
Qos
PacketGroup
X X X
X X X
X X X
RxSequenceChecking
RxModeBert
X
X
X
X RxModeDcc
X
Capture
PacketGroup
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
X
X
X
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
RxModeDcc
X X
X X
X X
X X
X X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
sumErrors
ModeCheck
RxSequenceChecking
RxModeDcc
Capture
PacketGroup
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
X
X
X
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
RxModeDcc
X X
X X
X X
X X
X X
PosExtendedStats
Add’l
Received
Receive Mode
Statistics Mode
UserDefinedStat2
UserDefinedStat1
RprHeaderCrcErrors
RprProtectionFrames
RprPayloadCrcErrors

Capture Capture
X X X
X X X
X X X
X X X
RxDataIntegrity
Normal
Normal
RxDataIntegrity
RxSequenceChecking
X
X
X
X
RxSequenceChecking
RxModeBertChannelized RxModeBertChannelized
RxModeDcc RxModeDcc
X X
X X
X X
X X
Capture Capture
Table B-23. Statistics for 10GE LSM Modules (except NGY)

Qos
PacketGroup
Qos
PacketGroup
RxDataIntegrity RxSequenceChecking
X X X X X X X X X X X X X
X X X X X X X X X X X X X
RxSequenceChecking RxModeBert
RxModeBert RxModeBertChannelized
RxModeBertChannelized RxModeDcc
RxModeDcc RxModeWidePacketGroup
RxModeWidePacketGroup Capture
Capture PacketGroup
PacketGroup
X X X
X X X
X X X
X X X
RxDataIntegrity
RxDataIntegrity
RxFirstTimeStamp
RxFirstTimeStamp
X
X
X
RxSequenceChecking
StreamTrigger
RxSequenceChecking
RxModeBert
StreamTrigger
RxModeBert
RxModeDcc
RxModeDcc
X X
X X
X X
X X
X X X X X X X X X X
Capture
Capture
PacketGroup
PacketGroup
RxDataIntegrity
RxDataIntegrity
RxFirstTimeStamp
sumErrors
RxFirstTimeStamp
ModeCheck
sumErrors
RxSequenceChecking
ModeCheck
X X X X
RxSequenceChecking
RxModeDcc
RxModeDcc
Capture Capture
X X X
X X X
X X X
X X X
X
X
X
ModeDataIntegrity
ModeDataIntegrity
RxModeDcc RxModeDcc
X X
X X
X X
X X
X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
Add’l
Add’l
Statistics Mode Normal Qos StreamTrigger ModeCheck ModeDataIntegrity Add’l
sumErrors
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
CaptureFilter X X X X X X X X X X X X X
StreamTrigger1 X X X X X X X X X X X X X X X X X X X X X X X
StreamTrigger2 X X X X X X X X X X X X X X X X X X X X X X X
Type: States
Link X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
LineSpeed X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
DuplexMode X X X X
TransmitState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseState X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FcsErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BitsSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B-119
B
B-120 Table B-23. Statistics for 10GE LSM Modules (except NGY)
sumErrors
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

IpPackets X X
UdpPackets X X
TcpPackets X X
DataIntegrityFrames X X X X X
DataIntegrityErrors X X X X X
Type: Sequence
Checking
Type: Ethernet
Fragments X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
sumErrors
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
Undersize X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Oversize X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
VlanTaggedFramesRx X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FlowControlFrames X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Gigabit
OversizeAndCrcErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: POS
SectionBip X
LineAis X
LineRdi X
LineRei X
LineBip X
PathAis X
B-121
PathRdi X
B
sumErrors
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
PathRei X
PathBip X
PathLossOfPointer X
PathPlm X
SectionBipErroredSecs X X X X X X
SectionBipSeverlyErrored X X X X X X
Secs
SectionLossOfSignalSecs X X X X X X
LineBipErroredSecs X X X X X X
LineReiErroredSecs X X X X X X
LineAisAlarmSecs X X X X X X
LineRdiUnavailableSecs X X X X X X
PathBipErroredSecs X X X X X X
PathReiErroredSecs X X X X X X
PathAisAlarmSecs X X X X X X
PathAisUnavailableSecs X X X X X X
PathRdiUnavailableSecs X X X X X X
InputSignalStrength X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PosK1Byte
PosK2Byte
Received
Received
Type: DCC
Temperature
DccBytesSent
Type: OC192 -
Receive Mode
SrpParityErrors
DccFramesSent
SrpUsageStatus
Statistics Mode
DMATemperature
DccFramingErrors
DccBytesReceived
SrpUsageTimeouts
LatencyTemperature
CaptureTemperature
DccFramesReceived
SrpDiscoveryFrames
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
sumErrors
ModeCheck
RxSequenceChecking
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
RxModeDcc
PosExtendedStats
X
X
X
X
Add’l
B
sumErrors
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
OverlayTemperature X
FrontEndTemperature X
PlmDevice1Internal
Temperature
PlmDevice2Internal
Temperature
PlmDevice3Internal
Temperature
FobBoardTemperature
FobDevice1Internal
Temperature
Type: 10 Gig
PauseAcknowledge X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseEndFrames X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseOverwrite X X X X X X X X X X X X X X X X X X X X X X X X X X X X
10GigLanTxFpga
Temperature
10GigLanRxFpga
Temperature
sumErrors
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
CodingErrorFrames X X X X X X X X X X X X X X X X X X X X
Received
EErrorCharacterFrames X X X X X X X X X X X X X X X X X X X X
Received
DroppedFrames X X X X X X X X X X X X X X X X X X X X
Type: Link Fault
Signaling
LinkFaultState X X X X X X X X X X X X X X X X X X X X X X X X
LocalFaults X X X X X X X X X X X X X X X X X X X X X X X X
RemoteFaults X X X X X X X X X X X X X X X X X X X X X X X X
Type: RPR
RprDiscoveryFrames X X X
Received
RprDataFramesReceived X X X
RprFairnessFrames X X X
Received
RprFairnessFramesSent X X X
RprFairnessTimeouts X X X
RprHeaderCrcErrors X X X
RprOamFramesReceived X X X
B-125
RprPayloadCrcErrors X X X
Received
Received
Received
Received
Receive Mode
Statistics Mode
LocalOrderedSets
Type: Ordered Sets
CustomOrderedSets
RemoteOrderedSets
RprProtectionFrames
LocalOrderedSetsSent
CustomOrderedSetsSent
RemoteOrderedSetsSent
Capture
PacketGroup
X X X
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
Normal
RxFirstTimeStamp
X
X
X
X
X
X RxSequenceChecking
RxModeBert
X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
X X X X X
X X X X X
X X X X X
X X X X X
X X X X X
X X X X X
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
X
X
X
X
RxSequenceChecking
StreamTrigger
RxModeBert
X
RxModeDcc
X
X
X
X
X
X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
sumErrors
ModeCheck
RxSequenceChecking
RxModeDcc
Capture
PacketGroup
X X X
X X X
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
X
X
X
X
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
X
X
X
X
X
X
PosExtendedStats
Add’l
Table B-24. Statistics for NGY Modules

Statistics Mode Normal Qos
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
UserDefinedStatByteCount1 X X X X X X X X
UserDefinedStatByteCount2 X X X X X X X X
CaptureTrigger X X X X
StreamTrigger1 X X X X X X X X
Type: States
Link X X X X X X X X
LineSpeed X X X X X X X X
DuplexMode
TransmitState X X X X X X X X
CaptureState X X X X X X X X
PauseState X X X X X X X X
Type: Common
FramesSent X X X X X X X X
B-127
FramesReceived X X X X X X X X
BytesSent X X X X X X X X
B
B-128 Table B-24. Statistics for NGY Modules
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
FcsErrors X X X X X X X X
BitsSent X X X X X X X X
PortCpuStatus X X X X X X X X
PortCpuDodStatus X X X X X X X X
TransmitDuration X X X X X X X X
IPv4Packets X X X X X X X X
UdpPackets X X X X X X X X
TcpPackets X X X X X X X X
IPv4ChecksumErrors X X X X X X X X
UdpChecksumErrors X X X X X X X X
TcpChecksumErrors X X X X X X X X
DataIntegrityFrames X X
DataIntegrityErrors X X
Type: Sequence Checking
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
SequenceFrames X X
SequenceErrors X X
Type: Ethernet
Fragments X X X X X X X X
Undersize X X X X X X X X
Oversize X X X X X X X X
FlowControlFrames X X X X X X X X
Type: Gigabit
SymbolErrorFrames
SynchErrorFrames
SymbolErrors
OversizeAndCrcErrors X X X X X X X X
Type: POS
SectionLossOfSignal
SectionLossOfFrame
SectionBip
LineAis
LineRdi
B-129
LineRei
B
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
LineBip
PathAis
PathRdi
PathRei
PathBip
PathLossOfPointer
PathPlm
Secs
LineBipErroredSecs
LineReiErroredSecs
LineAisAlarmSecs
PathBipErroredSecs
PathReiErroredSecs
PathAisAlarmSecs
InputSignalStrength X X X X X X X X
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
PosK1Byte
PosK2Byte
SrpDiscoveryFrames
Received
SrpParityErrors
SrpUsageStatus
SrpUsageTimeouts
Type: DCC
DccBytesReceived
DccBytesSent
DccFramesReceived
DccFramesSent
DccFramingErrors
Received
Type: OC192 - Temperature
DMATemperature
B-131
CaptureTemperature
B
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
LatencyTemperature
OverlayTemperature
FrontEndTemperature
PlmDevice1Internal
Temperature
PlmDevice2Internal
Temperature
PlmDevice3Internal
Temperature
FobBoardTemperature
FobDevice1Internal
Temperature
Type: 10 Gig
PauseAcknowledge X X X X X X X X
PauseEndFrames X X X X X X X X
PauseOverwrite X X X X X X X X
10GigLanTxFpga
Temperature
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
10GigLanRxFpga
Temperature
CodingErrorFrames X X X X X X X X
Received
EErrorCharacterFrames X X X X X X X X
Received
DroppedFrames X X X X X X X X
Type: Link Fault Signaling
LinkFaultState X X X X X X X X
LocalFaults X X X X X X X X
RemoteFaults X X X X X X X X
Type: RPR
RprDiscoveryFrames
Received
RprFairnessFrames
Received
RprFairnessTimeouts
RprHeaderCrcErrors
B-133
RprPayloadCrcErrors
B
Receive Mode
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
RprProtectionFrames
Received
Type: Ordered Sets
LocalOrderedSetsSent X X X X X X X X
LocalOrderedSets X X X X X X X X
Received
RemoteOrderedSetsSent X X X X X X X X
RemoteOrderedSets X X X X X X X X
Received
CustomOrderedSetsSent X X X X X X X X
CustomOrderedSets X X X X X X X X
Received
Table B-25. Statistics for 10G MSM modules

Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
UserDefinedStat1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureFilter X X X X X X X X X X X X X
Type: States
DuplexMode X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B-135
BytesReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
B
B-136 Table B-25. Statistics for 10G MSM modules
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
IpPackets X X X X X
UdpPackets X X X X X
TcpPackets X X X X X
IpChecksumErrors X X X X X
UdpChecksumErrors X X X X X
TcpChecksumErrors X X X X X
Type: Sequence
Checking
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
Type: Ethernet
VlanTaggedFramesRx X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FlowControlFrames X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: Gigabit
OversizeAndCrcErrors X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Type: POS
SectionLossOfSignal X X X
SectionLossOfFrame
SectionBip
LineAis
B-137
LineRdi
Secs
LineBip
LineRei
PathAis
PathBip
PathRei
PathRdi
PathPlm
LineAisAlarmSecs
PathAisAlarmSecs
PathLossOfPointer
LineBipErroredSecs
LineReiErroredSecs
PathBipErroredSecs
PathReiErroredSecs
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
Add’l
Received
Received
BertStatus
PosK2Byte
PosK1Byte
Type: DCC
Type: BERT
DccBytesSent
SrpParityErrors
DccFramesSent
SrpUsageStatus
DccFramingErrors
DccBytesReceived
SrpUsageTimeouts
InputSignalStrength
DccFramesReceived
SrpDiscoveryFrames
Capture
PacketGroup
X X X RxDataIntegrity
Normal
RxFirstTimeStamp
X
RxSequenceChecking
X
RxModeBert
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X X X X X X X X X
X
X
X
RxModeDcc
Capture
PacketGroup
X X X X
RxDataIntegrity
RxFirstTimeStamp
X
RxSequenceChecking
StreamTrigger
X
RxModeBert
X
X
RxModeDcc
X X X
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
RxModeBert
ModeChecksum
X
X
RxModeDcc
Capture
PacketGroup
X X X
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
RxModeDcc
X X X X X
Add’l
Ratio
Ratio
Ones
Errors
Seconds
BertBitsSent
BertBitErrorRatio
BertBitsReceived
BertBitErrorsSent
BertErroredBlocks
BertBlockErrorState
BertSeverelyErrored
BertErroredSeconds
BertBackgroundBlock
BertSeverlyErroredSecond
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
Add’l
Rate
Zeros
fFrame
Frames
Frames
Frames
Strength
BertTriggerCount
BertElapsedTestTime
BertRxDeskewLossO
BertTxDeskewErrored
BertRxDeskewErrored
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
Add’l
Time
Time
Time
Frames
Cumulative
Temperature
Temperature
Type: OC192 -
DMATemperature
PlmDevice1Internal
OverlayTemperature
LatencyTemperature
CaptureTemperature
FrontEndTemperature
BertLastServiceDisruption
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
X
X
X
X
X
X
Add’l
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
PlmDevice2Internal
Temperature
PlmDevice3Internal
Temperature
FobBoardTemperature
FobDevice1Internal
Temperature
Type: 10 Gig
PauseAcknowledge X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseEndFrames X X X X X X X X X X X X X X X X X X X X X X X X X X
PauseOverwrite X X X X X X X X X X X X X X X X X X X X X X X X X X
10GigLanTxFpga
Temperature
10GigLanRxFpga
Temperature
CodingErrorFrames X X X X X X X X X X X X X X X X X X X X
Received
EErrorCharacterFrames X X X X X X X X X X X X X X X X X X X X
Received
B-143
DroppedFrames X X X X X X X X X X X X X X X X X X X X
Received
Received
Received
Received
Signaling
Type: RPR
LocalFaults
RemoteFaults
LinkFaultState
Type: Link Fault
LocalOrderedSets
Type: Ordered Sets
RprFairnessFrames
RprHeaderCrcErrors
RprDiscoveryFrames
RprProtectionFrames
RprPayloadCrcErrors
RprFairnessTimeouts
Capture
PacketGroup
X X X
X X X
X X X
X X X RxDataIntegrity
Normal
RxFirstTimeStamp
X
X
X
X
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
X
X
X
X
X RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
X X X X X
X X X X X
X X X X X
X X X X X
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
Capture
PacketGroup
X X X X
X X X X
X X X X
X X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
X
X
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
X
X
X
X
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
X X X
X X X
X X X
X X X
RxDataIntegrity
RxFirstTimeStamp
X
X
X
X
RxSequenceChecking
RxModeBert
X
X
X
ModeDataIntegrity
X
X
X
X
X
X
X
X
X
RxModeDcc
X
X
X
X
Add’l
Received
Received
UserDefinedStat1
CustomOrderedSets
RemoteOrderedSets

Capture Capture
X X X
X X X
Normal
Normal
Table B-26. Statistics for ATM Modules

X X X X X
X
X
RxModeDcc RxModeDcc
X X X
Capture Capture
Qos
Qos
X X X X X
X X X X X
RxModeDcc RxModeDcc
Capture Capture
X X X X
X X X X
X X X X X X
X
X
StreamTrigger
StreamTrigger
RxModeDcc RxModeDcc
X
X
Capture Capture
Errors
Errors
X X X X X X X X
ModeChecksum
ModeChecksum
RxModeDcc RxModeDcc
Capture Capture
X X X
X X X
X
X
ModeDataIntegrity
ModeDataIntegrity
RxModeDcc RxModeDcc
X X X X X X X X X X
X
X
PosExtendedStats TemperatureSensorsStats
Add’l
Add’l
B
B-146 Table B-26. Statistics for ATM Modules
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
UserDefinedStat2 X X X X X X X X X X X X X X X X X X X X X X X X X X X
CaptureTrigger X X X X X X X X X
StreamTrigger1 X X X X X X X X X X
StreamTrigger2 X X X X X X X X X X
Type: States
DuplexMode X X X X
Type: Common
FramesSent X X X X X X X X X X X X X X X X X X X
FramesReceived X X X X X X X X X X X X X X X X X X X
BytesSent X X X X X X X X X X X X X X X X X X X
BytesReceived X X X X X X X X X X X X X X X X
BitsReceived X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
TransmitDuration X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
IpPackets X X X X X
UdpPackets X X X X X
TcpPackets X X X X X
IpChecksumErrors X X X X X
UdpChecksumErrors X X X X X
TcpChecksumErrors X X X X X
DataIntegrityFrames X
DataIntegrityErrors X
Type: Sequence
Checking
SequenceFrames X X
B-147
SequenceErrors X X
LineAis
LineBip
LineRei
LineRdi
Oversize
Undersize
Fragments
SectionBip
Type: POS
SymbolErrors
Type: Gigabit
Type: Ethernet
SynchErrorFrames
FlowControlFrames
SymbolErrorFrames
SectionLossOfSignal
SectionLossOfFrame
VlanTaggedFramesRx
Capture
PacketGroup
RxDataIntegrity
Normal
X
X
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
X
RxModeBert
X
X
X
X
X
X
RxModeDcc
X
X
X
X
X
X
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X X
X X
X X
X X
X X
X X
RxModeDcc
X
X
X
X
X
X
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
X
X
RxModeDcc
X
X
X
X
X
Capture
PacketGroup
Errors
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
X
X
X
X
X
X
X
X
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X
X X
X X
X X
X X
X X
ModeDataIntegrity
RxModeDcc
X
X
X
X
X
X
X
X
X
X
X
X
PosExtendedStats
Add’l
Secs
PathAis
PathBip
PathRei
PathRdi
PathPlm
LineAisAlarmSecs
PathAisAlarmSecs
PathLossOfPointer
InputSignalStrength
LineBipErroredSecs
LineReiErroredSecs
PathBipErroredSecs
PathReiErroredSecs
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
RxModeDcc
X X X
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
RxModeDcc
X X X
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
X
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
X X X X
X
X
X
X
X
X
PosExtendedStats
Add’l
Received
Received
BertStatus
PosK2Byte
PosK1Byte
Type: DCC
BertBitsSent
Type: BERT
DccBytesSent
SrpParityErrors
DccFramesSent
SrpUsageStatus
DccFramingErrors
DccBytesReceived
SrpUsageTimeouts
DccFramesReceived
SrpDiscoveryFrames
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
RxModeBert
X
X
X
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
RxModeBert
X
X
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
RxModeBert
ModeChecksum
X
X
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
X
X
RxModeDcc
PosExtendedStats
Add’l
Ratio
Ratio
Ones
Errors
Seconds
BertBitErrorRatio
BertBitsReceived
BertBitErrorsSent
BertErroredBlocks
BertBlockErrorState
BertSeverelyErrored
BertErroredSeconds
BertBackgroundBlock
BertSeverlyErroredSecond
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
PosExtendedStats
Add’l
Rate
Zeros
Frame
Frames
Frames
Frames
Frames
Strength
BertTriggerCount
BertElapsedTestTime
BertRxDeskewLossOf
BertTxDeskewErrored
BertRxDeskewErrored
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
X
X RxModeBert
RxModeDcc
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
RxModeBert
RxModeDcc
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
PosExtendedStats
Add’l
Time
Time
Received
Received
Type: ATM
Cumulative
Temperature
Temperature
Type: 10 Gig
DisruptionTime
BertLastService
PauseOverwrite
DroppedFrames
10GigLanTxFpga
10GigLanRxFpga
PauseEndFrames
CodingErrorFrames
PauseAcknowledge
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
RxModeBert
X
X
X
RxModeDcc
X
X
X
X
X
X
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X X
X X
X X
RxModeDcc
X
X
X
X
X
X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
X
X
X
X
RxModeBert
X
X
RxModeDcc
X
X
X
X
X
X
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
X
X
X
X
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X X
X X
X X
ModeDataIntegrity
RxModeDcc
X
X
X
X
X
X
PosExtendedStats
Add’l
B
B-154 Table B-26. Statistics for ATM Modules
Errors
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxSequenceChecking
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
RxFirstTimeStamp
PosExtendedStats
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
RxDataIntegrity
PacketGroup
PacketGroup
PacketGroup
PacketGroup
PacketGroup
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeBert
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
RxModeDcc
Capture
Capture
Capture
Capture
Capture
AtmAal5BytesReceived X X X X X X X X X X X X X X X X X X X X
AtmAal5BytesSent X X X X X X X X X X X X X X X X X X X X
AtmAal5CrcErrorFrames
AtmAal5FramesReceived X X X X X X X X X X X X X X X X X X X X
AtmAal5FramesSent X X X X X X X X X X X X X X X X X X X X
AtmAal5LengthError
Frames
AtmAal5TimeoutError
Frames
AtmCellsReceived X X X X X X X X X X X X X X X X X X X X
AtmCellsSent X X X X X X X X X X X X X X X X X X X X
AtmCorrectedHcsError X X X X X X X X X X X X X X X X X X X X
Count
AtmIdleCellCount X X X X X X X X X X X X X X X X X X X X
AtmScheduledCellsSent X X X X X X X X X X X X X X X X X X X X
AtmUncorrectedHcsError X X X X X X X X X X X X X X X X X X X X
Count
AtmUnregisteredCells X X X X X X X X X X X X X X X X X X X X
Received
EthernetCrc X X X X X X X X X X X X X X X X X X X X
Type: Link Fault
Signaling
Received
Received
Received
Received
Type: RPR
LocalFaults
RemoteFaults
LinkFaultState
LocalOrderedSets
Type: Ordered Sets
RprFairnessFrames
RprHeaderCrcErrors
RprDiscoveryFrames
RprProtectionFrames
RprPayloadCrcErrors
RprFairnessTimeouts
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
X
X
X
X
X
X
X
X
RxModeDcc
X
X
X
X
X
X
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
X
X
RxModeDcc
X
X
X
X
X
X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
X
X
X
X
X
X
X
X
X
X
X
RxModeDcc
X
X
X
X
X
X
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
X
X
ModeDataIntegrity
X
X
X
X
X
X
X
X
X
RxModeDcc
X
X
X
X
X
X
PosExtendedStats
Add’l
Received
Received
CustomOrderedSets
RemoteOrderedSets
Capture
PacketGroup
RxDataIntegrity
Normal
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
RxModeDcc
X
X
X
Capture
Qos
PacketGroup
RxDataIntegrity
RxSequenceChecking
RxModeBert
RxModeDcc
X
X
X
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
StreamTrigger
RxModeBert
RxModeDcc
X
X
X
Capture
PacketGroup
Errors
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeChecksum
RxModeDcc
Capture
PacketGroup
RxDataIntegrity
RxFirstTimeStamp
RxSequenceChecking
RxModeBert
ModeDataIntegrity
RxModeDcc
X
X
X
PosExtendedStats
Add’l
Table B-27. Statistics for PoE Modules

Single Mode
Type: PoE
PoeStatus X
PoeInputVoltage X
PoeInputCurrent X
PoeInputPower X
PoeActiveInput X
PoeTemperature X
PoeAutocalibration X
Table B-28. Statistics for 10/100/1000 AFM

Single Mode
Type: AFM
bytesFromApplication X
packetsFromApplication X
monitorBytesFromPort2 X
monitorBytesFromPort3 X
monitorPacketsFromPort2 X
monitorPacketsFromPort3 X
Table B-29. Statistics for IxNetwork

Additional Modes
ProtocolServerStats
IcmpStats
ArpStats
Type: Protocol Server - General

ProtocolServerTx X
ProtocolServerRx X
TxArpReply X
TxArpRequest X
TxPingReply X
TxPingRequest X
RxArpReply X
RxArpRequest X
RxPingReply X
RxPingRequest X
ProtocolServerVlanDroppedFrames X

Table B-29. Statistics for IxNetwork

Additional Modes
ProtocolServerStats
IcmpStats
ArpStats
ScheduledFramesSent
AsynchronousFramesSent
PortCPUFramesSent

Statistics for 1GbE In 1GbE Aggregated Mode, the ASM1000XMV12X-01 module has these
and 10GbE statistics for ports 1 through 12 (shown in Table B-30). Stats for Port 13 are
Aggregation Load inactive.
Modules In 10GbE Aggregated Mode, the ASM1000XMV12X-01 module has these
statistics for port 13. (shown in Table B-30). The stats in Port 1 to Port 12 are
resource only. The active stats are: Central Chip Temperature(C), Port Chip
Temperature(C), Port CPU Status, and Port CPU DoD Status.
In Normal mode, the ASM1000XMV12X-01 module statistics are shown in

Table B-10 on page B-41. In Normal (non-aggregated) mode only ports 1-12 are
active; port 13 is inactive.
Table B-30. Statistics for 1GbE/10GbE Aggregation Load Modules

1GbE Aggregation 10GbE Aggregation
Ports 1-12
LinkState X Resource only
LineSpeed X Resource only
DuplexMode X Resource only
FramesSent X Resource only
Valid FramesReceived X Resource only
Bytes Sent X Resource only
Bytes Received X Resource only
Port Cpu Status X X
Port Cpu Dod Status X X
Central Chip Temp (C) X X
Port Chip Temp (C) X X
Egress Dropped Frames X Resource only
Port CPU Ingress Dropped X X
Frames
Port CPU Frames X X
Received
Port CPU Bytes Received X X
Port 13
LinkState X
LineSpeed X
FramesSent X
Valid FramesReceived X
Bytes Sent X
Bytes Received X
Egress Dropped Frames X

Ethernet OAM Ethernet OAM statistics are capable of being generated for the load modules
Statistics listed in Table B-31 on page B-160.
Table B-31.Ethernet OAM Statistics

Ethernet OAM Stats
OAM Unsupported PDUs

OAM Organization PDUs
OAM Variable Response

OAM Event Notification
OAM Event Notification

OAM Information PDUs
OAM Information PDUs
OAM Variable Request

PDUs Received
PDUs Received
PDUs Received
PDUs Received
Received
Received
Received
Load Module Sent
10/100/1000 (S)TX(S)2, 4, 24 X X X X X X X X
1000 SFP(S)4 X X X X X X X X
10/100/1000 XMS(R)12 X X X X X X X X
10/100/1000 LSM XMV(R)4, 16 X X X X X X X X
10/100/1000 ASM XMV12 X X X X X X X X
10GE LSM (XM3, XMR3, XL6) in X X X X X X X X
LAN mode
10GE LSM (XM8, XMR8, XM4, X X X X X X X X
XMR4) in LAN mode
10GE LSM (XFP, XENPAK, X2, X X X X X X X X
10GBase-T) in LAN mode
10G MSM in LAN mode X X X X X X X X
10GE LSM MACSec LAN mode X X X X X X X X

MACsec Statistics MACsec statistics can be generated for the LSM10GMS load module and are
listed in Table B-32. For details, see IEEE standard 802.1 AE-2006, Media
Access Control (MAC) Security.
Table B-32. MACsec Statistics

Statistic Type Name Description
MACSec Valid Frames Sent macSecValidFramesSent 32-bit stat counter that indicates the
total number valid MACSEC packets
transmitted
MACSec Valid Bytes Sent macSecValidBytesSent 64-bit stat counter that indicates the
total numbre valid MACSEC bytes
transmitted
MACSec Frames With macSecFramesWithUnknownKeySent 32-bit stat counter that indicates the
Unknown Key Sent total number of transmit packets for
which no key was found
MACSec Valid Frames macSecValidFramesReceived 32-bit stat counter that indicates the
Received total number valid MACSEC packets
received
MACSec Valid Bytes macSecValidBytesReceived 64-bit stat counter that indicates the
Received total numbre valid MACSEC bytes
received
MACSec Frames With macSecFramesWithUnknownKeyReceived 32-bit stat counter that indicates the
Unknown Key Received total number of receive packets for
which no key was found
MACSec Frames With Bad macSecFramesWithBadHashReceived 32-bit stat counter that indicates the
Hash Received total number of receive packets with a
bad ICV
FCoE Statistics FCoE statistics can be generated for the NGY LSM10GXM family of load
modules and are listed in Table B-33.
Table B-33.FCoE Statistics
Statistic Type Name
FCoE Fabric Login sent fcoeFlogiSent
FCoE Fabric Login Link Service Accept fcoeFlogiLsAccReceived
received
FCOE Port Login sent fcoePlogiSent
FCOE Port Login Link Service Accept received fcoePlogiLsAccReceived
FCOE Port Login Requests received fcoePlogiRequestsReceived
FCoE Fabric Logout sent fcoeFlogoSent
FCOE Port Logout sent fcoePlogoSent
FCOE Port Logout received fcoePlogoReceived
FCoE Discovery sent. fcoeFdiscSent
FCoE Discovery Link Service Accept received fcoeFdiscLsAccReceived
FCoE Name Server Registration sent fcoeNSRegSent
FCoE Name Server Registration successful fcoeNSRegSuccessful
FCoE Nx Ports Enabled fcoeNxPortsEnabled

Table B-33.FCoE Statistics

Statistic Type Name
FCoE Nx Port IDs Acquired fcoeNxPortIdsAcquired
FCoE Rx Shared Stat 1 fcoeRxSharedStat1
FCoE Rx Shared Stat 2 fcoeRxSharedStat2
fcoeRxSharedStat1 and fcoeRxSharedStat2

Select the statistic to be assigned to these two counters from these options::
statFcoeInvalidDelimiter
statFcoeInvalidFrames
statFcoeInvalidSize
statFcoeNormalSizeBadFccRc
statFcoeNormalSizeGoodFccRc
statFcoeUndersizeBadFccRc
statFcoeUndersizeGoodFccRc
statFcoeValidFrames
FIP Statistics FIP statistics can be generated for any load module capable of FCoE and are
listed in Table B-34:
Table B-34.FIP Statistics
Statistic Type Name
Number of FIP Discovery Solicitations that FipDiscoverySolicitationsSent
have been sent
Number of FIP Discovery Advertisements FipDiscoveryAdvertisementsReceived
that have been received.
Number of FIP Keep Alives that have been FipKeepAlivesSent
sent.
Number of FIP Clear Virtual Links that have FipClearVirtualLinksReceived
been received.
ALM, ELM and Statistics generated for ALM1000T8, ELM1000ST2, and CPM1000T8-01 load
CPM Statistics modules are listed in Table B-35.
Table B-35. Statistics for 10/100/1000 ALM T8, ELM ST2, and CPM T8
Common Additional Statistics
TempSensors
DHCPv4Stats
DHCPv6Stats
ArpStats
Stats
Link State X
Line Speed X
Duplex Mode X

TempSensors
DHCPv4Stats
DHCPv6Stats
ArpStats
Stats
Frames Sent X
Valid Frames Received X
Bytes Sent X
Bytes Received X
Fragments X
Undersize X
Oversize and Good CRCs X
CRC Errors X
Alignment Errors X
Dribble Errors X
Collisions X
Late Collisons X
Collision Frames X
Excessive Collision Frames X
Oversize and CRC Errors X
ProtocolServer Transmit X
ProtocolServer Receive X
Transmit ARP Reply X
Transmit ARP Request X
Transmit Ping Reply X
Transmit Ping Request X
Receive ARP Reply X
Receive ARP Request X
Receive Ping Reply X
Receive Ping Request X
Bits Sent X
Bits Received X
Central Chip Temperature (C) X
Port Chip Temperature (C) X1
Port CPU Status X
Port CPU DoD Status X
DHCPv4 Discovered Messages Sent X
DHCPv4 Offers Received X
DHCPv4 Requests Sent X
DHCPv4 ACKs Received X
DHCPv4 NACKs Received X
DHCPv4 Releases Sent X
DHCPv4 Enabled Interfaces X

TempSensors
DHCPv4Stats
DHCPv6Stats
ArpStats
Stats
DHCPv4 Addresses Learned X
DHCPv6 Solicits Sent X
DHCPv6 Advertisements Received X
DHCPv6 Requests Sent X
DHCPv6 Declines Sent X
DHCPv6 Replies Received X
DHCPv6 Releases Sent X
DHCPv6 Enabled Interfaces X
DHCPv6 Addresses Learned X
1.Not ELM (ALM and CPM only)

40/100 GE Statistics
Table B-36. Statistics for 40/100GE LSM Modules
Normal Qos
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
UserDefinedStatByteCount X X X X X X X X
1
(supported only on Lava
AP40/100GE 2P
UserDefinedStatByteCount X X X X X X X X
2
(supported only on Lava
AP40/100GE 2P
CaptureTrigger X X X X X X X X
Type: States
Link X X X X X X X X
LineSpeed X X X X X X X X
TransmitState X X X X X X X X
CaptureState X X X X X X X X
PauseState X X X X X X X X
Type: Common
FramesSent X X X X X X X X
FramesReceived X X X X X X X X
BytesSent X X X X X X X X
FcsErrors X X X X X X X X
BitsSent X X X X X X X X
PortCpuStatus X X X X X X X X
PortCpuDodStatus X X X X X X X X
ScheduledTransmitTime X X X X X X X X


Normal Qos
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
TransmitDuration X X X X X X X X
QualityOfService 0-7 X X X X
IPv4Packets X X X X X X X X
UdpPackets X X X X X X X X
TcpPackets X X X X X X X X
IPv4ChecksumErrors X X X X X X X X
UdpChecksumErrors X X X X X X X X
TcpChecksumErrors X X X X X X X X
DataIntegrityFrames X X
DataIntegrityErrors X X
Type: Sequence
Checking
SequenceFrames X X
SequenceErrors X X
ReverseSequenceErrors X X
SmallSequenceErrors X X
TotalSequenceErrors X X
BigSequenceErrors X X
Type: Ethernet
Fragments X X X X X X X X
Undersize X X X X X X X X
Oversize X X X X X X X X
FlowControlFrames X X X X X X X X
Type: Temperature
PCPU FPGA Temperature X
Capture1 Fpga X
Temperature
Capture2 Fpga X
Temperature
Tx1 Fpga Temperature X


Normal Qos
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
Tx2 Fpga Temperature X
Latency1 Fpga X
Temperature
Latency2 Fpga X
Temperature
TxSchedulerOverlay X
Temperature
TxFmx Fpga Temperature X
RxFmx Fpga Temperature X
Type: Pause
PauseEndFrames
PauseOverwrite X X X X X X X X
Type: Gigabit
Oversize and CRC Errors X X X X X X X X
Type: POS
Input Signal Strength X X X X X X X X
Type: ARP
TxArpReply X X X X X X X X
TxArpRequest X X X X X X X X
RxArpReply X X X X X X X X
RxArpRequest X X X X X X X X
Type: ICMP
TxPingReply X X X X X X X X
TxPingRequest X X X X X X X X
RxPingReply X X X X X X X X
RxPingRequest X X X X X X X X
ScheduledFramesSent X X X X X X X X
AsynchronousFramesSent X X X X X X X X
PortCPUFramesSent X X X X X X X X
Type: Protocol Server-
General
ProtocolServerTx X X X X X X X X
ProtocolServerRx X X X X X X X X
ProtocolServerVlan X X X X X X X X
DroppedFrames


Normal Qos
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
Type: Link Fault
Signaling
LinkFaultState X X X X X X X X
LocalFaults X X X X X X X X
RemoteFaults X X X X X X X X
Type: LSM
codingErrorFrames X X X X X X X X
Received
eErrorCharacterFrames X X X X X X X X
Received
Type: PCS
PcsSyncErrorsReceived X X X X X X X X
PcsIllegalCodesReceived X X X X X X X X
PcsRemoteFaultsReceived X X X X X X X X
PcsLocalFaultsReceived X X X X X X X X
PcsIllegalOrderedSet X X X X X X X X
Received
PcsIllegalIdleReceived X X X X X X X X
PcsIllegalSofReceived X X X X X X X X
PcsOutOfOrderSof X X X X X X X X
Received
PcsOutOfOrderEof X X X X X X X X
Received
PcsOutOfOrderData X X X X X X X X
Received
PcsOutOfOrderOrderedSet X X X X X X X X
Received
TotalFrames X X X X X X X X
ReadTimeStamp X X X X X X X X
Type: Latency/Jitter
MinLatency X X X X X X X X
MaxLatency X X X X X X X X
MaxminInterval X X X X X X X X
AverageLatency X X X X X X X X
TotalByteCount X X X X X X X X
BitRate X X X X X X X X


Normal Qos
RxSequenceChecking
RxSequenceChecking
RxDataIntegrity
RxDataIntegrity
Capture
Capture
ByteRate X X X X X X X X
FrameRate X X X X X X X X
FirstTimeStamp X X X X X X X X
LastTimeStamp X X X X X X X X


GPS Antenna
Appendix C:
C Installation
Requirements
Ixia GPS equipped systems used to provide local Stratum 1 timing signals
requires the installation of a GPS antenna kit (942-0003 or 942-0005, where the
facility or environment prevent the window mount antenna from functioning).
This section describes the installation method we recommend for an IXIA GPS
Antenna. This section also provides a scheme for installation of lightning
protection for an installed antenna. In order to ensure that all of the following
criteria in this manual can be met, we recommend a site survey.
Note: This is not an installation manual and should not be used in place of
building codes for electronic installations applicable to specific sites.
This appendix has the following sections:

• Roof Mount Antenna on page C-1
• Window Mount Antenna on page C-5
Roof Mount Antenna

The general location requirements for installation of the GPS antenna and
conduit are:
Table C-1. GPS Location Requirements
1. Ideally, a roof area with an unobstructed 360-degree view of the sky

above the horizon. At the minimum, a 180-degree view of the sky is
required.
2. Mounted away from and above a plane from items such as elevators,
air conditions and other machinery.
3. Should have the best view of the horizon that is possible. No

obstructions should be within a ten-degree angle from the horizontal.
4. There should be adequate space available on the roof to install two

antennas with an absolute minimum of 10 feet between antennas.
5. The antenna should be 12 feet away from metallic objects.
Ixia Platform Reference Guide, Release 6.60 EA Patch1 C-1

C Roof Mount Antenna
Table C-1. GPS Location Requirements
6. Sufficient access to the roof for installation of the GPS conduit/mast

and antenna.
7. Permission to run a 2-inch PVC conduit from the GPS antenna on the
roof to the building entrance point.
8. The coax cable must be connected to the lightning protector

(supplied) in the most direct fashion possible, and the lightning
protector must be grounded. We recommend that this ground be
interconnected to the antenna’s tower ground.
It is very important that the lightning protector be grounded to a low

impedance (low R and low L) ground system.
One possible installation is shown in Figure C-1 on page C-2.
Figure C-1. GPS Installation Requirements
The following items are included as part of the Ixia package:

• The GPS Antenna
• GPS Cables (1 long and 1 short)
• Lightning Protector
• The PVC Strut
• Two metal clamps
The placement and construction illustrate many of the recommendations found in

this section.
C-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Roof Mount Antenna
Conduit We recommend the coax from the GPS antenna to the Ixia unit to be installed in
a secure conduit from the point directly above the chassis to the GPS antenna.
The conduit serves two purposes:
1. It protects the coax cable.
2. It provides a rigid mast on which the GPS can be mounted.
Conduit Type
The GPS conduit should be 2-inch PVC. Installation of the coaxial cable is
uncomplicated within the pipe. There should be no more than four 90-degree
bends between pull boxes.
Coaxial Bending Radius
The coaxial cable should be run as straight as possible to meet the manufacturer
phase stability. The coaxial cable may have a greater than 1in (25.4 mm) bending
radius.
Figure C-2. Coaxial Bending Radius
In order to go around a corner a conduit that has less than the required bending
radius, it would be necessary to use either a junction box with an accessible
elbow installed at each 90-degree turn or two 45-degree elbow connected with a
piece of straight pipe. A 2-inch conduit only requires one 90-degree elbow to
make the correct bending radius around a 90-degree turn.
Lightning Protection Lightning protection for the installation is required. The lightning protector
must be correctly grounded to function properly. It must be connected to a low

C Roof Mount Antenna
impedance (low R and low L) ground system. We recommend that this ground be
interconnected to the tower ground and power ground to form one system.
Note: When attaching to the grounding stud (M8), use a maximum of

88.5 lbf-in. (10 N-m) of torque.
The earth ground electrode should be driven in at least 8 ft. (2.44m) into the
earth. A #6 grounding wire should be used.
GPS Mast Location Preferred Location

Requirements
The preferred mounting location for the GPS antenna is an unobstructed 360-
degree view of the sky above the horizon. The specific requirements are:
Table C-2. GPS Mast Preferred Location Requirements
1. Optimal view of the sky.
2. Not the highest point of the building so as to reduce the possibility of

lightning strikes.
3. Located at least 12 ft. from any large metal objects.
4. Located at least 10 ft. from any other GPS antenna.
5. Located within 30 ft. of where the coax cable enters the building.
6. The GPS antenna mast should be mounted at least 4 feet higher

than the highest horizontal reflective surface such as roof top
mounted AC units.
Requirements if Preferred Location is Not Available
If an unobstructed 360-degree view of the sky is not available then the following
requirements should be met:
Table C-3. GPS Mast Location Requirements if a Preferred Location is not
Available
1. 300-degree azimuth view of the sky.
2. No vertical obstructions to obscure the view of the antenna from the

horizon for more than 10 degrees.
3. No high-power radar signal beamed directly at the unit; this may

damage the pre-amplifier in the antenna.
4. No harmonics from a high-power, broad band transmitter within a

few megahertz of the carrier frequency (1.575 GHz) should be
present. This may jam the GPS receiver.

Window Mount Antenna
Window Mount Antenna

The GPS chassis kit includes a window mount antenna. This antenna is capable
of operation in areas with a relatively unrestricted view of the sky, and low
background interference from other radiators.
Mounting
Mount the antenna on the metal frame of the window. The antenna should be no
lower than the lower edge of the glass. A 180-degree view of the sky is preferred,
with no buildings adjacent to the window.
In the absence of a metal window frame, a nine centimeter square metal plact can
be used to mount the antenna in a position above the window sill.

C Window Mount Antenna

Appendix D: Hot-Swap Procedure
D
Each Optixia chassis provides the ability of removing and reinstalling a Load
Module without requiring the removal of power from the rest of the chassis. The
operation of the OS or load modules installed in the chassis. The following
features are part of the installation/removal process:
• Remove Notification sent to you through IxServer and IxExplorer
• No impact on tests operating on other cards
• Safe power application/removal from the card interface
Legacy modules installed in the SFF adapter module can also be hot-swapped.
Note: The following guidelines should be applied when hot-swapping modules:

• Modules can be hot-swapped in and out of a chassis without impacting
server operation only if they are not currently being used to run a test.
• Do not add or remove more than one module at a time.
• Do not add or remove modules during IxServer start up—wait until LCD dis-
play shows ‘Server OK.’
• ‘In Use’ LED indicates the module is currently owned by an application. This
is to warn of hot-swapping conflicts.
Load Module Hot-Swap Insertion

The process of insertion of a Load Module causes the slot location to apply
power to the Load Module and determine that there is no immediate fault
condition. The presence of a Load Module in a slot is flagged to IxServer. Upon
recognition of a Load Module's presence, IxServer determines if the Load
Module is a supported type. All supported types shall be loaded automatically. In
all cases, once IxServer has determined the presence of a Load Module in a slot,
IxExplorer represents the Load Module as present and advertises the type. For
unsupported Load Modules, the module type is shown and is indicated as
unsupported in the IxExplorer GUI as long as it resides in a slot.
To insert a load module:
Ixia Platform Reference Guide, Release 6.60 EA Patch1 D-1

D Load Module Hot-Swap Removal
1. Carefully slide the load module along the chassis slot runners until it clicks
into place. Ensure that it is firmly connected to the backplane.
2. Secure the holding screws. Be careful not to over tighten the screws.
Note: You should not hot-swap more than one load module at a time into a
powered Optixia chassis.
Load Module Hot-Swap Removal

The removal of a load module does not impact the operation of other Load
Modules in the chassis with respect to power or independent operation. In the
event that an application is using the Load Module, the application operations for
that Load Module are terminated and a message is sent to you. In the event that
inter-board operations are enabled, the other Load Modules interfacing the
removed Load Module are notified of its absence and are instructed to terminate
operations to the removed Load Module.
To remove a load module:

1. Loosen the holding screws.
2. Disconnect the load module from the backplane and remove it from the
chassis. Be sure to use correct ESD handling procedures at all times.
Note: You should not hot-swap more than one load module at a time into a
powered Optixia chassis.

starting from the low-number slots (slot 1, 2, 3), then working upward toward the
higher-numbered slots, until the problem is solved.
D-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

IP Port Assignments on
Appendix E:
E Ixia Chassis and Linux

port CPUs
Applicability
The information in this bulletin applies to:
• All Ixia chassis
• All Load Modules with embedded Linux port CPUs
Services on Ports
The following table lists the services assigned to IP ports on Ixia chassis and port
CPUs as of May 10, 2012. Services listed in the Used on Chassis column are
accessed through the chassis management port (the NIC located in the rear of the
chassis). Services listed in the Used on Port CPU column are accessed through
the test ports.
Note: Do not expose any port on an Ixia chassis to an untrusted network.
Connections are initiated in the following directions:

Table E-1. Port Directions
Port Direction
2809 – 2825 client<- ->chassis
2809 – 2825 client<- ->chassis
All others client ->chassis
Ixia Platform Reference Guide, Release 6.60 EA Patch1 E-1

E Services on Ports
Table E-2. Services assigned to Ports
Port Use TCP UDP Used on Used on Port IxOS 5.30 and
Chassis CPU later
9 Discard service X X X X
21 FTP daemon X X
22 SSH (IxLoad) X X
23 Telnet daemon X X X
58 Reserved X X X
80 HTTP, License X X (IxSAN) X X

Management,
IxSAN
103 PIM daemon X X X X

(test port only)
111 Sun RPC portmap X X X X
123 NTP X X X X
125 Private NTP X X X
135 Windows COM X X X X

services
179 BGP daemon X X X

(test port only)
445 Windows COM X X X X

services
797 – 800 NFS mounts X X X
1024 – ? Windows X X X X
MStask.exe
(Google for 'mstask
vulnerability' for
details)
1080 SOCKS proxy X X X
2048 Service X X X
management
2049 NFS X X X X X
2050 – 2111 Service X X X

management
2600 – 26991 Ixia reserved X X X
2705 IxVPN X X X
2782 CliX X X X
2809 – 2825 Aptixia CORBA X X X
E-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Services on Ports
Chassis CPU later
3222 File Cabinet port X X X X
3600 – 39991 Ixia reserved X X X
3705 IxVPN X X X
4501 Licence X X X
Management
4555 IxTclServer X X X
4900 VNC X X X
5285 IxServer status X X X

connection to
IxDodServer
5286 IxServer X X X
connection to
IxAdmin
5555 IxVPN X X X
6001 Service manager X X X X
6002 Capture service X X X
6003 Capture service X X X

relay
6004 Download on X X X X
Demand broadcast
data
6005 Download on X X X
Demand server
6101 IxNetwork X X X
6809 – 6825 Aptixia / CORBA X X X
6665 InterfaceManager X X X
(IxAuthenticate &
IxAccess)
7768 RPF Impairment X X X X
8003 IxAuthenticate X X X
8008 IxNetwork X X X
8881 CP/DP X X X
9101 – 9102 Statistics engine X X X X

(Statengine)
9613 – 9676 Service X X X X

management
9888 OTN X X X
Ixia Platform Reference Guide, Release 6.60 EA Patch1 E-3

E Services on Ports
Chassis CPU later
10115 IxChariot X X X X
17668 IxServer X X X
17669 (4505h) IxServer X X X
17670 (4506h) Statistics watch X X X
17671 (4507h) Protocol watch X X
17672 (4508h) Port CPU message X X X

queue
17674 (450Ah) Logcollector X X X
17777 (4571h) Port CPU serial X X X

console
26999 – 27009 License X X X

Management pre-
2.40SP1
(if license server is
running on chassis)
27000 License X X X
Management
2.40SP1 and later
(if license server is
running on chassis)
32769 mountd X X X
32800 – 32816 IxVPN CORBA X X X
38001-38096 IxSAN X X X
54321 IxVPN X X X
Legend for Chart

• Blank = not supported or not applicable
• X = supported feature
More Information
For more information, contact Ixia Technical Support:
Phone (877) 367 – 4942, ext. 1
Fax (818) 444 – 3101
Email: support@ixiacom.com
E-4 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Appendix F: Laptop Controller
F The Laptop Controller supports the following Ixia applications:
•
•
•
IxNetwork
IxN2X
IxLoad
• IxAutomate
• IxANVL
• IxOS
The Laptop Controller has a dual-use operation similar to the IxN2X Controller
and the Ixia Application Server. So we do not require simultaneous operation for
these two.
Specifications
The following table lists the sspecifications of the Laptop Controller.:
Table F-1. Laptop Controller Specifications
Specifications Details
Supported Configurations 1 heavy user (complex and high scale

configurations)
Base Unit Dell Latitude E6430n (225-3543)
Processor 3rd gen Intel Core i5-3210M

Processor (2.5GHz, 3M cache), Dell
Latitude E6X30 (317-9440)
RAM 8.0GB, DDR3-1600MHz SDRAM
Hard Drive 750 GB, 7200 RPM
Ports 2 LAN Ports (10/100/1000-Base-T)
Keyboard Internal English Keyboard
Monitor 14.0" HD (1366x768) Anti-Glare LED-

backlit
Graphics Intel HD Graphics 4000
Ixia Platform Reference Guide, Release 6.60 EA Patch1 F-1

F Specifications
Table F-1. Laptop Controller Specifications
Specifications Details
Performance Multi-core / Hi-performance
Life Cycle Projected life-cycle of at least 2 years

(2 years before EOL date by the
manufacturer)
Some of the other specifications of the Laptop Controller are as follows:

• Documentation (English/French)
• Tech Setup Guide, English
• No Dell ControlVault, No Fingerprint Reader, No Smartcard Reader and No
Contactless Smartcard Reader
• Windows OS
• Ixia Label
• Dell Wireless 380 Bluetooth 4.0 LE Module
• No Modem
• No Modem for Latitude E-Family
• US - 3 foot Flat Power Cord
• 90W 3-Pin, AC Adapter
• 8X DVD+/-RW
• 8X DVD+/-RW Bezel
• Noise Cancelling Digital Array Microphone
• Dell Wireless 1504 802.11g/n Single Band Wi-Fi Half Mini-card
• No Intel vPro Technology Advanced Management Features
• 6-Cell (60WH) Primary Lithium Ion Battery, (2.8Ah) ExpressCharge
F-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Index
Numerics BGP 3-1
10 Gigabit Ethernet BGP4 3-8
Ports 2-15 External 3-8
Internal 3-8
10GE BERT 23-1, 24-1 RFC 1771 3-8
10GE LAN 23-1, 24-1 RFC 2547 3-12
10GE Load Modules 23-1, 24-1 Bit Error Rate Test (BERT) 2-45
10GE WAN 23-1, 24-1 Border Gateway Protocol 3-8
10Gigabit 23-1, 24-1 Bursts 2-50
2x Fibre Channel 2-21 Continuous 2-49
A C
AAL5 2-42 Capture
Continuous 2-67
Advance to Next Stream 2-50
Filter 2-66
Advanced Streams Trigger 2-66
Scheduling 2-48
Cards 2-8, 2-79
Alerts 2-83
CDL 2-33
Area ID 3-5
Channelized SONET 2-22
ARP 3-1, 3-2
Chassis 2-4, 2-79
Asynchronous Transfer Mode (ATM) 2-41
Chassis Chain 2-2, 2-78
ATM 2-41, 3-34 Sync-In 2-2
Adaptation Layer 5 2-42 Sync-Out 2-2
LLC/NLPID 2-41
LLC/SNAP 2-41 Chassis chain
timing specification 2-4
OC-12c 2-41
OC-3c 2-41 cHEC 2-30
RFC 2684 3-47 CID 2-30
Statistics 2-76 CLNP 3-17
Auto Negotiation 2-10 clock in/out NGY 24-14
Available/Unavailable Seconds 2-46 cluster-list 3-8
B community 3-9
BERT 2-22, 2-45 Concatenated SONET 2-22
Statistics 2-77 confederation 3-8
Ixia Platform Reference Guide, Release 6.60 EA Patch1 Index-1

Index
Connection Identification 2-30 fault handling, NGY 24-20

Continuous Bursts 2-49 FCM 32-1, 33-1
Continuous Capture 2-67 FCM Part Numbers 32-2, 33-3
FCM ports per chassis 32-2
Continuous Packets 2-49
FCM Specifications 32-2, 33-4
Converged Data Link 2-33 FCM Statistics 32-4
cooling fan, XM12 4-13, 6-15 FCMGXM 32-1
cooling fan, XM2 5-15 FCM Part Numbers 32-2, 33-3
Core Header Error Check (cHEC) 2-30 FCM ports per chassis 32-2
Counted Burst 2-49 FCM Specifications 32-2, 33-4
Counter Mode UDF 2-56 FCM statistics 32-4
CSNP 3-18 FCMGXM 32-1
Cut Through Latency 2-72 FCoE Initialization Protocol 3-40
FCoE statistics B-160
D FCS 2-31
Data Communication Channel (DCC) 2-22, 2-25 Fibre Channel 2-21
Data Generators 2-52 FIP 3-40
Data Integrity 2-74 FIP statistics B-161
Statistics 2-76
Flow Control 2-79
Data Link Layer 2-52
Flows 2-47, 2-48
Data Patterns 2-52
Forced Collisions 2-69
DCC 2-22, 2-25 Operation 2-68
Dead interval 3-18 Frame Check Sequence (FCS) 2-31, 2-52
Default Gateway 3-3 Frame Data 2-51
Designated IS 3-18 Data Generators 2-52
Device Under Test (DUT) 2-4 Data Patterns 2-52
Frame Identity Record (FIR) 2-52
DHCPv6 3-58
Frame Size 2-51
DLL 2-86 High speed 32 bit counters 2-52
Dual ISIS 3-17 MAC Addresses 2-51
DUT 2-4 Preamble Size 2-51
Protocol Related Data 2-52
E Frame Identity Record (FIR) 2-52
EBGP 3-8 Frame Relay 2-22, 2-39, 3-34
Egress LSRs 3-20, 3-21 Frame Size 2-51
eHEC 2-30
G
Encapsulations 2-41
GBIC 2-10
Errors
Insertion 2-22, 2-24 Generic Framing Procedure (GFP) 2-22, 2-29
ES 3-18 Generic Routing Encapsulation, GRE 3-53
Ethernet 2-10 GFP 2-22, 2-29
delta 2-32
Extended Reach 2-15
Frame Check Sequence (FCS) 2-31
Extension Header Error Check (eHEC) 2-30 Hunt 2-31
External BGP 3-8 Payload 2-30
Presync 2-31
F Scrambling 2-32
fan speed control, XM12 4-13, 6-15 Sync 2-32
Gigabit Ethernet 2-21
fan speed control, XM2 5-15
GPS 2-7
Index-2 Ixia Platform Reference Guide, Release 6.60 EA Patch1

Index
GPS Antenna, lightning protection C-3 Chassis Chain 2-78

GRE, Generic Routing Encapsulation 3-53 Multi-User Operation 2-81
Port 2-79
H Ports 2-79
Statistics Logging and Alerts 2-82
Half Duplex 2-68
Ixia Hardware 2-1
HDLC 2-22, 2-39 Chassis 2-4
Header 2-51 Chassis Chain 2-2
Hello interval 3-18 Load Modules 2-8
HELLO message 3-21 IxRouter Statistics 2-76
Hello PDU 3-18 IxServer 2-86, 2-87
I L
IBGP 3-8 Label Distribution Protocol 3-27
IGMP 3-1, 3-3 LAN 2-15
IIH 3-18 Latency 2-69, 2-76
Cut Through 2-72
Ingress LSRs 3-20, 3-21
Store and Forward 2-72
Integrated ISIS 3-17 Store and Forward Preamble 2-72
Inter-Arrival Jitter 2-72 Latency View 2-80
Inter-Burst Gaps (IBG) 2-50 Latency, intrinsic, adjusting 23-9, 24-21
Intermediate Reach 2-22 Layouts 2-80
Intermediate System to Intermediate System (ISIS) 3- LCP 2-33, 2-34
17
LDP 3-2, 3-27
Internal BGP 3-8 RFC 3031 3-27
Internet Group Management Protocol (IGMP) 3-3 RFC 3036 3-27
Internet Protocol Control Protocol (IPCP) 2-36 lightning protection C-3
Inter-Packet Gaps (IPG) 2-51 Line Overhead (LOH) 2-23
Inter-Stream Gaps (ISG) 2-50 Link Alarm Status Interrupt (LASI) 2-19
Intrinsic Latency Adjustment 23-9, 24-21 Link Control Protocol (LCP) 2-33, 2-34
IP protocol server support 3-2 Link Fault Signaling 2-18
IP/UDP/TCP Checksum Verification Statistics 2-76 Link Quality Monitoring 2-33
IPCP 2-36 LLC Bridged Ethernet 2-41
IPv4 2-36 Load Modules 2-8
IPv6 2-36
LOH 2-23
IPv4 Counter Mode 2-62
Long Reach 2-15, 2-22
IS 3-18
LQM 2-33
ISIS 3-1, 3-17
ISO 10589 3-17, 3-18 LSP 3-18
RFC 1195 3-17 LSP Tunnel 3-21
RFC 2966 3-17
ISO 10589 3-17, 3-18 M
ITU-T I.363.5 2-42 MAC 2-51
IxExplorer MACsec statistics B-160
Operation 2-81 Magic Number 2-36
Ports 2-9 Maximum Receive Unit (MRU) 2-34
Software 2-78
MII Templates 2-80
IxExplorer Software 2-78
Minimum Flag 2-51
Cards 2-79
Chassis 2-79 MLD 3-2, 3-28

Index
RFC 2710 3-28 Pause Transmit 2-66

RFC 3810 3-28 Payload Length Indicator (PLI) 2-30
MPLS 3-2, 3-20, 3-34 PCPU 2-10
MPLS Network Control Protocol 2-37 PCS lane
MPLSCP 2-37 configuration and skew 23-10
MRU 2-34 PD 2-11
MT-RJ Fibre 2-10 PDU 3-18
Multicast Listener Discovery 3-28 PESQ speech quality analysis 4-19
Multiple Clients 2-87 PFC 3-40
Multi-User PIM 3-29
Operation 2-81 PIM-SM 3-2
Platform 1-1
N
PLI 2-30
NCP 2-33, 2-36
PoE 2-10
Nested Counter Mode UDF 2-60
POH 2-24
Network Control Protocol (NCP) 2-33, 2-36
Port assignments on ixia chassis E-1
NGY fault handling 24-20
Port Capture Operations 2-68
O Start Capture 2-68
Start Collision 2-68
OC-12c 2-21, 2-41 Start Latency 2-68
OC-192c 2-21 Stop Capture 2-68
OC-3c 2-21, 2-41 Stop Collision 2-68
Stop Latency 2-68
OC-48c 2-21
Port CPU 2-10
OC-48c VAR 2-22
Open Shortest Path First (OSPFv2) 3-4 Port Data Capture 2-66
Port Groups 2-80
Open Shortest Path First Version 3 (OSPFv3) 3-7
Port Hardware 2-9
originator-id 3-8
OSI Network Layer Control Protocol 2-37 Port Properties 2-79
Port Statistics 2-76
OSINLCP 2-37
ATM 2-76
OSPFv2 3-1, 3-4 BERT 2-77
OSPFv3 3-1, 3-7 Data Integrity 2-76
RFC 2740 3-7 IP/UDP/TCP Checksum Verification 2-76
IxRouter 2-76
P Packet Groups 2-76
Packet Groups 2-66 Quality of Service 2-76
Operation 2-69 SONET Extended 2-76
Statistics 2-76 Temperature Sensors 2-77
User Defined 2-76
Packet over Sonet 3-1 VSR 2-76
Packet over SONET (POS) 2-21 Port Transmit Capabilities 2-47
Packet Size 2-67 Ports 2-79
Packets 2-51 Groups 2-80
Continuous 2-49 Types 2-9
PATH message 3-21 Power over Ethernet (PoE) 2-10
PATH Messages 3-22 Power Sourcing Equipment (PSE) 2-10
Path Overhead (POH) 2-24 Powered Device (PD) 2-11
PATH_ERR message 3-21 PPP 2-22, 2-33
Pause Control 2-10 Configure-ACK 2-34
Configure-NAK 2-34

Index
Configure-Reject 2-34 RMII 2-10

Preamble Size 2-51 Round Trip TCP Flows 2-75
Priority-based Flow Control 3-40 route coloring 3-9
Protocol Data Unit 3-18 route reflection 3-8
Protocol Independent Multicast - Sparse Mode 3-29 Router ID 3-5
Protocol-Specific Data 2-52 Routing Information Protocol - Next Generation 3-16
PSE 2-10 RPR 2-22
PSNP 3-18 Fairness Algorithm 2-27
Fairness Frames 2-27
Q Operations, Administration and Management 2-29
Protection Switching Message 2-29
Quality of Service Topology Discovery 2-28
Statistics 2-76 Topology Discovery Message 2-28
Topology Extended Status Message 2-28
R
RSVP-TE 3-2, 3-20
Random Mode UDF 2-57 Fast Reroute 3-25
Range List Mode UDF 2-59 RTP
Reach 2-15, 2-22 on ACCELERON 22-2
Real-Time Latency 2-69 Real-time Transport Protocol 22-2
Receive Mode 2-66 RTTCP 2-75
Reduced features, load module 1-6
S
Reset Sequence Index 2-73
SC 2-10
Resilient Packet Ring (RPR) 2-22, 2-26
Section Overhead (SOH) 2-23
Resource Reservation Protocol - Traffic
Sequence Checking
Engineering 3-20
Operation 2-73
RESV message 3-21
Sequence Number PDU 3-18
Return to First for Count 2-50
Services on ports E-1
Return to ID 2-50
Short Reach 2-15, 2-22
RFC 1112 3-3
SNP 3-18
RFC 1195 3-17
SOH 2-23
RFC 1771 3-8
SONET
RFC 2080 3-16 Extended Statistics 2-76
RFC 2236 3-3 SONET/POS 2-21
RFC 2328 3-4 2x Fibre Channel 2-21
RFC 2547 3-12 Fibre Channel 2-21
Gigabit Ethernet 2-21
RFC 2684 3-47
OC-12c 2-21
RFC 2710 3-28 OC-192c 2-21
RFC 2740 3-7 OC-3c 2-21
RFC 2966 3-17 OC-48c 2-21
RFC 3031 3-27 Spatial Reuse Protocol (SRP) 2-25
RFC 3036 3-27 speech quality analysis 4-19
RFC 3376 3-3 SRP 2-25
RFC 3810 3-28 Staggered Start Transmit 2-65
RIP 3-1, 3-14 Start Capture 2-68
RIPng 3-1, 3-16 Start Collision 2-68
RFC 2080 3-16 Start Latency 2-68
RJ-45 2-10 Start Transmit 2-65

Index
Statistic View 2-80 Capture Filter B-11

Statistics Capture State B-12
Alignment Errors B-18 Capture Trigger B-11
ALM, ELM, CPM B-161 CDL Error Frames Received B-24
Asynchronous Frames Sent B-15 CDL Good Frames Received B-24
ATM AAL5 Bytes Received B-28 Collision Frames B-18
ATM AAL5 Bytes Sent B-28 Collisions B-18
ATM AAL5 CRC Error Frames B-29 CPU DoD Status B-12
ATM AAL5 Frames Received B-29 CPU Status B-12
ATM AAL5 Frames Sent B-29 CRC Errors B-18, B-19
ATM AAL5 Length Error Frames B-29 Cumulative Service Disruption Time B-24
ATM AAL5 Timeout Error Frames B-29 Custom Ordered Sets Received B-28
ATM Cells Received B-29 Custom Ordered Sets Sent B-28
ATM Cells Sent B-29 Data Integrity Errors B-13
ATM Corrected HCS Error Count B-29 Data Integrity Frames B-13
ATM Idle Cell Count B-29 DCC Bytes Received B-24
ATM Scheduled Cells Sent B-29 DCC Bytes Sent B-24
ATM Uncorrected HCS Error Count B-29 DCC CRC Receive Errors B-24
ATM Unregistered Cells B-29 DCC Frames Received B-24
Background Chip Temperature B-25 DCC Frames Sent B-24
BERT Available Seconds B-23 DCC Framing Errors Received B-24
BERT Background Block Error Ratio B-23 DHCPv4 ACKs Received B-15
BERT Background Block Errors B-23 DHCPv4 Addresses Learned B-15
BERT Bit Error Ratio B-22 DHCPv4 Discovered Messages Sent B-15
BERT Bit Errors Received B-22 DHCPv4 Enabled Interfaces B-15
BERT Bit Errors Sent B-22 DHCPv4 NACKs Received B-15
BERT Bits Received B-22 DHCPv4 Offers Received B-15
BERT Bits Sent B-22 DHCPv4 Releases Sent B-15
BERT Block Error State B-23 DHCPv4 Requests Sent B-15
BERT Elapsed Test Time B-23 DHCPv6 Addresses Learned B-15
BERT Error Free Seconds B-23 DHCPv6 Advertisements Received B-15
BERT Errored Blocks B-22 DHCPv6 Declines Received B-15
BERT Errored Second Ratio B-22 DHCPv6 Enabled Interfaces B-15
BERT Errored Seconds B-22 DHCPv6 Releases Sent B-15
BERT Mismatched Ones Ratio B-23 DHCPv6 Replies Received B-15
BERT Mismatched Zeros Ratio B-23 DHCPv6 Requests Sent B-15
BERT Number Mismatched Ones B-23 DHCPv6 Solicits Sent B-15
BERT Number Mismatched Zeros B-23 DMA Chip Temperature B-25
BERT Severely Errored Second Ratio B-23 Dribble Errors B-18
BERT Severely Errored Seconds B-23 Dropped Frames B-28
BERT Status B-22 Duplex Mode B-12
BERT Unavailable Seconds B-23 Ethernet CRC B-30
BGP Sessions Configured B-16 Excessive Collision B-19
BGP Sessions Established B-16 FCoE B-160
Big Sequence Errors B-14 FEC Corrected 0s Count B-24
Bits Received B-12 FEC Corrected 1s Count B-24
Bits Received Rate B-12 FEC Corrected Bits Count B-25
Bits Sent B-12 FEC Corrected Bytes Count B-25
Bits Sent Rate B-12 FEC Uncorrectable Subrow Count B-25
Byte Alignment Error B-19 FIP B-161
Bytes from Port 2 B-31 Flow Control Frames B-18
Bytes from Port 3 B-31 Fom Board Temperature B-25
Bytes Received B-12 Fom Internal Temperature B-25
Bytes Received Rate B-12 Fom Port Temperature B-25
Bytes Sent B-12 Fragments B-17
Bytes Sent Rate B-12 Framer Abort B-13
Capture Chip Temperature B-25 Framer CRC Errors B-13

Index
Framer Frames Received B-13 OAM Rx Fault Management CC B-30

Framer Frames Sent B-13 OAM Rx Fault Management LB B-30
Framer Max Length & Rate B-13 OAM Rx Fault Management RDI B-29
Framer Min Length & Rate B-13 OAM Rx Good Cells B-29
Frames Received with /E/ error Character B-28 OAM Tx Bytes B-29
Frames Received with Coding Errors B-28 OAM Tx Cells B-29
Frames Sent B-12 OAM Tx Fault ActDeact CC B-29
Frames Sent Rate B-12 OAM Tx Fault Management AIS B-29
Front End Chip Temperature B-25 OAM Tx Fault Management CC B-29
GFP eHEC Errors B-22 OAM Tx Fault Management LB B-29
GFP Idle Frames B-22 OAM Tx Fault Management RDI B-29
GFP Payload FCS Errors B-22 OSPF Neighbors in Full State B-17
GFP Receive Bandwidth B-22 OSPF Total Sessions B-17
GFP Sync State B-22 Overlay Chip Temperature B-25
GFP SYNC/HUNT Transitions B-22 Oversize B-18, B-19
GFP tHEC Errors B-22 Packets from Application B-30
Input Signal Strength B-20 Packets from Port 3 B-31
Insertion State B-24 Packets Skipped In Packet Group Mode B-14
IP Checksum Errors B-13 Path AIS B-19
IP Packets Received B-13 Path AIS Alarmed Seconds B-20
ISIS L1 Sessions Configured B-16 Path AIS Unavailable Seconds B-20
ISIS L1 Sessions Up B-16 Path BIP Errored Seconds B-20
ISIS L2 Sessions Configured B-16 Path BIP(B3) B-19
ISIS L2 Sessions Up B-16 Path LOP B-19
IxRouter Receive B-14 Path PLM(C2) B-20
IxRouter Transmit B-14 Path RDI B-19
Last Service Disruption Time B-24 Path RDI Unavailable Seconds B-20
Late Collisions B-18 Path REI B-19
Latency Chip Temperature B-25 Path REI Errored Seconds B-20
LDP Basic Sessions Up B-17 Pause Acknowledge B-28
LDP Sessions Configured B-17 Pause End Frames B-28
LDP Sessions Up B-17 Pause Overwrite B-28
Line AIS B-19 Pause State B-12
Line AIS Alarmed Seconds B-20 PIM-SM Learned Neighbors B-17
Line BIP Errored Seconds B-20 PIM-SM Routers Configured B-17
Line BIP(B2) B-19 PIM-SM Routers Running B-17
Line Error Frames B-19 Plm Internal Chip Temperature B-25
Line Errors B-18 Plm Internal Chip Temperature 1 B-25
Line RDI B-19 Plm Internal Chip Temperature 2 B-25
Line RDI Unavailable Seconds B-20 PoE Active Input B-30
Line REI Errored Seconds B-20 PoE Amplitude Arm Status B-30
Line REI(FEBE) B-19 PoE Amplitude Done Status B-30
Line Speed B-12 PoE Amplitude Time Status B-30
Link Fault State B-24 PoE AutoCalibration B-30
Link State B-11 POE Input Current B-30
Local Faults B-24 POE Input Power B-30
Local Ordered Sets Received B-28 POE Input Voltage B-30
Local Ordered Sets Sent B-27 POE Status B-30
MACsec B-160 PoE Temperature B-30
Max Service Disruption Time B-24 PoE Trigger Amplitude DC Amps B-30
Min Service Disruption Time B-24 PoE Trigger Amplitude DC Volts B-30
MLD Frames Transmitted B-17 Port CPU Frames Sent B-15
MLD Frances Received B-17 POS K1 Byte B-21
OAM Rx ActDeact CC B-30 POS K2 Byte B-21
OAM Rx Bad Cells B-30 Power Over Ethernet B-30
OAM Rx Bytes B-29 Quality of Service B-13
OAM Rx Fault Management AIS B-29 Quality of Service Rate B-13

Index
Receive Arp Reply B-14 SRP Header Parity Errors B-21

Receive Arp Request B-14 SRP IPS Frames Received B-21
Receive Ping Reply B-14 SRP Usage Frames Received B-21
Receive Ping Request B-15 SRP Usage Frames Sent B-21
Received IGMP Frames B-16 SRP Usage Status B-21
Remote Faults B-24 SRP Usage Timeouts B-21
Remote Ordered Sets Received B-28 Stream Extraction Module B-30
Remote Ordered Sets Sent B-28 TCP Checksum Errors B-13
Reverse Sequence Errors B-14 TCP Packets Received B-13
RPR Data Frames Received B-21 Total Sequence Errors B-14
RPR Discovery Frames Received B-21 Transmit Arp Reply B-14
RPR Fairness Frames Received B-21 Transmit Arp Request B-14
RPR Fairness Frames Sent B-21 Transmit Duration B-13
RPR Fairness Timeouts B-21 Transmit Ping Reply B-15
RPR Header CRC Errors B-21 Transmit Ping Request B-15
RPR Idle Frames Received B-22 Transmit State B-12
RPR OAM Frames Received B-21 Transmitted IGMP Frames B-16
RPR Payload CRC Errors B-22 Tx Hardware Error Counter B-27
RPR Protection Frames Received B-22 Tx Out Of Frame Counter B-27
RSVP Egress LSPs Up B-17 UDP Checksum Errors B-13
RSVP Ingress LSPs Configured B-17 UDP Packets Received B-13
RSVP Ingress LSPs Up B-17 Undersize B-18
Rx Channel Protection Disabled B-26 User Defined Stats B-11
Rx Channel Skew Error B-26 User Defined Stats 5 and 6 B-11
RX Channel Skew First B-26 User Defined Stats 5 and 6 Rate B-11
Rx Channel Skew Last B-26 Valid Frames Received B-12
Rx Channel Skew Max B-26 Valid Frames Received Rate B-12
Rx Channel Swapped B-26 VLAN Dropped Frames B-14
Rx Code Word Violation Counter B-27 VLAN Tagged Frames Received B-18
Rx Code Word Violation Error B-26 Statistics Logging and Alerts 2-82
Rx CRC Corrected Errors B-26
Rx CRC Correction Disabled B-26 Step Stream 2-66
Rx CRC Error B-26 Stop After Stream 2-49
Rx CRC Error Counter B-27 Stop Capture 2-68
Rx CRC Uncorrected Errors B-26 Stop Collision 2-68
Rx Hardware Error B-26
Rx Loss Of Synchronization Counter B-26 Stop Latency 2-68
Rx Loss Of Synchronization Status B-27 Stop Transmit 2-65
Rx Multi-loss Of Synchronization Counter B-26 Store and Forward Latency 2-72
Rx Multi-loss Of Synchronization Status B-27 Preamble 2-72
Rx Out of Frame Counter B-27 Stream Control
Rx Out of Frame Status B-27
Advance to Next Stream 2-50
Rx Section BIP Error Counter B-27 Bursts 2-50
Scheduled Frames Sent B-15 Continuous Bursts 2-49
Scheduled Transmit Time B-12
Continuous Packets 2-49
Scheduler Chip Temperature B-25
Counted Burst 2-49
Section BIP Errored Seconds B-20
Inter-Burst Gaps 2-50
Section BIP Severely Errored Seconds B-20
Inter-Packet Gaps 2-51
Section BIP(B1) B-19
Inter-Stream Gaps 2-50
Section LOF B-19
Packets 2-51
Section LOS B-19
Return to First for Count 2-50
Section LOS Seconds B-20
Return to ID 2-50
Sequence Errors B-14 Stop After Stream 2-49
Sequence Frames B-13
Small Sequence Errors B-14 Stream Queues 2-49
SRP Data Frames Received B-21 Stream Statistic View 2-80
SRP Discovery Frames Received B-21 Streams 2-47

Index
Synchronous Payload Envelope (SPE) 2-24 voice quality analysis 4-19

Sync-In 2-2 VSR Statistics 2-76
Sync-Out 2-2
W
T WAN 2-15
Table Mode UDF 2-63 Wide Packet Groups 2-69
Tcl-DP Server 2-87 Windows (Microsoft) 2-4
TclHAL 2-86, 2-87
X
Temperature Sensor Statistics 2-77
XAUI 2-15, 2-16
tHEC 2-30
xdensity 34-1, 34-2
Theory of Operation 2-1, 3-1
XDM10G32S 34-1, 34-2
Time and Frequency Module A-1
XDM10G32S 14-1, 15-1, 34-1, 34-2
Timing specification XDM10G32S Part Numbers 14-3, 15-5, 34-4
chassis chain 2-4 XDM10G32S Specifications 14-4, 15-9, 34-5
TOH 2-24 XDM10G32S Part Numbers 14-3, 15-5, 34-4
Transmit Modes 2-49 XDM10G32S Specifications 14-4, 15-9, 34-5
Transmit Operations 2-65 XENPAK 2-15
Pause Transmit 2-66
Staggered Start Transmit 2-65
Start Transmit 2-65
Step Stream 2-66
Stop Transmit 2-65
Transport Overhead (TOH) 2-24
Trigger Capture 2-67
Tx Out of Frame Status B-27
Tx Section BIP Error Counter B-27
Type Header Error Check (tHEC) 2-30
Type-3 2-9
Type-M 2-9
U
UDFs 2-55
Counter Mode 2-56
IPv4 Counter Mode 2-62
Nested Counter Mode 2-60
Random Mode 2-57
Range List Mode 2-59
Table Mode 2-63
Value List Mode 2-58
UDSs 2-76
User Defined Fields (UDF) 2-55
User Defined Statistics (UDS) 2-76
V
Value List Mode UDF 2-58
Variable Clocking 2-22
VC Mux Bridged Ethernet 2-41
VC Mux Routed 2-41
virtual chassis chain 2-6

Index

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ii Ixia Platform Reference Guide, Release 6.60 EA Patch1

Change: 4150211, Date: September 24, 2013

Ixia Platform Reference Guide, Release 6.60 EA Patch1 iii

About This Guide

Chapter 1 Platform and Reference Overview

Ixia Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Ixia Load Module Properties . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Card Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Ixia Platform Reference Guide, Release 6.60 EA Patch1 v

Maximum number of PGIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

New in Version 6.60 EA Patch1 . . . . . . . . . . . . . . . . . . . . . 1-29

Chapter 2 Theory of Operation: General

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Ixia Platform Reference Guide, Release 6.60 EA Patch1 vii

IxExplorer Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

Tcl Software Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85

Chapter 3 Theory of Operation: Protocols

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Multicast VPNs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

FCoE and NPIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

Precision Time Protocol (PTP) IEEE 1588v2. . . . . . . . . . . 3-41

ATM Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

x Ixia Platform Reference Guide, Release 6.60 EA Patch1

Generic Routing Encapsulation (GRE) . . . . . . . . . . . . . . . . 3-53

DHCP Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57

DHCPv6 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58

Ethernet OAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59

Chapter 4 Optixia XM12 Chassis

Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

SFF Adapter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Cooling Fan Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

XM12 Sound Reducer Installation. . . . . . . . . . . . . . . . . . . . 4-15

Install XM12 Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Rack Mount Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

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High Performance Upgrade Kit . . . . . . . . . . . . . . . . . . . . . 4-18

Chapter 5 Optixia XM2 Chassis

Rack Mount Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

SFF Adapter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

.Cooling Fan Speed Control. . . . . . . . . . . . . . . . . . . . . . . . 5-15

Chapter 6 XG12 Chassis

Chapter 7 XGS12 Chassis

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CPU Slot LED Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11

Chapter 8 Optixia X16 Chassis

Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Rack Mount Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

Chapter 9 Optixia XL10 Chassis

Hot-Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Rack Mount Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Chapter 10 IXIA 1600T Chassis

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Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

Rack Mount Cautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Chapter 11 IXIA 400T Chassis

Use of Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Rack Mount Cautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

Chapter 12 IXIA 400T v2 Chassis

Use of Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

Rack Mount Cautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

Chapter 13 IXIA 250 Chassis

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Chapter 14 Ixia 100 Chassis

IXIA 100 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2