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Verilog HDL - 18ec56 Assignment

The document contains details of assignments for a Verilog HDL course divided into 5 modules. The modules cover topics like design flows, abstraction levels, modeling styles, module definitions, tasks, gates, adders, multiplexers, flip-flops, synthesis and more. Students are asked to write code, explain concepts and provide examples for concepts like comments, data types, modules, conditional statements, loops, case statements, assign statements and modeling different digital components like adders and multiplexers at different levels of abstraction in Verilog.

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sureshfm1
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650 views

Verilog HDL - 18ec56 Assignment

The document contains details of assignments for a Verilog HDL course divided into 5 modules. The modules cover topics like design flows, abstraction levels, modeling styles, module definitions, tasks, gates, adders, multiplexers, flip-flops, synthesis and more. Students are asked to write code, explain concepts and provide examples for concepts like comments, data types, modules, conditional statements, loops, case statements, assign statements and modeling different digital components like adders and multiplexers at different levels of abstraction in Verilog.

Uploaded by

sureshfm1
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog HDL

ASSIGNMENTS
_____________________________________________________________________________
Module-1
1. Explain a typical design flow for designing VLSI IC circuits using the block diagram.
2. Explain the different levels of Abstraction used for programming in Verilog.
3. Explain a top-down design methodology and a bottom-up design methodology.
Explain the factors that have made Verilog HDL popular.

Module-2
3 a. Write a note on i) Comments ii) Number Specification iii) X and Z values and
iv) Identifiers and Keywords with suitable examples.
4. Explain a Components of a Verilog Module with a neat block diagram.
5. Explain $display and $monitor tasks with examples.
6. A 4-bit parallel shift register has I/O pins as shown in the figure below. Write the
module definition for this shift register. Include the list of ports and port declarations
(no need to show the internals).

Module-3
7. Explain the instantiation of gates by writing a gate level module by name gates
in Verilog.
8. Explain regular assignment delay in dataflow level of abstraction in Verilog.
9. The input output expressions for 1-bit Full Adder are given as sum= a ^ b^ c;
co= (a &b)|(b&c)|(c&a). Write the gate level abstraction of 1-bit Full Adder by
instantiating and, or, xor gates only.
10. Write the Verilog description of 4-bit Ripple carry Adder at Gate level abstraction.
11. Write a program for 4-to-1 Multiplexer, Using Conditional Operators in dataflow
level of abstraction in Verilog.
Module-4
12. Explain combined port declaration and combined ANSI C style port declaration
with examples in Verilog.
13. Explain the conditional statements in Verilog.
14. Write a behavioral 4 bit counter program in Verilog.
15. Explain different Loop statements in Verilog.
16. Write a Verilog behavioral 4 to 1 Multiplexer program using CASE statement.

Module-5
17. Using assign and deassign statements, design a positive edge-triggered Dflipflop
with asynchronous clear (q=0) and preset (q=1).
18. Using primitive gates, design a 1-bit full adder FA. Instantiate the full adder
inside a stimulus module. Force the sum output to a & b & c_in for the time
between 15 and 35 units.
19. Explain the Logic Synthesis Flow from RTL to Gates
20. A 1-bit full subtractor has three inputs x, y, and z (previous borrow) and two outputs
D(difference) and B(borrow). The logic equations for D and B are as follows:
D = x'y'z + x'yz' + xy'z' + xyz
B = x'y + x'z +yz
Write the Verilog RTL description for the full subtractor. Synthesize the full subtractor,
using any technology library available to you. Optimize for fastest timing. Apply identical
stimulus to the RTL and the gate-level netlist and compare the output.

STAFF INCHARGE: Prof. Suresh Murgod

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