Scribd
Upload
7K views6 pages

Problem Statement: Design of A Binary Divider

The document describes the design and implementation of an 8-bit binary divider using Verilog HDL. It includes the problem statement, design of the binary divider, Verilog code for the binary divider module, test bench code to simulate the divider, and results. The divider module takes 8-bit inputs for the dividend and divisor, and outputs the 8-bit quotient and remainder. It handles different cases such as when the divisor is zero.

Uploaded by

Samarth Sama
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
7K views6 pages

Problem Statement: Design of A Binary Divider

The document describes the design and implementation of an 8-bit binary divider using Verilog HDL. It includes the problem statement, design of the binary divider, Verilog code for the binary divider module, test bench code to simulate the divider, and results. The divider module takes 8-bit inputs for the dividend and divisor, and outputs the 8-bit quotient and remainder. It handles different cases such as when the divisor is zero.

Uploaded by

Samarth Sama
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
You are on page 1/ 6

 Problem Statement :-

Implement 8 bit binary divider using Verilog HDL. Simulate the


design and analyze the result.

 Design of a binary divider :-


We will consider the design of a binary divider for unsigned
binary numbers. As an example, we will design a circuit to divide an 8-bit
dividend by a 8-bit divisor to obtain a 8-bit quotient. The following example
illustrates the division process .let us consider 8 bit dividend (10000010)2 and 8
bit divisor (100000001)2 .

10000001) 10000010 (00000001 (quotient)

-10000001

= 00000001 (remainder)
 Verilog code for binary divider :-

module divider (a,b,quo,rem);


input [7:0] a;//dividend
input [7:0] b;//divisor
output [7:0] quo;//quotient
output [7:0] rem;//remainder
//declaring internal variable
reg [7:0] quo=0;//initially declaring quotient as zero
reg [7:0] rem=0;//initially declaring remainder as zero
always@(a or b)//whenever changes occur in a or b the below program will
execute
begin
if(a==0&&b==0)//if both dividend and divisor are zero
begin
quo=8'd0;//quotient is equal to zero
rem=8'd0;//remainder is equal to zero
end
else if(a!==0&&b==0)//if dividend is not equal to zero and divisor is
equal to zero
begin
quo=8'dz;//quotient is in unknown state(divided by zero error)
rem=8'dz;//remainder is in unknown state
end
else
begin
quo=a/b;//quotient is equal to dividend by divisor
rem=a%b;//remainder
end
end
endmodule

 :-
The module named “divider” is declared with an 8 bit inputs
named “a” and “b” where a is the dividend and b is divisor, and an 8 bit
range outputs named “quo” which is the quotient and “rem” which is the
remainder of the division process.

Initially make the quotient and remainder to be zero or clear the previous values
of quotient and remainder. By using an always and conditional statements we
can solve the given problem statement.

Always block is used to distinguish between synchronous sequential logic and


combinational logic in Verilog, the sensitivity list is used. In sequential logic, the
signals that trigger the always block are put in the sensitivity list where a and b
are sensitivity list elements . when ever the compiler finds the change in the a
and b values it will enter the always block and start to execute the sub code in
the always block. By checking the values of dividend and divisor ie if a and b
input are zeros division process cannot be carried out so it will assign quotient
and remainder as zero and end the simulation if a is assigned to some interger
value and b is made equal to zero we will get an undefined state so in this case
quotient and remainder will be assigned a value z which is high z state .after
checking all the undefined states we will end the always block and we will
proceed with the division process and the value of quotient will be assigned to
(a/b) and the remainder will be the modulus value of a and b.

 Test bench for binary divider :-


module divtestcode; //test bench module declaration
reg [7:0] a; //divident
reg [7:0] b;// divisor
wire [7:0] quo;//quotient
wire [7:0] rem;//remainder
divider uut (a,b,quo,rem);//instantiating the module
initial
begin
a= 0;
b= 0;
#100; // after 100 time units
a=8'd220;
b=8'd165;
#100; // after 100 time units
a=8'd254;
b=8'd70;
#100; // after 100 time units
a=8'd10;
b=8'd110;
#100; // after 100 time units
a=8'd100;
b=8'd2;
#100; // after 100 time units
a=8'd59;
b=8'd16;
#100; // after 100 time units
a=8'd255;
b=8'd0;
#100 $finish;// after 100 time units terminate the simulation
end
endmodule

 Result :-
Binary divider is designed and verified using verilog HDl code.
 Simulation results :-

You might also like