EEE316

Microprocessors

LECTURE #3

Asst. Prof. Dr. Volkan 
KILIÇ
 Today’s discussion
• Chapter 3 review
– Looping in PIC
– Loop inside loop
– Other conditional jumps
– All conditional branches are short jumps
– Calculating the short branch address
– Unconditional branch instruction
 Looping in PIC
• Repeat a sequence of instructions or a certain
number of times
• Two ways to achieve looping:
– Using DECFSZ instruction
– Using BNZ\BZ instructions
 DECFSZ instruction

• Decrement file register, skip the next instruction if

the result is equal 0
DECFSZ fileReg, d
GOTO instruction follows DECFSZ
 Example
Write a program to:
a) Clear WREG
b) Add 3 to WREG ten times and place the result in
SFR PORTB
 Solution
COUNT EQU 0x25
MOVLW d'10’ ;10 WREG
MOVWF COUNT
MOVLW 0 ;0 WREG
AGAIN ADDLW 3
DECFSZ COUNT,F
GOTO AGAIN
MOVWF PORTB
Solution
 Using BNZ\BZ instructions
• Branch Non-Zero (BNZ), Branch Zero (BZ)
• Supported by PIC18 families
– Early families such as PIC16 and PIC12 does NOT support
these instructions
• These instructions check the status flag

Back ……………….
……………….
DECF fileReg, f
BNZ Back
 Example

• Write a program to
a) Clear WREG
b) Add 3 to WREG ten times and place
the result in SFR PORTB
 Solution
COUNT EQU 0x25 ;use loc 25h for counter
MOVLW d'10'
MOVWF COUNT
MOVLW 0
AGAIN ADDLW 3
DECF COUNT,F
BNZ AGAIN
MOVWF PORTB
Solution
 Example 3-3
• What is the maximum number of times that the
loop can be repeated?
• All locations in the FileReg are 8-bit
• Hence the max. loop size is 255 time
 Loop inside a loop (nested loop)
e.g. Write a program to:
a) Load the PORTB SFR register with the value 55H
b) Complement PORTB 700 times
Solution
R1 EQU 0x25
R2 EQU 0x26
COUNT_1 EQU d'10'
COUNT_2 EQU d'70'
 Solution

Address Data
MOVLW 0x55
 
MOVWF PORTB
MOVLW COUNT_1
25H   (R1)  10 
MOVWF R1
LOP_1 MOVLW COUNT_2
MOVWF R2 26H   (R2)  70
LOP_2 COMF PORTB, F …  
DECF R2, F …  
BNZ LOP_2
DECF R1, F
F81H(PORTB) 55
BNZ LOP_1
Solution
 Looping 100,000 times
• Because two registers give us a maximum value
of 65025, we can use three registers to get up to
more 16 million iterations
17
Other Conditional Branch Instructions
 BZ (Branch if Z=1)
• The Z flag is checked
– If it is high, it jumps to the target address.
• For example
OVER DECF PORTB, W
BZ OVER
• In this example, if PORTB is zero, it jumps to the
label OVER
 Example 3-5

• Write a program to determine if the fileReg loc. 0x30

contains the value 0. if so, put 55H in it.
• Solution:
MYLOC EQU 0x30
MOVF MYLOC, F ; copy MYLOC to itself
BNZ NEXT ; branch if MYLOC is not zero
MOVLW 0x55
MOVWF MYLOC ; put 0x55 if MYLOC has zero value
NEXT ...
 BNC (branch if no carry)
• The carry flag bit in the status register is used to
make the decision whether to jump.
– If it (c=0), the CPU starts to fetch and execute instructions
from the address of the label.
– If it (c=1), the CPU will execute the instruction below BNC
 Example 3-6
• Find the sum of the values 79H, F5H, and E2H.
Put the sum in fileReg loc. 5H and 6H.
23
 Unconditional branch instructions
• 2 unconditional branches:
– GOTO (go to)
– BRA (branch)
• GOTO to itself using $ sign
– HERE GOTO HERE
– GOTO $
– BRA $
 GOTO
• GOTO (go to)
– Unconditional jump to any memory location in the
2M address space of PIC18
– Its 4-Byte (32 bit) instruction
• 12 bit  Opcode
• 20 bit  Address
 BRA
• BRA (branch)
– 2 byte instruction
• First 5 bit  opcode
• Lower 11 bit  relative address of the target
000-FFFH is divided into forward and backward jumps
– If the jump is forward, then target address is positive.
– If the jump is backward then the target address is
negative.
– Program jumps backward and forward relative to PC (-
1024 to 1023 bytes of memory)
– The 2-byte instruction is preferred because it takes
less ROM space.
 Call instructions and Stack
• CALL instruction is used to call a subroutine.
• Subroutines are often used to perform tasks the need
to be performed frequently.
• In the PIC18 there are two instructions for call:
– CALL (long call)
– RCALL (relative call)
 CALL
• This is 4-Byte(32-bit) instruction
– 12 bit  Opcode
– 20 bit  address of the target subroutine.
• To make sure the PIC knows where to come back
after execution of the called subroutines, the
microcontroller automatically saves on the stack the
address of the instruction immediately below the
CALL.
• After finishing execution of the subroutine, the
instruction RETURN transfers control back to caller.
 Stack and stack pointer in the PIC18
• The Stack is read/write memory (RAM) used by the
CPU to store some very critical information
temporarily.
• The information can be address or data.
• The stack is 21-bit because PC is 21-bit.
• The Stack Pointer (SP) is register used to access the
stack
– SP is 5-bit, this give use 32 location each 21bit wide
• When the PIC18 is powered up , the SP register
contains value 0.
 Stack Pointer (SP)
• The stack location 1 is the first location used to stack,
because SP points to the last-used location.
• The location 0 of the stack is not available and we
have only 31 stack location in the PIC18
 Stack Pointer (SP)
• The storing of CPU information such as PC on the
stack is called PUSH, and loading back the contents
into CPU register is called POP.
• Push in the stack
– As data is pushed onto the stack, the stack pointer is
incremented.
– For every program counter saved on the tack, SP is
incremented only once.
 Stack Pointer (SP)
• Popping from the stack
– Popping the contents of the stack back into a given register
such as program counter is the opposite of pushing.
– When the RETURN instruction at the end of the subroutine
is executed, the top location of the stack is copied back to
the program counter.
– The stack pointer is decremented.
– The Stack is (LIFO) memory.
 CALL instruction and the role of stack
• In PIC, the CPU uses the stack to save address of the
instruction just below the CALL instruction.
• This is how CPU knows where to resume when it returns
from the called subroutine.
Calling many subroutines form the main program
 RCALL (Relative Call)
• 2-Byte instruction
• The target address must be within 2K
– Because only 11 bits of the 2 Byte are used for the
address
• Save a number of bytes.
 PIC18 Time Delay and instruction pipeline

Two factors can affect the accuracy of the delay:

1. The duration of the clock period, which is function of
the Crystal Frequency
– Connected to OSC1 and OSC2
2. The instruction cycle duration
– Most of the PIC18 instructions are 1 cycle
• Use Harvard Architecture
• Use RISC Architecture
• Use the pipeline concept between fetch and execute.
 Pipelining
• The idea of pipelining in its simplest from to allow
the CPU to Fetch and execute at the same time.
 Instruction cycle time for the PIC
• Instruction cycle: is a certain amount of the time for
the CPU to execute an instruction.
• Because all instructions in the PIC are either 2-byte
of 4-byte, most instruction take one or two instruction
cycles to execute.
• Instruction cycle depends on the freq. of oscillator
– Crystal oscillator and on-chip circuitry
• One instruction cycle consists of 4 oscillator periods.
– Therefore 1/4th of the crystal frequency
• 4Mhz  1us
• 16Mhz  250ns
 Branch Penalty
• For the concept of pipelining to work, we need a
buffer or queue in which an instruction is perfected
and ready to be executed.
• When the branch instruction is executed, the CPU
starts to fetch codes from the new memory location.
• In this case, the execution unit must wait until fetches
the new instruction (Branch Penalty)
 Branch Penalty
• For this reason there are some instruction take more
than one instruction cycle such as GOTO, BRA,CALL
and all conditional branch such as BNZ, BC …
• The conditional branch can take one instruction cycle
if it does not jump.
 Delay Calculation of PIC18
• The delay of subroutines consist of two parts:
– Setting counter.
– Loop
• Most of time delay is performed by the body of
loop.
 PIC multistage execution pipeline
• Superpipelining is used to speed up execution of
instruction.
• The process of executed Instruction is split into many
small steps that are executed in parallel. So the
execution of many instructions is overlapped.
• Limited to the slowest step
 PIC multistage execution pipeline
• In PIC18, the execution unit takes 4 clock periods
of the oscillator.
PIC multistage execution pipeline