UGC NET

Computer Science and Applications

SAMPLE

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 Computer System Architecture

Computer Architecture :
 Computer Architecture defines the system in an abstract manner.
 It defines low level concepts / logical units.
 It defines the concept that the programmer deals with directly.
 This consider ‘what’ does the system do.
 It deals with those units which are directly concerned to the programmers like types of
instructions, addressing modes, data types etc.

1. REGISTER TRANSFER AND MICRO-OPERATIONS

Registers :
(i) Registers are the memory units.
(ii) Registers store, accept and transfer data and instructions that are being used immediately.
Register Transfer : It means transfer the content of one register to another register or in the
same register. This express by the Register Transfer Language (RTL).
Note : The operations on the data in registers are called micro operations.
Register Transfer Language (RTL)
 RTL used to express the design process of the digital systems.
 It is a symbolic language.
 It is a tool for describing the internal organization of digital computers.
For Example : R2  R1 , R1 and R2 denoting the registers
It denotes transfer the content of R1 into register R2.

Example : P : R 2  R1 this indicates if the value of P is 1 then transfer the content of R1 into
R2.
RTL Symbols :
(i) Letters and numerals
Description – Denote a register Ex.: R2 MAR etc.
(ii) Parentheses Description – Denote a part of a register Ex.: R1(0 – 7)
(iii) Arrow  Denotes transfer of data R3  R2
(iv) Comma, Denotes the separation of two micro operations.
Ex.: R3  R2, R4  R1
(v) Colon : Terminates Control Conditions P : R3  R2
Ex.: F : R4  R3, R3  R4
Above RTL show an operation that exchanges the content of R3 and R4 during one
common clock pulse when F = 1.
Bus : Bus refers to a group of wires which is used for transferring information from one part of
computer system to another.
Bus Transfer : For Example : Bus  C, R4  Bus.

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 Computer Science and Applications (Sample Theory)

This shows content of register C is placed on the bus, and then bus content is loaded into R4
register.
Bus Types

Internal External
Internal Bus : It connects all the internal computer components to the CPU and main memory.
It is also called as system Bus.
External Bus : It connects the external devices with the computer system.
There are some commonly used buses are also that are as follows :
(a) Data Bus : The data bus is used to transfer the data, from CPU to memory, or memory
to CPU. It is bidirectional bus.
(b) Address Bus : This is used to transfer information about where the data should go. It is
unidirectional CPU is addressing a specific location where data should be go.
(c) Control Bus : This bus is used to transmit the information which are necessary to control
and coordinate the operation of the computer. It transmits variety of individuals signals
(read, write, interrupt, etc.) to control and coordinate the operation of the computer.
Memory Transfer
(i) Memory Read : Transfer of information from memory to outside world is called memory
read.
(ii) Memory Write : Transfer of new information to be stored into the memory is write operation.
Example : Memory Read : Read : DR  M[AR]
DR  Data Register AR  Address Register
M[AR]  Denotes memory location of AR.
Memory Write : Write : M[AR]  R1
Store R1 register content to memory location of address register M[AR].
Memory Address Register (MAR) : It is used to store the address of the memory location. It
is address register.
Memory Data Register (MDR) : It is used to store the data on which operation is being performed.
It is data register.
Arithmetic Micro-operations
These micro operations perform arithmetic operations on numeric data stored in registers.

Add Micro-operation : R3  R1  R2 Contents of R1 plus R2 and transferred to R3.

Subtract Micro-operation : This micro-operation is implemented through complementation and
addition.

Example : R3  R1 + R2 + 1 (Subtraction) R2  complementation of register R2 contents.

Example : R2 = 1101 its one’s complement is R2 = 0010 then 2’s complement add 1 is one’s
complement.
0010 + 1 = 0011
Note :
(i) Binary adder is a circuit which is used for add microoperation. This is constructed through
full adder.
(ii) Subtract microoperation is implemented through by including XOR circuit with each full
adder.
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 Computer Science and Applications (Sample Theory)

Binary Incrementer : This micro operation adds one to a number in a register. This micro
operation is implemented by binary counter.
Half adder combinational circuit is used for implementing binary incrementer. Half adders are
connected in cascade to implement binary incrementer.
Logic Microoperations
These microoperations consider each bit of register and treated them as binary variables.
AND, OR, NOT, XOR these microoperations are used by computer, and other logic microoperations
are derived from these four microoperations.
Selective Set Micro-Operation : This logic microoperation set 1 the bits in register D where
there are corresponding is in register E.

1010 D before
1100 E (logic operand)
Example :
1110 A After

Selective Complement : It will complements the bit of A when bits of E corresponding to A is 1

Example :

Selective complement is nothing but ex-or operation  it says if both digit are same then output
is zero otherwith 1.

A A 0/P
same
1 1 0
1 diff. 0 1  0100
1 same 1 0
0 same 0 0

Selective Clear : It clears bits of A (make it zero) if corresponding bit in B is 1.

A 1 1 1 0
B 0 1 0 0
Example :
0/P 1 0 1 0

Selective Clear : A • B’
•  and operation
B’  complement of B

A B B' A B'
1 0 1 1
1 1 0 0 1010
1 0 1 1
0 0 1 0

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 Computer Science and Applications (Sample Theory)

Mask Operation : It is nothing but AND Operation A • B

A 1 1 1 0
B 0 1 0 0
0 1 0 0  after marking

Insert Operation : It replaces A’s value as

A = (A • B) + C
Two Operation •, +  AND, OR
Example of Insert Operation : Suppose an 8 bit register.
A contain 01101010 if we want to replace left 4 digit by 1001 then
(i) First remove left 4 digits of existing bits
means remove 0110
For this masking (and operation)
0 1 1 0 1 0 1 0
0 0 0 0 1 1 1 1 No masking so 1
0 0 0 0 1 0 1 0 Masking
Masking so zero
For masking we use digit zero  where we want to remove digit means at 4 left most
places, and where we don’t want masking we use 1.
Now to make left 4 digit 1001 we use OR operation.

0 0 0 0 1 0 1 0
1 0 0 1 0 0 0 0
1 0 0 1 1 0 1 0  Final result of insert operation

Shift Micro-Operation
 Shift micro-operations are used for serial transfer of data.
 The content of the registers can be shifted to the left or right.
There are three shift micro-operation :
(i) Logical Shift (ii) Arithmetic Shift
(ii) Circular Shift
(i) Logical Shift :
(a) Right Logical Shift : R  Shr R

0 1 1 0 1 1 0 1  8 bit register

Right Logical Shift  0 0 1 1 0 1 1 0 [Fill blank space with 0]

(b) Left Logical Shift : R  Shl R

0 1 1 0 1 1 0 1  8 bit register

Left Logical Shift  1 1 0 1 1 0 1 0 [Fill blank space with 0]

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 Computer Science and Applications (Sample Theory)

(ii) Circular Shift

0 1 1 0 1 1 0 1  8 bit register

Do right logical shift 1 0 1 1 0 1 1 0 1 Discard

(Right Circular Shift)

0 1 1 0 1 1 0 1  8 bit register

Do Left logical shift 1 1 0 1 1 0 1 0

0 Discard Left Circular Shift

R  Cil R (Circular Shift – Left Register R)
R  Cir R (Circular Shift – Right Register R)
(iii) Arithmetic Shift : (R  ashl R  Arithmetic Shift – Left R)
(R  ashr R  Arithmetic Shift – Right R)
 An arithmetic shift left multiplies a signed number.
 An arithmetic shift right multiples a signed number.
 Left most bit in register hold the sign bit 0 is positive, 1 is register.
 Arithmetic shift right leaves the signs unchanged.
 Arithmetic shift left not leaves the signs uncharged it changes the sign bit, so it is a
condition of over flow.
Instruction Codes : It is a group of bits that instruct a computer to perform a specific operation.
 It have operation code part which defines the operation (add, subtract multiply, shift and
complement).
 If there are 2n or less distinct operations than the operation code must at least n bits.

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 Computer Science and Applications (Sample Theory)

2. BASIC COMPUTER ORGANIZATION AND DESIGN

Components of a Computer
Input Unit
CPU

Arithmetic logic Registers

Control Unit
Unit

Output Memory Unit

Input Unit : That accepts data by the user. Example, Keyboards, Mouse, Joystick, Light Pen,
Scanner, Touch Screen etc.
Output Unit : That shows the information to the user. Example, Monitor, Printer, Speakers,
Plotter, Projector etc.
Memory Unit : Memory units store the data permanently and temporarily. Example Primary
Storage, Secondary Storage.
CPU (Central Processing Unit) : It is an electronic brain of the computer. A CPU controls all
the internal and external devices and perform arithmetic and logical operations. A CPU consist of three
main components, Arithmetic Logical Unit (ALU), Control Unit (CU), and Registers.
Arithmetic Logical Unit (ALU) : It performs all arithmetic operations (addition, multiplication,
division, and modulus), and logical operations (< , > , = , AND, OR etc).
Control Unit – (CU) : The function of control unit is to fetch the instruction stored in RAM
(Random Access Memory), identify the operations and the devices involved in it and accordingly generate
control signals.
Stored Program Organization : There is a one processor register (or accumulator AC) and
instruction code format.
 Instruction code format have two parts, one part denotes the operation which to be
performed and second specifics the address.
 Memory : Memory of computer system stored instructions and data or (operands). If
memory unit with 4096 words then 12 bits are need to specify the address (212 = 4096)
 Example : Instruction format = 16 bits

15 12 0
So, Opcode Address

12 bits  specify the address.

Remaining bits specify the OPCODE. Opcode means which operation (add, multiply,
subtract, complement etc.) should be done on the data (operand).

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 Computer Science and Applications (Sample Theory)

2 4096
2 2048 0
2 1024 0
2 512 0
2 256 0
2 128 0
2 64 0
2 32 0
2 16 0
2 8 0
2 4 0
2 2 0
1 0

If a + b is a instruction a and b are operands + is a operation.

(Memory)
Instruction (program)

Operands (data)

Pr ocessor Re gister
(Accumulator OR AC)

Solved Question :
Q. Any instruction should have at least :
(A) 2 operands (B) 1 operand
(C) 3 operands (D) None of above
Ans. (B) 1 operand

Computer Register
Registers are memory units which stores the data which is use frequently because registers are
fast storage devices, there storage capacity is much less but there speed is very fast.

Ex. _________ Stores the temporary data.

Sol. Registers.

Types of Registers : Registers resides in CPU. There are various computer registers that
stores specific content.
(a) Data Register (DR)  Holds data (or operands)
(b) Address Register (AR)  Holds address of data or operand
(c) Accumulator (AC)  Processor Register
(d) PC program counter  Holds address of next instruction
(e) Input register (INPR)  Holds input character
(f) Output register (OUTR)  Hold output character.
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 Computer Science and Applications (Sample Theory)

Ex.: The register which holds the address of the next instruction :
(A) Address Register (B) Data Register
(C) Program Counter (D) Accumulator
Ans. (C) Program Counter

Computer Instructions
There are three instruction code formats in general purpose computers :
(a) Memory Reference Instruction
(b) Register Reference Instruction
(c) Input Output Instruction
Each instruction format is of 16 bits.
(a) Memory Reference Instruction
From 16 bits opcode (operation code)  3 bits
(Number of bits specify)  Address  12 bits
Remaining 1 bit specify direct address or indirect address 0  direct address, 1  indirect
address.
Direct Address : Instruction format have two parts opcode and address, if address part shows
the address of a operand then it is a direct address.
Indirect Address : If address part of instruction format specify an address of a memory word
in which the address of operand is found, called indirect address.
Example : Instruction format is 457  indicates address of operand. At 457 find the operand. 15th
bit is 0 for direct address.
15 14 1211 0
0 ADD 457

16 bit

0 ADD 457

457 Operand

Memory (16 bit)

(Direct Address)
Indirect Address Example
Indirect Address :

15 14 1211 0
1 ADD 200
(Instruction format)
Location 200 specifies the address of operand, (for example it is 1000) at location 1000 we found
the operand in indirect address.

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 Computer Science and Applications (Sample Theory)

Direct Address :

15 14 1211 0
0 Opcode Address

(Direct Address Memory – Reference Instruction)

Indirect Address :

15 14 1211 0
1 Opcode Address

(Indirect Address Memory Reference Instruction)

Register Reference Instruction :
 Opcode = 111 and left most bit (15th bit) = 0

15 14 1211 0
Example : 0 111 Re gister Operation

Input – Output Instruction :

Opcode = 111 and left most bit (15th bit) = 1

15 14 1211 0
Example : 1 111 I / O Operation

Timing and Control : The events which are occur into the computer system are occur on time,
there is a master clock generator which controlled the timing for all the registers in CPU.
 Timing signals or clock pulses are applied to every registers in the control unit.
 Control signals are used to enable the registers so that clock pulses change the state of
the registers. Control signals are generated by the control unit.
 Control signals indicates whether a data is read into or written out to memory, whether
CPU is accessing memory of I/O device, and whether I/O device or memory is ready to
transfer data.

Ex. The control signals indicates.

(i) Whether a data is read into or written out to memory.
(ii) Whether CPU is accessing memory of Input/output device.
(iii) Whether I/O device or memory is ready to transfer data.
(iv) All of the above
Ans. (iv) All of the above

Instruction Cycle : A program resides in memory consists of instructions, these instructions

have to be executed by going through a cycle this is called a instruction cycle. There are different phases
in instruction cycle are as follows :
(i) Fetch (ii) Decode
(iii) Execute (iv) Interrupt

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 Computer Science and Applications (Sample Theory)

Fetch

Interrupt Decode

Execute

Following registers are used in instruction cycle :

(i) Memory Address Register (MAR) : It holds the address of data.
(ii) Memory Data Register (MDR) : It holds the data.
(iii) Program Counter (PC) : It holds the address of next instruction to be executed.
(iv) Instruction Register (IR) : It holds the last instruction fetched.
(a) Fetch Phase : The following sequence explains the fetch phase :
PC  MAR  Memory  MDR  IR
When moving from memory  MDR then PC incremented by 1. Fetch phase is used to fetch
the instruction.
(b) Decode Phase : This phase fetch source operands.
(i) The address part of IR register transfer to MAR.
(ii) Through MAR, see the data from the particular memory location and placed the data into
MDR.
In this phase control unit also include.
IR  Control Unit
Example IR contain LOAD 10
LOAD 10  control unit. [10  Address location]
(c) Execute Phase : For this phase take an example.
Example : Execute Transfer Notation (LOAD) :
(i) The operand of instruction in IR  MAR.
(ii) The content at MAR  MDR
(iii) Because it is a load So MDR  Accumulator
(d) Interrupt Cycle : When a CPU is processing a process but at this particular time user
request for another process, so it disturb the running process it is called a interrupt.
At the completion of Execute cycle a test is made to determine whether any enabled interrupt has
occurred or not.
If an enable interrupt has occurred than interrupt cycle occurs. There are following micro-operations
are in interrupt cycle :
MBR  PC
MAR  Save – Address
PC  Routine – Address
Memory  MBR
Ex. The CPU of a computer takes instruction from the memory and executes them this process is
called –
Ans. Fetch – Execute Cycle.

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 Computer Science and Applications (Sample Theory)

Memory – Reference Instructions

(i) AND AC  AC  M [AR] AC  Accumulator
AR  Address Register
M [AR]  Data on AR.
  AND operation
(ii) ADD AC  AC + M[AR], E  Cout
E  Extended Accumulator
Cout  Output Carry.
(iii) LDA  Load Operation. Transfer data from memory to Accumulator.
AC  M[AR]
(iv) STA  Store Operation : Transfer content of AC to memory.
M[AR]  AC
(v) BUN : Branch Unconditionally – PC  AR
The address in AR transferred to PC.
(vi) BSA  Branch and Save Return Address : Two micro operations are required for this :
(1) M[AR]  PC (2) PC  AR + 1
This instruction is useful for branching to a portion of a program called a subroutine or
procedure.
(vii) ISZ  Increment and Skip if Zero :
M[AR]  M[AR] + 1
if M[AR] + 1 = 0 then PC  PC + 1
Input-Output Instructions : I/O instructions are used to transfer data between peripheral devices
and main memory and able CPU to control the peripheral devices.
INPR  Input character (INPR  AC)
OUTR  Output character (AC  OUTR)
SKI If (FGI = 1) then (PC  PC + 1)
SKO If (FGO = 1) then (PC  PC + 1)
ION  IEN  1 (Interrupt enable on)
IOF  IEN  0 (Interrupt enable off)

Input Interface Interface Output

(Transmitter) INPR AR OUTR (Receiver)
Device Device

Interrupt
CPU is currently executing a process, user requesting a new process then the disturbance is
occurred it is called an interrupt.
Three Types of interrupts -
(a) Internal Interrupt (occurs due to some problem in execution)
(b) External Interrupt (occurs when CPU is executing the instructions and that time some
I/O operation will occur)
(c) Software Interrupt (occurs when while we are processing some instructions and that time
execute a one more new application program).
(d) Maskable Interrupt – Ignored by CPU.
(e) Non Maskable Interrupt – Not Ignored by CPU.

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 Computer Science and Applications (Sample Theory)

3. PROGRAMMING THE BASIC COMPUTER

Machine Language
(i) Machine language written as combination of 0 bit and 1 bit. For example 01110, 1110,
11100010
(ii) It is machine dependent.
(iii) Every statement written in machine language is machine dependent.
Assembly Language : In this language some english words are used to represent the operation
performed by the instructions. These english words are called mnemonic.
For Example : ADD Format  ADD A, B
Add A and B places the result in A.
LDA Load operation
LDA M  The content of memory M to AC.
AC  Accumulator
STA M  Store the content of AC to accumulator (AC).
 Mnemonics are used to written machine instructions.
 Assembler : It is a system software which converts the assembly language program to
machine language.
Assembly language Program  Assembler  Machine Language
Program Control Instruction in Assembly Language
These instructions are used to change or modify the flow of program, through these instructions
flow of program can be modify or change. For Example :
(i) JMP (ii) CALL
(iii) HLT (iv) MOVE
(v) JOV (Jump on Overflow)
(vi) LOOP etc.
The two types of program control instructions are :
1. Unconditional : These instructions execute always.
Example : CALL, RET, JUMP, LOOP etc.
2. Conditional : These execute only when the specified condition is true.
Example : JC, JNC, JZ,JNZ,JO,JNO etc.
(1) Unconditional Program Control Instructions :
Opcode Operand Explanation Example
CALL Address It calls the subroutine CALL 205
and saves the return
address on the stack
RET NO Operand Returns from the RET
subroutine to main
program
JUMP Address It transfers the control of JUMP 205
execution to the
specified address
LOOP Address loops through a LOOP 205
sequence of instructions
until CX=0
CX is the register

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 Computer Science and Applications (Sample Theory)

(2) Conditional Program Control Instructions :

Opcode Operand Explanation Example

Jump if CF=1
JC Address JC 205
CF is a carry flag
Jump if CF=0
JNC Address JNC 205
CF is a carry flag
Jump if ZF=1
JZ Address JC 205
ZF is zero flag
Jump if ZF=0
JNZ Address JNF 205
ZF is zero flag
LOOPE address loop while ZF = 1 and CX = 0 LOOPE 2050

Ex. Which category of microprocessor instructions detect the status conditions in registers and
accordingly exhibit the variations in program sequence on the basis of detected results?
(A) Transfer Instructions (B) Operation Instructions
(C) Control Instructions (D) All of the above
Ans. (C) Control instruction

Ex. Which of the following is not a program control instruction?

(A) CMP (B) MOV
(C) JMP (D) CALL
Ans. (A) CMP

Program Loops
A program loop is a sequence of instructions that are executed many times each time with a
different set of data.
Program Loops are specified by the FORTRAN by a
Do statement.
DIMENSION A(100)
INTEGER SUM, A
SUM = 0
Do 3 J = 1, 100
3 SUM = SUM + A(J)
There are two types of program loops finite and infinite loops. Finite loops are terminated on some
conditions, infinite loops are not terminated.
Subroutines : It is a block of instructions which perform a specific and well defined task is called
a subroutine. Subroutines are written and stored separately.
Subroutine can -
(i) Half the main program
(ii) Provide returning to the same point
(iii) Transfer control to subroutine
(iv) Execute the subroutine
(v) Revert to the main program
The link between subroutine and main program is the BSA (branch and save return address)
instruction is used.

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 Computer Science and Applications (Sample Theory)

Micro programmed Control

 In digital computer system control unit used to initiate sequences of micro operations.
 There are two ways to initiate sequences of microoperations hardwired and micro
programmed control.
 Hardwired control consists encoders decoders, etc, the speed of hardwired control is fast.
 Microprogrammed control unit uses micro programming for controlling the sequence of
microoperations.
 In this design control signal are expressed in the sum of product expression format. The
control expression is directly realized by the independent hardware components.
 It is used in the Real time applications.
 It is not suitable in the designing and testing places.
 Even a minor modification requires redesign and reconnection of the control signals, so
it is not a flexible design.
 RISC control unit is hardwired control unit.
Microprogrammed Control Unit
(i) In this unit, control memory is present to store the microprograms.
(ii) Control memory is a permanent memory i.e. ROM.
(iii) It uses a sequence of micro instructions in microprogramming language.
(iv) It acts as a midway between hardware and software.
(v) It generates a control signals to perform micro-instruction.
(vi) It is easy to design, test and implement.
(vii) It is flexible to modify.
Microprogrammed Control Unit Consist of Following Elements
(i) Control Signals : Control Signals are a group of bits that selects a path whether go to
decoder, encoder or multiplexer according to the micro instruction.
(ii) Control Variables : A binary variable which specify a micro operation.
(iii) Control Word : It is a sequence of 0 and 1 which represents control variable.
(iv) Control Memory : It is a memory which contains control signals or control word.
(v) Micro Instructions : It contains control word stored in control memory, specify control
signals for execution of micro operation.
(vi) Microprogram : It contains a sequence of micro instructions.

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 Computer Science and Applications (Sample Theory)

To understand the microprogrammed control unit components, see the diagram below :

External Address Generator

M=0

MUX

CMAR

M=1

CONTROL
MEMORY
(ROM)

M BA

CF
(Control Field)
 CMAR (Control Memory Address Register) : It tells the address of control memory which
is to be read.
 Through control memory we take control signals which are put in control field (CF), this
is a part of output register, one part of output register contains BA (Branch Address).
 Branch Address is an address of next address in the control memory which should be
read.
 External Address generator identifies, the address of the next instruction to be executed.
 There are two inputs of multiplexer (MUX), one is Branch address and other from External
Address Generator.
 So there is a selection mechanism for it if M = 0 then address is generated through
External Address Generator and if M = 1 address is generated from Branch address.

Branch Condition Flag Control Field Control Memory

Address

One of the systems One of the systems Control signals Next Instruction
supported branch supported flags Log 2 Decoded binary address
condition Log 2 (No. (No. of flages) format (1 bit/CS) Log 2 CM size
of Branch conditions) Encoded binary
format
(N CS’s  log2 N bits)
Fig. Microinstruction control word format
Microprogram Sequencer : This is a set of components which are taking part to determine
which the next location in control memory to read is. In MCU control memory is not a part of microprogram
sequencer.

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 Computer Science and Applications (Sample Theory)

Example of Microprogrammed Unit and Address Sequencing

Consider the operations which are occur in instruction fetch and decode :

T0 : MAR  PC IR0 11  Lower Twelve bits of 

 
IR that holds operand address,

Time signals T1 : IR  M[MAR] : PC  PC  1
T : DCD(IR) : MAR  IR in memory if it is a memory 
 2 0 : 11  
reference register 
Controls that are involved from T0 to T2 are as follows :

In T0  LDMAR , OEPC (Both signals have to activated)


Control Signals

T1  {LDIR, RDM, PCINR} Control Signals

T2  LDMAR, OEIR (Control Signals)
Number of Control Signals = n
Ci represents ith bit in a memory location.
So in the MCU : Associate these control signals with bits in the control memory.

LDMAR  C 0 , OEPC  C1, LDIR  C 2 , RDM  C 3 , PCINR  C 4 , OEIR  C 5

So, in T0 time C5 C4 C3 C2 C1 C0 [LDMAR  C0 , OEPC  C1]

0 0 0 0 1 1
T1 time 0 1 1 1 0 0
T2 time 1 0 0 0 0 1
Branch Address Fields or Next Address Fields :
(i) In T0  01 (for simplicity put in decimal form in system it is in binary form)
(ii) In T1  02 (these control signals are generated from 02 central memory location)
(iii) In T2  XX (Because After T2 execution is done so there is no next address generation)
(the address should be generated by external address generator)
Mode(M) field for T0 time signal :
M = 1 (next address field is branch address field)
For T1 time signal  M = 1 (next address field is branch address field)
For T2 time signal  M = 0 (address generated by external address generator)
So,

C5 C4 C3 C2 C1 C0 B A M
0 0 0 0 1 1 0 1 1
0 1 1 1 0 0 0 2 1
1 0 0 0 0 1 x x 0
In MCU (Micro Programmed Control Unit) if we change the sequence of control signals in control
memory without any modifications in hardwired or circuit we can change the sequence of micro operations,
so that’s why micro programmed control unit is more flexible.
Disadvantage : It have low speed as compare to harwired control unit.
Design of Control Unit
Functions of Control Unit
1. The control unit is a component of CPU that directs the operations of the processor.
2. It tells the computer’s memory, ALU and input / output devices how to respond to a
program’s instructions.
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 Computer Science and Applications (Sample Theory)

3. It directs the operation of the other units by providing timing and control signals.
4. It generates the control signals to perform the operations.
Components of Control Unit
1. Sequence logic (It generates a logic in which sequence the operations have to the executed)
2. Registers
3. Decoder
4. Control Memory (Stores control signals)

Control Unit
Sequencing
Logic
Registers and
Decoders

Control
Memory

Working of Control Unit

(1) Fetch instruction from the memory
(2) Decode instruction (into command)
(3) Execute the instruction
(4) Store instruction in memory
Diagram of Working of Control Unit
Step 2 : Decode Instruction Step 3 : Execute Instruction

ALU Control Unit

Step 1 : Fetch instruction Step 4 : Store instruction

from the memory in memory

Main Memory

Central Processing Unit

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 Computer Science and Applications (Sample Questions)

Sample Questions With Solutions

1. An n-bit binary adder requires :

(A) n/2 full adder (B) n – 1 full adder
(C) n/2 – 1 full adder (D) n full adder

2. To construct Binary Adder - Subtractor which Logic Gate is include with each full adder. :
(A) OR-Gate (B) NOT-Gate
(C) Exclusive NOR Gate (D) Exclusive OR GATE

3. To construct n-bit binary incrementer, how many half adders require :

(A) n/2 half adder (B) n half adder
(C) n – 1 half adder (D) None of the above

4. The basic component of an arithmetic circuit is :

(A) Half Adder (B) Full Adder
(C) Binary Adder (D) Parallel Adder

5. The sequence of events that happen during a typical fetch operation is :

(A) PC  MAR  Memory  MDR  IR
(B) PC  Memory  MDR  IR
(C) PC  Memory  IR
(D) PC  MAR  Memory  IR

6. Which of the following cycle is used for interpreting the instruction that was fetched in the fetch
cycle?
(A) Fetch cycle (B) Decode cycle
(C) Execute cycle (D) Interrupt cycle

7. The register which contains the data to be written into or read out of the addressed location is
called :
(A) Memory addressed register (B) Memory Data register
(C) Program counter (D) Index register

8. An interrupt can be temporarily ignored by the counter is called :

(A) Vector interrupt (B) Non-maskable interrupt
(C) Maskable interrupt (D) Low priority interrupt

9. How many 32 K × 1 RAM chips are needed to provide a memory capacity of 256 KB ?
(A) 8 (B) 32
(C) 64 (D) 128

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 Computer Science and Applications (Sample Questions)

10. Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on
a non-pipelined but identical CPU we can say that :
(A) T1  T2
(B) T1  T2
(C) T1  T2
(D) T1 is T2 plus line taken for one instruction fetch cycle

SOLUTIONS

1. (D) n full adder

2. (D) Exclusive NOR Gate
3. (B) n half adder
4. (D) Parallel Adder
5. (A) PC  MAR  Memory  MDR  IR
Steps of fetch cycle
(1) PC has address of next instruction
(2) Content of PC copied to the MAR
(3) MAR to Memory
(4) The contents (instruction) at the memory location (address) contained in MAR are
then copied into the MDR
(5) The contents (instruction) in the MDR is then copied and placed into the IR
6. (B) Decode cycle
7. (B) Memory Data register
8. (C) Maskable interrupt
9. (C) We need 256 Kbytes i.e. 256 × 1024 × 8 bits RAM chips of capacity 32 K bits = 32 ×
1024 bits  (256 × 1024 × 8) / (32 × 1024) = 64
10. (B) T1  T2
Pipelining does not increase the execution time of a single instruction. It increases the
overall performance by executing instructions in multiple pipeline stages.
We assume that each stage takes ‘T’ unit of time both in pipelined and non-pipelined CPU.
Let total stages in pipelined CPU = Total stages in non-pipelined CPU = K and number
of Instructions = N = 1
Pipelined CPU : Total time (T1) = (K + (N – 1)) * T = KT
Non-Pipelined CPU : Total time (T2) = KNT = KT
Considering buffer delays in pipelined CPU, T1  T2

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