; generated by ARM C/C++ Compiler, 5.

03 [Build 76]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave
-o.\flash\obj\stm32f10x_rcc.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\
--depend=.\flash\obj\stm32f10x_rcc.d --cpu=Cortex-M3 --apcs=interwork -O0
--diag_suppress=870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include
-I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\User\bsp
-I..\..\User\bsp\inc -I..\..\uCOS-II\uCOS-II\Ports\ARM-Cortex-M3\Generic\RealView
-I..\..\uCOS-II\uCOS-II\Source -I..\..\uCOS-II\uC-LIB -I..\..\uCOS-II\uC-
LIB\Ports\ARM-Cortex-M3\RealView -I..\..\uCOS-II\uC-CPU -I..\..\uCOS-II\uC-CPU\ARM-
Cortex-M3\RealView -I..\..\User -I..\..\Libraries\CMSIS\Include
-IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\ST\STM32F10x
-D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD
..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c]
THUMB

AREA ||i.RCC_ADCCLKConfig||, CODE, READONLY, ALIGN=2

RCC_ADCCLKConfig PROC
;;;771 */
;;;772 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
000000 4601 MOV r1,r0
;;;773 {
;;;774 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;775 /* Check the parameters */
;;;776 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
;;;777 tmpreg = RCC->CFGR;
000004 4a03 LDR r2,|L1.20|
000006 6850 LDR r0,[r2,#4]
;;;778 /* Clear ADCPRE[1:0] bits */
;;;779 tmpreg &= CFGR_ADCPRE_Reset_Mask;
000008 f4204040 BIC r0,r0,#0xc000
;;;780 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
;;;781 tmpreg |= RCC_PCLK2;
00000c 4308 ORRS r0,r0,r1
;;;782 /* Store the new value */
;;;783 RCC->CFGR = tmpreg;
00000e 6050 STR r0,[r2,#4]
;;;784 }
000010 4770 BX lr
;;;785
ENDP

000012 0000 DCW 0x0000

|L1.20|
DCD 0x40021000

AREA ||i.RCC_AHBPeriphClockCmd||, CODE, READONLY, ALIGN=2

RCC_AHBPeriphClockCmd PROC
;;;1069 */
;;;1070 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState
NewState)
000000 b129 CBZ r1,|L2.14|
;;;1071 {
;;;1072 /* Check the parameters */
;;;1073 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
;;;1074 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1075
;;;1076 if (NewState != DISABLE)
;;;1077 {
;;;1078 RCC->AHBENR |= RCC_AHBPeriph;
000002 4a06 LDR r2,|L2.28|
000004 6952 LDR r2,[r2,#0x14]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L2.28|
00000a 615a STR r2,[r3,#0x14]
00000c e004 B |L2.24|
|L2.14|
;;;1079 }
;;;1080 else
;;;1081 {
;;;1082 RCC->AHBENR &= ~RCC_AHBPeriph;
00000e 4a03 LDR r2,|L2.28|
000010 6952 LDR r2,[r2,#0x14]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L2.28|
000016 615a STR r2,[r3,#0x14]
|L2.24|
;;;1083 }
;;;1084 }
000018 4770 BX lr
;;;1085
ENDP

00001a 0000 DCW 0x0000

|L2.28|
DCD 0x40021000

AREA ||i.RCC_APB1PeriphClockCmd||, CODE, READONLY,

ALIGN=2

RCC_APB1PeriphClockCmd PROC
;;;1131 */
;;;1132 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState
NewState)
000000 b129 CBZ r1,|L3.14|
;;;1133 {
;;;1134 /* Check the parameters */
;;;1135 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1136 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1137 if (NewState != DISABLE)
;;;1138 {
;;;1139 RCC->APB1ENR |= RCC_APB1Periph;
000002 4a06 LDR r2,|L3.28|
000004 69d2 LDR r2,[r2,#0x1c]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L3.28|
00000a 61da STR r2,[r3,#0x1c]
00000c e004 B |L3.24|
|L3.14|
;;;1140 }
;;;1141 else
;;;1142 {
;;;1143 RCC->APB1ENR &= ~RCC_APB1Periph;
00000e 4a03 LDR r2,|L3.28|
000010 69d2 LDR r2,[r2,#0x1c]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L3.28|
000016 61da STR r2,[r3,#0x1c]
|L3.24|
;;;1144 }
;;;1145 }
000018 4770 BX lr
;;;1146
ENDP

00001a 0000 DCW 0x0000

|L3.28|
DCD 0x40021000

AREA ||i.RCC_APB1PeriphResetCmd||, CODE, READONLY,

ALIGN=2

RCC_APB1PeriphResetCmd PROC
;;;1221 */
;;;1222 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState
NewState)
000000 b129 CBZ r1,|L4.14|
;;;1223 {
;;;1224 /* Check the parameters */
;;;1225 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1226 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1227 if (NewState != DISABLE)
;;;1228 {
;;;1229 RCC->APB1RSTR |= RCC_APB1Periph;
000002 4a06 LDR r2,|L4.28|
000004 6912 LDR r2,[r2,#0x10]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L4.28|
00000a 611a STR r2,[r3,#0x10]
00000c e004 B |L4.24|
|L4.14|
;;;1230 }
;;;1231 else
;;;1232 {
;;;1233 RCC->APB1RSTR &= ~RCC_APB1Periph;
00000e 4a03 LDR r2,|L4.28|
000010 6912 LDR r2,[r2,#0x10]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L4.28|
000016 611a STR r2,[r3,#0x10]
|L4.24|
;;;1234 }
;;;1235 }
000018 4770 BX lr
;;;1236
ENDP

00001a 0000 DCW 0x0000

|L4.28|
DCD 0x40021000

AREA ||i.RCC_APB2PeriphClockCmd||, CODE, READONLY,

ALIGN=2

RCC_APB2PeriphClockCmd PROC
;;;1100 */
;;;1101 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState
NewState)
000000 b129 CBZ r1,|L5.14|
;;;1102 {
;;;1103 /* Check the parameters */
;;;1104 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1105 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1106 if (NewState != DISABLE)
;;;1107 {
;;;1108 RCC->APB2ENR |= RCC_APB2Periph;
000002 4a06 LDR r2,|L5.28|
000004 6992 LDR r2,[r2,#0x18]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L5.28|
00000a 619a STR r2,[r3,#0x18]
00000c e004 B |L5.24|
|L5.14|
;;;1109 }
;;;1110 else
;;;1111 {
;;;1112 RCC->APB2ENR &= ~RCC_APB2Periph;
00000e 4a03 LDR r2,|L5.28|
000010 6992 LDR r2,[r2,#0x18]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L5.28|
000016 619a STR r2,[r3,#0x18]
|L5.24|
;;;1113 }
;;;1114 }
000018 4770 BX lr
;;;1115
ENDP

00001a 0000 DCW 0x0000

|L5.28|
DCD 0x40021000

AREA ||i.RCC_APB2PeriphResetCmd||, CODE, READONLY,

ALIGN=2

RCC_APB2PeriphResetCmd PROC
;;;1190 */
;;;1191 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState
NewState)
000000 b129 CBZ r1,|L6.14|
;;;1192 {
;;;1193 /* Check the parameters */
;;;1194 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1195 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1196 if (NewState != DISABLE)
;;;1197 {
;;;1198 RCC->APB2RSTR |= RCC_APB2Periph;
000002 4a06 LDR r2,|L6.28|
000004 68d2 LDR r2,[r2,#0xc]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L6.28|
00000a 60da STR r2,[r3,#0xc]
00000c e004 B |L6.24|
 |L6.14|
;;;1199 }
;;;1200 else
;;;1201 {
;;;1202 RCC->APB2RSTR &= ~RCC_APB2Periph;
00000e 4a03 LDR r2,|L6.28|
000010 68d2 LDR r2,[r2,#0xc]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L6.28|
000016 60da STR r2,[r3,#0xc]
|L6.24|
;;;1203 }
;;;1204 }
000018 4770 BX lr
;;;1205
ENDP

00001a 0000 DCW 0x0000

|L6.28|
DCD 0x40021000

AREA ||i.RCC_AdjustHSICalibrationValue||, CODE, READONLY,

ALIGN=2

RCC_AdjustHSICalibrationValue PROC
;;;339 */
;;;340 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
000000 4601 MOV r1,r0
;;;341 {
;;;342 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;343 /* Check the parameters */
;;;344 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
;;;345 tmpreg = RCC->CR;
000004 4a03 LDR r2,|L7.20|
000006 6810 LDR r0,[r2,#0]
;;;346 /* Clear HSITRIM[4:0] bits */
;;;347 tmpreg &= CR_HSITRIM_Mask;
000008 f02000f8 BIC r0,r0,#0xf8
;;;348 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;349 tmpreg |= (uint32_t)HSICalibrationValue << 3;
00000c ea4000c1 ORR r0,r0,r1,LSL #3
;;;350 /* Store the new value */
;;;351 RCC->CR = tmpreg;
000010 6010 STR r0,[r2,#0]
;;;352 }
000012 4770 BX lr
;;;353
ENDP

|L7.20|
DCD 0x40021000

AREA ||i.RCC_BackupResetCmd||, CODE, READONLY, ALIGN=2

RCC_BackupResetCmd PROC
;;;1242 */
;;;1243 void RCC_BackupResetCmd(FunctionalState NewState)
000000 4901 LDR r1,|L8.8|
;;;1244 {
;;;1245 /* Check the parameters */
;;;1246 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1247 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
000002 6008 STR r0,[r1,#0]
;;;1248 }
000004 4770 BX lr
;;;1249
ENDP

000006 0000 DCW 0x0000

|L8.8|
DCD 0x42420440

AREA ||i.RCC_ClearFlag||, CODE, READONLY, ALIGN=2

RCC_ClearFlag PROC
;;;1376 */
;;;1377 void RCC_ClearFlag(void)
000000 4803 LDR r0,|L9.16|
;;;1378 {
;;;1379 /* Set RMVF bit to clear the reset flags */
;;;1380 RCC->CSR |= CSR_RMVF_Set;
000002 6a40 LDR r0,[r0,#0x24]
000004 f0407080 ORR r0,r0,#0x1000000
000008 4901 LDR r1,|L9.16|
00000a 6248 STR r0,[r1,#0x24]
;;;1381 }
00000c 4770 BX lr
;;;1382
ENDP

00000e 0000 DCW 0x0000

|L9.16|
DCD 0x40021000

AREA ||i.RCC_ClearITPendingBit||, CODE, READONLY, ALIGN=2

RCC_ClearITPendingBit PROC
;;;1453 */
;;;1454 void RCC_ClearITPendingBit(uint8_t RCC_IT)
000000 4901 LDR r1,|L10.8|
;;;1455 {
;;;1456 /* Check the parameters */
;;;1457 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
;;;1458
;;;1459 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected
interrupt
;;;1460 pending bits */
;;;1461 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
000002 7288 STRB r0,[r1,#0xa]
;;;1462 }
000004 4770 BX lr
;;;1463
ENDP

000006 0000 DCW 0x0000

|L10.8|
DCD 0x40021000
 AREA ||i.RCC_ClockSecuritySystemCmd||, CODE, READONLY,
ALIGN=2

RCC_ClockSecuritySystemCmd PROC
;;;1255 */
;;;1256 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
000000 4901 LDR r1,|L11.8|
;;;1257 {
;;;1258 /* Check the parameters */
;;;1259 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1260 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
000002 64c8 STR r0,[r1,#0x4c]
;;;1261 }
000004 4770 BX lr
;;;1262
ENDP

000006 0000 DCW 0x0000

|L11.8|
DCD 0x42420000

AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2

RCC_DeInit PROC
;;;222 */
;;;223 void RCC_DeInit(void)
000000 480f LDR r0,|L12.64|
;;;224 {
;;;225 /* Set HSION bit */
;;;226 RCC->CR |= (uint32_t)0x00000001;
000002 6800 LDR r0,[r0,#0]
000004 f0400001 ORR r0,r0,#1
000008 490d LDR r1,|L12.64|
00000a 6008 STR r0,[r1,#0]
;;;227
;;;228 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
;;;229 #ifndef STM32F10X_CL
;;;230 RCC->CFGR &= (uint32_t)0xF8FF0000;
00000c 4608 MOV r0,r1
00000e 6840 LDR r0,[r0,#4]
000010 490c LDR r1,|L12.68|
000012 4008 ANDS r0,r0,r1
000014 490a LDR r1,|L12.64|
000016 6048 STR r0,[r1,#4]
;;;231 #else
;;;232 RCC->CFGR &= (uint32_t)0xF0FF0000;
;;;233 #endif /* STM32F10X_CL */
;;;234
;;;235 /* Reset HSEON, CSSON and PLLON bits */
;;;236 RCC->CR &= (uint32_t)0xFEF6FFFF;
000018 4608 MOV r0,r1
00001a 6800 LDR r0,[r0,#0]
00001c 490a LDR r1,|L12.72|
00001e 4008 ANDS r0,r0,r1
000020 4907 LDR r1,|L12.64|
000022 6008 STR r0,[r1,#0]
;;;237
;;;238 /* Reset HSEBYP bit */
;;;239 RCC->CR &= (uint32_t)0xFFFBFFFF;
000024 4608 MOV r0,r1
000026 6800 LDR r0,[r0,#0]
000028 f4202080 BIC r0,r0,#0x40000
00002c 6008 STR r0,[r1,#0]
;;;240
;;;241 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
;;;242 RCC->CFGR &= (uint32_t)0xFF80FFFF;
00002e 4608 MOV r0,r1
000030 6840 LDR r0,[r0,#4]
000032 f42000fe BIC r0,r0,#0x7f0000
000036 6048 STR r0,[r1,#4]
;;;243
;;;244 #ifdef STM32F10X_CL
;;;245 /* Reset PLL2ON and PLL3ON bits */
;;;246 RCC->CR &= (uint32_t)0xEBFFFFFF;
;;;247
;;;248 /* Disable all interrupts and clear pending bits */
;;;249 RCC->CIR = 0x00FF0000;
;;;250
;;;251 /* Reset CFGR2 register */
;;;252 RCC->CFGR2 = 0x00000000;
;;;253 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined
(STM32F10X_HD_VL)
;;;254 /* Disable all interrupts and clear pending bits */
;;;255 RCC->CIR = 0x009F0000;
;;;256
;;;257 /* Reset CFGR2 register */
;;;258 RCC->CFGR2 = 0x00000000;
;;;259 #else
;;;260 /* Disable all interrupts and clear pending bits */
;;;261 RCC->CIR = 0x009F0000;
000038 f44f001f MOV r0,#0x9f0000
00003c 6088 STR r0,[r1,#8]
;;;262 #endif /* STM32F10X_CL */
;;;263
;;;264 }
00003e 4770 BX lr
;;;265
ENDP

|L12.64|
DCD 0x40021000
|L12.68|
DCD 0xf8ff0000
|L12.72|
DCD 0xfef6ffff

AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2

RCC_GetClocksFreq PROC
;;;913 */
;;;914 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
000000 b530 PUSH {r4,r5,lr}
;;;915 {
;;;916 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
000002 2100 MOVS r1,#0
000004 2200 MOVS r2,#0
000006 2400 MOVS r4,#0
000008 2300 MOVS r3,#0
;;;917
;;;918 #ifdef STM32F10X_CL
;;;919 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0,
pll2mull = 0;
;;;920 #endif /* STM32F10X_CL */
;;;921
;;;922 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined
(STM32F10X_HD_VL)
;;;923 uint32_t prediv1factor = 0;
;;;924 #endif
;;;925
;;;926 /* Get SYSCLK source
-------------------------------------------------------*/
;;;927 tmp = RCC->CFGR & CFGR_SWS_Mask;
00000a 4d2d LDR r5,|L13.192|
00000c 686d LDR r5,[r5,#4]
00000e f005010c AND r1,r5,#0xc
;;;928
;;;929 switch (tmp)
000012 b121 CBZ r1,|L13.30|
000014 2904 CMP r1,#4
000016 d005 BEQ |L13.36|
000018 2908 CMP r1,#8
00001a d123 BNE |L13.100|
00001c e005 B |L13.42|
|L13.30|
;;;930 {
;;;931 case 0x00: /* HSI used as system clock */
;;;932 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00001e 4d29 LDR r5,|L13.196|
000020 6005 STR r5,[r0,#0]
;;;933 break;
000022 e022 B |L13.106|
|L13.36|
;;;934 case 0x04: /* HSE used as system clock */
;;;935 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
000024 4d27 LDR r5,|L13.196|
000026 6005 STR r5,[r0,#0]
;;;936 break;
000028 e01f B |L13.106|
|L13.42|
;;;937 case 0x08: /* PLL used as system clock */
;;;938
;;;939 /* Get PLL clock source and multiplication factor
----------------------*/
;;;940 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00002a 4d25 LDR r5,|L13.192|
00002c 686d LDR r5,[r5,#4]
00002e f4051270 AND r2,r5,#0x3c0000
;;;941 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000032 4d23 LDR r5,|L13.192|
000034 686d LDR r5,[r5,#4]
000036 f4053480 AND r4,r5,#0x10000
;;;942
;;;943 #ifndef STM32F10X_CL
;;;944 pllmull = ( pllmull >> 18) + 2;
00003a 2502 MOVS r5,#2
00003c eb054292 ADD r2,r5,r2,LSR #18
;;;945
;;;946 if (pllsource == 0x00)
000040 b91c CBNZ r4,|L13.74|
;;;947 {/* HSI oscillator clock divided by 2 selected as PLL clock entry
*/
;;;948 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
000042 4d21 LDR r5,|L13.200|
000044 4355 MULS r5,r2,r5
000046 6005 STR r5,[r0,#0]
000048 e00b B |L13.98|
|L13.74|
;;;949 }
;;;950 else
;;;951 {
;;;952 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined
(STM32F10X_HD_VL)
;;;953 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
;;;954 /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;955 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) *
pllmull;
;;;956 #else
;;;957 /* HSE selected as PLL clock entry */
;;;958 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
00004a 4d1d LDR r5,|L13.192|
00004c 686d LDR r5,[r5,#4]
00004e f4153f00 TST r5,#0x20000
000052 d003 BEQ |L13.92|
;;;959 {/* HSE oscillator clock divided by 2 */
;;;960 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
000054 4d1c LDR r5,|L13.200|
000056 4355 MULS r5,r2,r5
000058 6005 STR r5,[r0,#0]
00005a e002 B |L13.98|
|L13.92|
;;;961 }
;;;962 else
;;;963 {
;;;964 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
00005c 4d19 LDR r5,|L13.196|
00005e 4355 MULS r5,r2,r5
000060 6005 STR r5,[r0,#0]
|L13.98|
;;;965 }
;;;966 #endif
;;;967 }
;;;968 #else
;;;969 pllmull = pllmull >> 18;
;;;970
;;;971 if (pllmull != 0x0D)
;;;972 {
;;;973 pllmull += 2;
;;;974 }
;;;975 else
;;;976 { /* PLL multiplication factor = PLL input clock * 6.5 */
;;;977 pllmull = 13 / 2;
;;;978 }
;;;979
;;;980 if (pllsource == 0x00)
;;;981 {/* HSI oscillator clock divided by 2 selected as PLL clock entry
*/
;;;982 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
;;;983 }
;;;984 else
;;;985 {/* PREDIV1 selected as PLL clock entry */
;;;986
;;;987 /* Get PREDIV1 clock source and division factor */
;;;988 prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
;;;989 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
;;;990
;;;991 if (prediv1source == 0)
;;;992 { /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;993 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) *
pllmull;
;;;994 }
;;;995 else
;;;996 {/* PLL2 clock selected as PREDIV1 clock entry */
;;;997
;;;998 /* Get PREDIV2 division factor and PLL2 multiplication factor
*/
;;;999 prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
;;;1000 pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
;;;1001 RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) *
pll2mull) / prediv1factor) * pllmull;
;;;1002 }
;;;1003 }
;;;1004 #endif /* STM32F10X_CL */
;;;1005 break;
000062 e002 B |L13.106|
|L13.100|
;;;1006
;;;1007 default:
;;;1008 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
000064 4d17 LDR r5,|L13.196|
000066 6005 STR r5,[r0,#0]
;;;1009 break;
000068 bf00 NOP
|L13.106|
00006a bf00 NOP ;933
;;;1010 }
;;;1011
;;;1012 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies
----------------*/
;;;1013 /* Get HCLK prescaler */
;;;1014 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00006c 4d14 LDR r5,|L13.192|
00006e 686d LDR r5,[r5,#4]
000070 f00501f0 AND r1,r5,#0xf0
;;;1015 tmp = tmp >> 4;
000074 0909 LSRS r1,r1,#4
;;;1016 presc = APBAHBPrescTable[tmp];
000076 4d15 LDR r5,|L13.204|
000078 5c6b LDRB r3,[r5,r1]
;;;1017 /* HCLK clock frequency */
;;;1018 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00007a 6805 LDR r5,[r0,#0]
00007c 40dd LSRS r5,r5,r3
00007e 6045 STR r5,[r0,#4]
;;;1019 /* Get PCLK1 prescaler */
;;;1020 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
000080 4d0f LDR r5,|L13.192|
000082 686d LDR r5,[r5,#4]
000084 f40561e0 AND r1,r5,#0x700
;;;1021 tmp = tmp >> 8;
000088 0a09 LSRS r1,r1,#8
;;;1022 presc = APBAHBPrescTable[tmp];
00008a 4d10 LDR r5,|L13.204|
00008c 5c6b LDRB r3,[r5,r1]
;;;1023 /* PCLK1 clock frequency */
;;;1024 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00008e 6845 LDR r5,[r0,#4]
000090 40dd LSRS r5,r5,r3
000092 6085 STR r5,[r0,#8]
;;;1025 /* Get PCLK2 prescaler */
;;;1026 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
000094 4d0a LDR r5,|L13.192|
000096 686d LDR r5,[r5,#4]
000098 f4055160 AND r1,r5,#0x3800
;;;1027 tmp = tmp >> 11;
00009c 0ac9 LSRS r1,r1,#11
;;;1028 presc = APBAHBPrescTable[tmp];
00009e 4d0b LDR r5,|L13.204|
0000a0 5c6b LDRB r3,[r5,r1]
;;;1029 /* PCLK2 clock frequency */
;;;1030 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
0000a2 6845 LDR r5,[r0,#4]
0000a4 40dd LSRS r5,r5,r3
0000a6 60c5 STR r5,[r0,#0xc]
;;;1031 /* Get ADCCLK prescaler */
;;;1032 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
0000a8 4d05 LDR r5,|L13.192|
0000aa 686d LDR r5,[r5,#4]
0000ac f4054140 AND r1,r5,#0xc000
;;;1033 tmp = tmp >> 14;
0000b0 0b89 LSRS r1,r1,#14
;;;1034 presc = ADCPrescTable[tmp];
0000b2 4d07 LDR r5,|L13.208|
0000b4 5c6b LDRB r3,[r5,r1]
;;;1035 /* ADCCLK clock frequency */
;;;1036 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
0000b6 68c5 LDR r5,[r0,#0xc]
0000b8 fbb5f5f3 UDIV r5,r5,r3
0000bc 6105 STR r5,[r0,#0x10]
;;;1037 }
0000be bd30 POP {r4,r5,pc}
;;;1038
ENDP

|L13.192|
DCD 0x40021000
|L13.196|
DCD 0x007a1200
|L13.200|
DCD 0x003d0900
|L13.204|
DCD APBAHBPrescTable
|L13.208|
DCD ADCPrescTable
 AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2

RCC_GetFlagStatus PROC
;;;1331 */
;;;1332 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
000000 b510 PUSH {r4,lr}
;;;1333 {
000002 4601 MOV r1,r0
;;;1334 uint32_t tmp = 0;
000004 2200 MOVS r2,#0
;;;1335 uint32_t statusreg = 0;
000006 2300 MOVS r3,#0
;;;1336 FlagStatus bitstatus = RESET;
000008 2000 MOVS r0,#0
;;;1337 /* Check the parameters */
;;;1338 assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;1339
;;;1340 /* Get the RCC register index */
;;;1341 tmp = RCC_FLAG >> 5;
00000a 114a ASRS r2,r1,#5
;;;1342 if (tmp == 1) /* The flag to check is in CR register */
00000c 2a01 CMP r2,#1
00000e d102 BNE |L14.22|
;;;1343 {
;;;1344 statusreg = RCC->CR;
000010 4c09 LDR r4,|L14.56|
000012 6823 LDR r3,[r4,#0]
000014 e006 B |L14.36|
|L14.22|
;;;1345 }
;;;1346 else if (tmp == 2) /* The flag to check is in BDCR register */
000016 2a02 CMP r2,#2
000018 d102 BNE |L14.32|
;;;1347 {
;;;1348 statusreg = RCC->BDCR;
00001a 4c07 LDR r4,|L14.56|
00001c 6a23 LDR r3,[r4,#0x20]
00001e e001 B |L14.36|
|L14.32|
;;;1349 }
;;;1350 else /* The flag to check is in CSR register */
;;;1351 {
;;;1352 statusreg = RCC->CSR;
000020 4c05 LDR r4,|L14.56|
000022 6a63 LDR r3,[r4,#0x24]
|L14.36|
;;;1353 }
;;;1354
;;;1355 /* Get the flag position */
;;;1356 tmp = RCC_FLAG & FLAG_Mask;
000024 f001021f AND r2,r1,#0x1f
;;;1357 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
000028 2401 MOVS r4,#1
00002a 4094 LSLS r4,r4,r2
00002c 421c TST r4,r3
00002e d001 BEQ |L14.52|
;;;1358 {
;;;1359 bitstatus = SET;
000030 2001 MOVS r0,#1
000032 e000 B |L14.54|
|L14.52|
;;;1360 }
;;;1361 else
;;;1362 {
;;;1363 bitstatus = RESET;
000034 2000 MOVS r0,#0
|L14.54|
;;;1364 }
;;;1365
;;;1366 /* Return the flag status */
;;;1367 return bitstatus;
;;;1368 }
000036 bd10 POP {r4,pc}
;;;1369
ENDP

|L14.56|
DCD 0x40021000

AREA ||i.RCC_GetITStatus||, CODE, READONLY, ALIGN=2

RCC_GetITStatus PROC
;;;1407 */
;;;1408 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
000000 4601 MOV r1,r0
;;;1409 {
;;;1410 ITStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;1411 /* Check the parameters */
;;;1412 assert_param(IS_RCC_GET_IT(RCC_IT));
;;;1413
;;;1414 /* Check the status of the specified RCC interrupt */
;;;1415 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
000004 4a03 LDR r2,|L15.20|
000006 6892 LDR r2,[r2,#8]
000008 420a TST r2,r1
00000a d001 BEQ |L15.16|
;;;1416 {
;;;1417 bitstatus = SET;
00000c 2001 MOVS r0,#1
00000e e000 B |L15.18|
|L15.16|
;;;1418 }
;;;1419 else
;;;1420 {
;;;1421 bitstatus = RESET;
000010 2000 MOVS r0,#0
|L15.18|
;;;1422 }
;;;1423
;;;1424 /* Return the RCC_IT status */
;;;1425 return bitstatus;
;;;1426 }
000012 4770 BX lr
;;;1427
ENDP
 |L15.20|
DCD 0x40021000

AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2

RCC_GetSYSCLKSource PROC
;;;592 */
;;;593 uint8_t RCC_GetSYSCLKSource(void)
000000 4802 LDR r0,|L16.12|
;;;594 {
;;;595 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
000002 6840 LDR r0,[r0,#4]
000004 f000000c AND r0,r0,#0xc
;;;596 }
000008 4770 BX lr
;;;597
ENDP

00000a 0000 DCW 0x0000

|L16.12|
DCD 0x40021000

AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2

RCC_HCLKConfig PROC
;;;613 */
;;;614 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
000000 4601 MOV r1,r0
;;;615 {
;;;616 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;617 /* Check the parameters */
;;;618 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
;;;619 tmpreg = RCC->CFGR;
000004 4a03 LDR r2,|L17.20|
000006 6850 LDR r0,[r2,#4]
;;;620 /* Clear HPRE[3:0] bits */
;;;621 tmpreg &= CFGR_HPRE_Reset_Mask;
000008 f02000f0 BIC r0,r0,#0xf0
;;;622 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;623 tmpreg |= RCC_SYSCLK;
00000c 4308 ORRS r0,r0,r1
;;;624 /* Store the new value */
;;;625 RCC->CFGR = tmpreg;
00000e 6050 STR r0,[r2,#4]
;;;626 }
000010 4770 BX lr
;;;627
ENDP

000012 0000 DCW 0x0000

|L17.20|
DCD 0x40021000

AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2

RCC_HSEConfig PROC
;;;275 */
;;;276 void RCC_HSEConfig(uint32_t RCC_HSE)
000000 4911 LDR r1,|L18.72|
;;;277 {
;;;278 /* Check the parameters */
;;;279 assert_param(IS_RCC_HSE(RCC_HSE));
;;;280 /* Reset HSEON and HSEBYP bits before configuring the HSE
------------------*/
;;;281 /* Reset HSEON bit */
;;;282 RCC->CR &= CR_HSEON_Reset;
000002 6809 LDR r1,[r1,#0]
000004 f4213180 BIC r1,r1,#0x10000
000008 4a0f LDR r2,|L18.72|
00000a 6011 STR r1,[r2,#0]
;;;283 /* Reset HSEBYP bit */
;;;284 RCC->CR &= CR_HSEBYP_Reset;
00000c 4611 MOV r1,r2
00000e 6809 LDR r1,[r1,#0]
000010 f4212180 BIC r1,r1,#0x40000
000014 6011 STR r1,[r2,#0]
;;;285 /* Configure HSE (RCC_HSE_OFF is already covered by the code section
above) */
;;;286 switch(RCC_HSE)
000016 f5b03f80 CMP r0,#0x10000
00001a d003 BEQ |L18.36|
00001c f5b02f80 CMP r0,#0x40000
000020 d10e BNE |L18.64|
000022 e006 B |L18.50|
|L18.36|
;;;287 {
;;;288 case RCC_HSE_ON:
;;;289 /* Set HSEON bit */
;;;290 RCC->CR |= CR_HSEON_Set;
000024 4908 LDR r1,|L18.72|
000026 6809 LDR r1,[r1,#0]
000028 f4413180 ORR r1,r1,#0x10000
00002c 4a06 LDR r2,|L18.72|
00002e 6011 STR r1,[r2,#0]
;;;291 break;
000030 e007 B |L18.66|
|L18.50|
;;;292
;;;293 case RCC_HSE_Bypass:
;;;294 /* Set HSEBYP and HSEON bits */
;;;295 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
000032 4905 LDR r1,|L18.72|
000034 6809 LDR r1,[r1,#0]
000036 f44121a0 ORR r1,r1,#0x50000
00003a 4a03 LDR r2,|L18.72|
00003c 6011 STR r1,[r2,#0]
;;;296 break;
00003e e000 B |L18.66|
|L18.64|
;;;297
;;;298 default:
;;;299 break;
000040 bf00 NOP
|L18.66|
000042 bf00 NOP ;291
;;;300 }
;;;301 }
000044 4770 BX lr
;;;302
ENDP

000046 0000 DCW 0x0000

|L18.72|
DCD 0x40021000

AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2

RCC_HSICmd PROC
;;;359 */
;;;360 void RCC_HSICmd(FunctionalState NewState)
000000 4901 LDR r1,|L19.8|
;;;361 {
;;;362 /* Check the parameters */
;;;363 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;364 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
000002 6008 STR r0,[r1,#0]
;;;365 }
000004 4770 BX lr
;;;366
ENDP

000006 0000 DCW 0x0000

|L19.8|
DCD 0x42420000

AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2

RCC_ITConfig PROC
;;;705 */
;;;706 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
000000 b129 CBZ r1,|L20.14|
;;;707 {
;;;708 /* Check the parameters */
;;;709 assert_param(IS_RCC_IT(RCC_IT));
;;;710 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;711 if (NewState != DISABLE)
;;;712 {
;;;713 /* Perform Byte access to RCC_CIR bits to enable the selected
interrupts */
;;;714 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
000002 4a06 LDR r2,|L20.28|
000004 7a52 LDRB r2,[r2,#9]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L20.28|
00000a 725a STRB r2,[r3,#9]
00000c e004 B |L20.24|
|L20.14|
;;;715 }
;;;716 else
;;;717 {
;;;718 /* Perform Byte access to RCC_CIR bits to disable the selected
interrupts */
;;;719 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00000e 4a03 LDR r2,|L20.28|
000010 7a52 LDRB r2,[r2,#9]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L20.28|
000016 725a STRB r2,[r3,#9]
|L20.24|
;;;720 }
;;;721 }
000018 4770 BX lr
;;;722
ENDP

00001a 0000 DCW 0x0000

|L20.28|
DCD 0x40021000

AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2

RCC_LSEConfig PROC
;;;834 */
;;;835 void RCC_LSEConfig(uint8_t RCC_LSE)
000000 2100 MOVS r1,#0
;;;836 {
;;;837 /* Check the parameters */
;;;838 assert_param(IS_RCC_LSE(RCC_LSE));
;;;839 /* Reset LSEON and LSEBYP bits before configuring the LSE
------------------*/
;;;840 /* Reset LSEON bit */
;;;841 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000002 4a0a LDR r2,|L21.44|
000004 7011 STRB r1,[r2,#0]
;;;842 /* Reset LSEBYP bit */
;;;843 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000006 4a0a LDR r2,|L21.48|
000008 f8821020 STRB r1,[r2,#0x20]
;;;844 /* Configure LSE (RCC_LSE_OFF is already covered by the code section
above) */
;;;845 switch(RCC_LSE)
00000c 2801 CMP r0,#1
00000e d002 BEQ |L21.22|
000010 2804 CMP r0,#4
000012 d108 BNE |L21.38|
000014 e003 B |L21.30|
|L21.22|
;;;846 {
;;;847 case RCC_LSE_ON:
;;;848 /* Set LSEON bit */
;;;849 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
000016 2101 MOVS r1,#1
000018 4a04 LDR r2,|L21.44|
00001a 7011 STRB r1,[r2,#0]
;;;850 break;
00001c e004 B |L21.40|
|L21.30|
;;;851
;;;852 case RCC_LSE_Bypass:
;;;853 /* Set LSEBYP and LSEON bits */
;;;854 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
00001e 2105 MOVS r1,#5
000020 4a02 LDR r2,|L21.44|
000022 7011 STRB r1,[r2,#0]
;;;855 break;
000024 e000 B |L21.40|
|L21.38|
;;;856
;;;857 default:
;;;858 break;
000026 bf00 NOP
|L21.40|
000028 bf00 NOP ;850
;;;859 }
;;;860 }
00002a 4770 BX lr
;;;861
ENDP

|L21.44|
DCD 0x40021020
|L21.48|
DCD 0x40021000

AREA ||i.RCC_LSICmd||, CODE, READONLY, ALIGN=2

RCC_LSICmd PROC
;;;867 */
;;;868 void RCC_LSICmd(FunctionalState NewState)
000000 4901 LDR r1,|L22.8|
;;;869 {
;;;870 /* Check the parameters */
;;;871 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;872 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
000002 6008 STR r0,[r1,#0]
;;;873 }
000004 4770 BX lr
;;;874
ENDP

000006 0000 DCW 0x0000

|L22.8|
DCD 0x42420480

AREA ||i.RCC_MCOConfig||, CODE, READONLY, ALIGN=2

RCC_MCOConfig PROC
;;;1287 */
;;;1288 void RCC_MCOConfig(uint8_t RCC_MCO)
000000 4901 LDR r1,|L23.8|
;;;1289 {
;;;1290 /* Check the parameters */
;;;1291 assert_param(IS_RCC_MCO(RCC_MCO));
;;;1292
;;;1293 /* Perform Byte access to MCO bits to select the MCO source */
;;;1294 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
000002 71c8 STRB r0,[r1,#7]
;;;1295 }
000004 4770 BX lr
;;;1296
ENDP

000006 0000 DCW 0x0000

|L23.8|
 DCD 0x40021000

AREA ||i.RCC_PCLK1Config||, CODE, READONLY, ALIGN=2

RCC_PCLK1Config PROC
;;;639 */
;;;640 void RCC_PCLK1Config(uint32_t RCC_HCLK)
000000 4601 MOV r1,r0
;;;641 {
;;;642 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;643 /* Check the parameters */
;;;644 assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;645 tmpreg = RCC->CFGR;
000004 4a03 LDR r2,|L24.20|
000006 6850 LDR r0,[r2,#4]
;;;646 /* Clear PPRE1[2:0] bits */
;;;647 tmpreg &= CFGR_PPRE1_Reset_Mask;
000008 f42060e0 BIC r0,r0,#0x700
;;;648 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
;;;649 tmpreg |= RCC_HCLK;
00000c 4308 ORRS r0,r0,r1
;;;650 /* Store the new value */
;;;651 RCC->CFGR = tmpreg;
00000e 6050 STR r0,[r2,#4]
;;;652 }
000010 4770 BX lr
;;;653
ENDP

000012 0000 DCW 0x0000

|L24.20|
DCD 0x40021000

AREA ||i.RCC_PCLK2Config||, CODE, READONLY, ALIGN=2

RCC_PCLK2Config PROC
;;;665 */
;;;666 void RCC_PCLK2Config(uint32_t RCC_HCLK)
000000 4601 MOV r1,r0
;;;667 {
;;;668 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;669 /* Check the parameters */
;;;670 assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;671 tmpreg = RCC->CFGR;
000004 4a03 LDR r2,|L25.20|
000006 6850 LDR r0,[r2,#4]
;;;672 /* Clear PPRE2[2:0] bits */
;;;673 tmpreg &= CFGR_PPRE2_Reset_Mask;
000008 f4205060 BIC r0,r0,#0x3800
;;;674 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
;;;675 tmpreg |= RCC_HCLK << 3;
00000c ea4000c1 ORR r0,r0,r1,LSL #3
;;;676 /* Store the new value */
;;;677 RCC->CFGR = tmpreg;
000010 6050 STR r0,[r2,#4]
;;;678 }
000012 4770 BX lr
;;;679
ENDP

|L25.20|
DCD 0x40021000

AREA ||i.RCC_PLLCmd||, CODE, READONLY, ALIGN=2

RCC_PLLCmd PROC
;;;406 */
;;;407 void RCC_PLLCmd(FunctionalState NewState)
000000 4901 LDR r1,|L26.8|
;;;408 {
;;;409 /* Check the parameters */
;;;410 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;411
;;;412 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
000002 6608 STR r0,[r1,#0x60]
;;;413 }
000004 4770 BX lr
;;;414
ENDP

000006 0000 DCW 0x0000

|L26.8|
DCD 0x42420000

AREA ||i.RCC_PLLConfig||, CODE, READONLY, ALIGN=2

RCC_PLLConfig PROC
;;;383 */
;;;384 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
000000 4602 MOV r2,r0
;;;385 {
;;;386 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;387
;;;388 /* Check the parameters */
;;;389 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
;;;390 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
;;;391
;;;392 tmpreg = RCC->CFGR;
000004 4b04 LDR r3,|L27.24|
000006 6858 LDR r0,[r3,#4]
;;;393 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
;;;394 tmpreg &= CFGR_PLL_Mask;
000008 f420107c BIC r0,r0,#0x3f0000
;;;395 /* Set the PLL configuration bits */
;;;396 tmpreg |= RCC_PLLSource | RCC_PLLMul;
00000c ea420301 ORR r3,r2,r1
000010 4318 ORRS r0,r0,r3
;;;397 /* Store the new value */
;;;398 RCC->CFGR = tmpreg;
000012 4b01 LDR r3,|L27.24|
000014 6058 STR r0,[r3,#4]
;;;399 }
000016 4770 BX lr
;;;400
ENDP
 |L27.24|
DCD 0x40021000

AREA ||i.RCC_RTCCLKCmd||, CODE, READONLY, ALIGN=2

RCC_RTCCLKCmd PROC
;;;898 */
;;;899 void RCC_RTCCLKCmd(FunctionalState NewState)
000000 4901 LDR r1,|L28.8|
;;;900 {
;;;901 /* Check the parameters */
;;;902 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;903 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
000002 6008 STR r0,[r1,#0]
;;;904 }
000004 4770 BX lr
;;;905
ENDP

000006 0000 DCW 0x0000

|L28.8|
DCD 0x4242043c

AREA ||i.RCC_RTCCLKConfig||, CODE, READONLY, ALIGN=2

RCC_RTCCLKConfig PROC
;;;884 */
;;;885 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
000000 4902 LDR r1,|L29.12|
;;;886 {
;;;887 /* Check the parameters */
;;;888 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
;;;889 /* Select the RTC clock source */
;;;890 RCC->BDCR |= RCC_RTCCLKSource;
000002 6a09 LDR r1,[r1,#0x20]
000004 4301 ORRS r1,r1,r0
000006 4a01 LDR r2,|L29.12|
000008 6211 STR r1,[r2,#0x20]
;;;891 }
00000a 4770 BX lr
;;;892
ENDP

|L29.12|
DCD 0x40021000

AREA ||i.RCC_SYSCLKConfig||, CODE, READONLY, ALIGN=2

RCC_SYSCLKConfig PROC
;;;569 */
;;;570 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
000000 4601 MOV r1,r0
;;;571 {
;;;572 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;573 /* Check the parameters */
;;;574 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
;;;575 tmpreg = RCC->CFGR;
000004 4a03 LDR r2,|L30.20|
000006 6850 LDR r0,[r2,#4]
;;;576 /* Clear SW[1:0] bits */
;;;577 tmpreg &= CFGR_SW_Mask;
000008 f0200003 BIC r0,r0,#3
;;;578 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;579 tmpreg |= RCC_SYSCLKSource;
00000c 4308 ORRS r0,r0,r1
;;;580 /* Store the new value */
;;;581 RCC->CFGR = tmpreg;
00000e 6050 STR r0,[r2,#4]
;;;582 }
000010 4770 BX lr
;;;583
ENDP

000012 0000 DCW 0x0000

|L30.20|
DCD 0x40021000

AREA ||i.RCC_USBCLKConfig||, CODE, READONLY, ALIGN=2

RCC_USBCLKConfig PROC
;;;733 */
;;;734 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
000000 4901 LDR r1,|L31.8|
;;;735 {
;;;736 /* Check the parameters */
;;;737 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
;;;738
;;;739 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
000002 6008 STR r0,[r1,#0]
;;;740 }
000004 4770 BX lr
;;;741 #else
ENDP

000006 0000 DCW 0x0000

|L31.8|
DCD 0x424200d8

AREA ||i.RCC_WaitForHSEStartUp||, CODE, READONLY, ALIGN=1

RCC_WaitForHSEStartUp PROC
;;;309 */
;;;310 ErrorStatus RCC_WaitForHSEStartUp(void)
000000 b538 PUSH {r3-r5,lr}
;;;311 {
;;;312 __IO uint32_t StartUpCounter = 0;
000002 2000 MOVS r0,#0
000004 9000 STR r0,[sp,#0]
;;;313 ErrorStatus status = ERROR;
000006 2400 MOVS r4,#0
;;;314 FlagStatus HSEStatus = RESET;
000008 2500 MOVS r5,#0
;;;315
;;;316 /* Wait till HSE is ready and if Time out is reached exit */
;;;317 do
00000a bf00 NOP
 |L32.12|
;;;318 {
;;;319 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
00000c 2031 MOVS r0,#0x31
00000e f7fffffe BL RCC_GetFlagStatus
000012 4605 MOV r5,r0
;;;320 StartUpCounter++;
000014 9800 LDR r0,[sp,#0]
000016 1c40 ADDS r0,r0,#1
000018 9000 STR r0,[sp,#0]
;;;321 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus ==
RESET));
00001a 9800 LDR r0,[sp,#0]
00001c f5b06fa0 CMP r0,#0x500
000020 d001 BEQ |L32.38|
000022 2d00 CMP r5,#0
000024 d0f2 BEQ |L32.12|
|L32.38|
;;;322
;;;323 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
000026 2031 MOVS r0,#0x31
000028 f7fffffe BL RCC_GetFlagStatus
00002c b108 CBZ r0,|L32.50|
;;;324 {
;;;325 status = SUCCESS;
00002e 2401 MOVS r4,#1
000030 e000 B |L32.52|
|L32.50|
;;;326 }
;;;327 else
;;;328 {
;;;329 status = ERROR;
000032 2400 MOVS r4,#0
|L32.52|
;;;330 }
;;;331 return (status);
000034 4620 MOV r0,r4
;;;332 }
000036 bd38 POP {r3-r5,pc}
;;;333
ENDP

AREA ||.data||, DATA, ALIGN=0

APBAHBPrescTable
000000 00000000 DCB 0x00,0x00,0x00,0x00
000004 01020304 DCB 0x01,0x02,0x03,0x04
000008 01020304 DCB 0x01,0x02,0x03,0x04
00000c 06070809 DCB 0x06,0x07,0x08,0x09
ADCPrescTable
000010 02040608 DCB 0x02,0x04,0x06,0x08

;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_rcc.c"
AREA ||.rev16_text||, CODE, READONLY
THUMB
EXPORT |__asm___15_stm32f10x_rcc_c_49e27980____REV16|
#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f10x_rcc_c_49e27980____REV16| PROC
#line 115

rev16 r0, r0
bx lr
ENDP
AREA ||.revsh_text||, CODE, READONLY
THUMB
EXPORT |__asm___15_stm32f10x_rcc_c_49e27980____REVSH|
#line 128
|__asm___15_stm32f10x_rcc_c_49e27980____REVSH| PROC
#line 129

revsh r0, r0
bx lr
ENDP

;*** End embedded assembler ***