VHDL Concurrent Assignment Examples

3.
2 Concurrent Signal Assignments with Logical Operators • 25
describes two wires in series. Automated synthesis tools will eliminate this unnecessary signal name.
This is not the same functionality that would result if this example was implemented as a sequentially
executed computer program. A computer program would execute the assignment of B to A first and then
assign the value of C to B second. In this way, B represents a storage element that is passed to A before
it is updated with C.
Each of the logical operators described in Sect. 3.1.2 can be used in conjunction with concurrent
signal assignments to create individual combinational logic circuits.
3.2.1 Logical Operator Example: SOP Circuit

Example 3.1 shows how to design a VHDL model of a standard sum of products’ combinational logic
circuit using concurrent signal assignments with logical operators.
Example 3.1
SOP logic circuit: VHDL modeling using logical operators
26 • Chapter 3: Modeling Concurrent Functionality
3.2.2 Logical Operator Example: One-Hot Decoder

A one-hot decoder is a circuit that has n inputs and 2n outputs. Each output will assert for one and
only one input code. Since there are 2n outputs, there will always be one and only one output asserted at
any given time. Example 3.2 shows how to model a 3-to-8 one-hot decoder in VHDL with concurrent
signal assignments and logic operators.
Example 3.2
3-to-8 One-hot decoder: VHDL modeling using logical operators
3.2 Concurrent Signal Assignments with Logical Operators • 27
3.2.3 Logical Operator Example: 7-Segment Display Decoder

A 7-segment display decoder is a circuit used to drive character displays that are commonly found in
applications such as digital clocks and household appliances. A character display is made up of seven
individual LEDs, typically labeled a–g. The input to the decoder is the binary equivalent of the decimal or
Hex character that is to be displayed. The output of the decoder is the arrangement of LEDs that will form
the character. Decoders with 2-inputs can drive characters “0” to “3.” Decoders with 3-inputs can drive
characters “0” to “7.” Decoders with 4-inputs can drive characters “0” to “F” with the case of the Hex
characters being “A, b, c or C, d, E, and F.”
Let’s look at an example of how to design a 3-input, 7-segment decoder by hand. The first step in the
process is to create the truth table for the outputs that will drive the LEDs in the display. We’ll call these
outputs Fa, Fb, . . ., Fg. Example 3.3 shows how to construct the truth table for the 7-segment display
decoder. In this table, a logic 1 corresponds to the LED being ON.
Example 3.3
7-Segment display decoder: truth table
If we wish to design this decoder by hand, we need to create seven separate combinational logic
circuits. Each of the outputs (Fa–Fg) can be put into a 3-input K-map to find the minimized logic
expression. Example 3.4 shows the design of the decoder from the truth table in Example 3.3 by hand.
Example 3.4
7-Segment display decoder: logic synthesis by hand
This same functionality can be modeled in VHDL using concurrent signal assignments with logical
operators. Example 3.5 shows how to model the 7-segment decoder in VHDL using concurrent signal
assignments with logic operators. It should be noted that this example is somewhat artificial because a
design would typically not be minimized before modeling in VHDL. Instead, model would be entered at
the behavioral level, and then the CAD tool would be allowed to synthesize and minimize the final logic.
Example 3.5
7-Segment display decoder: VHDL modeling using logical operators
3.2.4 Logical Operator Example: One-Hot Encoder

A one-hot binary encoder has n outputs and 2n inputs. The output will be an n-bit, binary code which
corresponds to an assertion on one and only one of the inputs. Example 3.6 shows the process of
designing a 4-to-2 binary encoder by hand (i.e., using the classical digital design approach).
Example 3.6
4-to-2 Binary encoder: logic synthesis by hand
In VHDL this can be implemented directly using logical operators. Example 3.7 shows how to model
the encoder in VHDL using concurrent signal assignments with logical operators.
Example 3.7
4-to-2 Binary encoder: VHDL modeling using logical operators
3.2.5 Logical Operator Example: Multiplexer

A multiplexer is a circuit that passes one of its multiple inputs to a single output based on a select
input. This can be thought of as a digital routing switch. The multiplexer has n select lines, 2n inputs, and
one output. Example 3.8 shows the process of designing a 4-to-1 multiplexer using concurrent signal
assignments and logical operators.
Example 3.8
4-to-1 Multiplexer: VHDL modeling using logical operators
3.2.6 Logical Operator Example: Demultiplexer

A demultiplexer works in a complementary fashion to a multiplexer. A demultiplexer has one input
that is routed to one of its multiple outputs. The output that is active is dictated by a select input. A demux
has n select lines that choose to route the input to one of its 2n outputs. When an output is not selected, it
outputs a logic 0. Example 3.9 shows the process of designing a 1-to-4 demultiplexer using concurrent
signal assignments and logical operators.
Example 3.9
1-to-4 Demultiplexer: VHDL modeling using logical operators
CONCEPT CHECK
CC3.2 Why does modeling combinational logic in its canonical form with concurrent signal
assignments with logical operators defeat the purpose of the modern digital design flow?
(A) It requires the designer to first create the circuit using the classical digital
design approach and then enter it into the HDL in a form that is essentially a
text-based netlist. This doesn’t take advantage of the abstraction capabilities
and automated synthesis in the modern flow.
(B) It cannot be synthesized because the order of precedence of the logical
operators in VHDL doesn’t match the precedence defined in Boolean algebra.
(C) The circuit is in its simplest form so there is no work for the synthesizer to do.
(D) It doesn’t allow an else clause to cover the outputs for any remaining input
codes not explicitly listed.

VHDL Concurrent Assignment Examples

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VHDL Concurrent Assignment Examples

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3.

2 Concurrent Signal Assignments with Logical Operators • 25

3.2.1 Logical Operator Example: SOP Circuit

3.2.2 Logical Operator Example: One-Hot Decoder

3.2.3 Logical Operator Example: 7-Segment Display Decoder

3.2.4 Logical Operator Example: One-Hot Encoder

3.2.5 Logical Operator Example: Multiplexer

3.2.6 Logical Operator Example: Demultiplexer

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