Dept.

of Electronics and Communication Engineering

National Institute of Technology Manipur

STUDY MATERIAL
Microprocessors (EC 301)

Prepared by:
Richard Ningthoujam
Architecture of 8085 Microprocessor
ALU:

i. Addition
ii. Subtraction
iii. Logical AND
iv. Logical OR
v. Logical EX OR
vi. Complement
vii. Increment
viii. Decrement
ix. Left shift, Rotate left, Rotate right
x. Clear

Timing and control unit:

 It provides status, control and timing signals which are required for the execution of
instructions and operation of memory and I/O devices.
 It controls data flow between CPU and Peripherals including memory.

Registers:

 Registers are used for temporary storage and manipulation of data and instructions.
 Data remains in the registers till they are sent to memory or I/O devices.
 If the number of registers is more, it requires less transfer of data to/from the memory.
 Accumulator (ACC):
o It is 8-bit used to hold one of the operands of an arithmetic or logical operation, the
other operand may be in any general purpose register or memory.
o After the arithmetic or logical operation, accumulator holds the result.
 General purpose registers:
o 8-bit registers namely B, C, D, E, H, L.
o They can be combined as register pairs B-C, D-E, H-L to hold 16 bit data.
o H-L pair can be as memory pointer holding the 16-bit address of a memory location.
 Program Counter (PC):
o 16-bit register which holds the memory address of the next instruction to be
executed.
o It is incremented during the execution of an instruction, so that it points to the next
instruction to be executed.
o E.g. if the PC holds 2050H, then the instruction located at 2050 will be executed,
while it is being executed PC content will be incremented to 2051H (location of the
next instruction to be executed), while execution instruction of 2051 PC will again be
incremented to 2052H, likewise it will be executed and incremented till the end of
the program. PC will keep of track of the execution of the program.
 Stack Pointer (SP):
o It keeps track of the stack, a pointer. (will see in detail in later).
 Instruction Register:
o It holds the opcode (operation code or instruction code) of the instruction which is
being decoded and executed.
 Temporary Register:
o Used by the microprocessor for holding data, not accessible to the programmer.

 Flags (Program status word):

o It indicates the status of the ALU.
o Carry Flag (CS): if a carry is produces after an arithmetic instruction, CS is set to 1
else it is 0.
o Parity Flag (P): If the result of an arithmetic or logical operation has even no of 1s
else it is 0.
o Auxiliary Carry Flag (AC). If there is carry out from 4th bit to 5th bit (or bit number 3 to
bit number 4), it is set to 1 else it is 0.
o Zero Flag (Z): if an arithmetic or logical operation results to 0, it is set to 1 else it is 0.
o Sign Flag (S): it is set to 1 if the result is negative, 0 if the number is positive.
Pin diagram of 8085

A8 – A15: Address bus for carrying most significant bits of the memory address or 8 bits of
I/O address.
AD0 – AD7: Time multiplex address/Data bus. 8 bits of the least memory address or I/O
address during the first clock cycle, then 8 bit data during second and third clock cycles.
ALE: Address Latch Enable. It goes high during 1st clock cycle and latches the lower 8 bit
address to memory or external latch.
IO/Mbar: Status signal which distinguishes whether the address is for memory or I/O. High
for I/O access and low for memory access.
S0, S1: Status signals to distinguish the various types of operation.

S1 S0 Operations

O O HALT

0 1 WRITE

1 0 READ

1 1 FETCH
RDbar: when this signal is low, READ operation from memory or Input device is performed.
WRbar: When this signal is low, WRITE operation to memory or output device is performed.
READY: when it is high, it input or output device is ready to send or receive data. When it is
low, microprocessor waits till it becomes high.
HOLD: data address bus are shared between microprocessor and other devices in the computer
system. When another devices requires address and data buses for data transfer, it sends HOLD
signal to the microprocessor. Upon receiving the hold signal, the microprocessor sends back
HLDA (acknowledge) signal to the requesting device. Microprocessor leaves control over the
buses after completing the current machine cycle, but the internal processing continues. It
regains the control after removing the HOLD signal.
HLDA: Hold acknowledge signal by the microprocessor. After removing HOLD, HLDA goes
low.
INTR: Interrupt signal sent by an external device to the microprocessor informing that it is
ready to transfer data or to initiate certain operation. When it is high, microprocessor suspends
the execution of its normal sequence of instructions after completing the current instruction at
hand, then it attends the interrupting device.
INTAbar: Interrupt acknowledge signal sent by microprocessor after receiving INTR signal.
RST 5.5, 6.5, 7.5 and TRAP: When any of these instruction is recognised, the next instruction
is executed from a fixed location in the memory.
Line Location of next
instruction
TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
 Line Priority
TRAP highest
RST 7.5
RST 6.5
RST 5.5
INTR Lowest

RESET IN: it resets the program counter to zero.

RESET OUT. It indicates that the CPU is being reset.
X1, X2: terminals to be connected to external crystal oscillator.
CLK: clock output for user for other digital ICs, its frequency is same at which the processor
operates.
SID: Serial input data.
SOD: Serial output data.
Addressing Modes of 8085:
The process of specifying the data to be operated on by the instruction is called addressing.

The various formats for specifying operands are called addressing modes. The 8085 has five types of addressing
modes:

I. Direct addressing mode

II. Register addressing mode

III. Register indirect addressing mode

IV. Immediate addressing mode

V. Implicit addressing

I. Direct addressing mode: The address of the operand (data) is given in the instruction itself.

E.g. STA 2400 IN 02

II. Register addressing mode: The operand is in one of the general purpose registers. The opcode specifies the
address of the register(s) in addition to the operation to be performed.

E.g. MOV A, B ADD B

III. Register indirect addressing mode: In this addressing mode the address of the operand is specify by a register
pair.

E.g. LXI H, 2000H // H represents register pair H-L which is being used as a pointer.

MOV A, M // M indicates the source is from memory address whose address is currently hold
by the register pair H-L

IV. Immediate addressing mode: In this addressing mode operand is specify with in the instruction.

E.g. MVI A, 05 H // Move immediate data 05H to Accumulator.

V) Implicit addressing mode: This instruction operates on the content of the accumulator. They don’t required
operand address.

E.g. CMA //Complement the content of accumulator.

INSTRUCTIONS of 8085
As Intel 8085 is an 8-bit microprocessor. It handles 8-bit data at a time. One byte consists of 8-bits. A
memory location for Intel 8085 microprocessor is designed to accumulate 8-bit data. If 16-bit data are to be stored,
they are stored in consecutive memory locations. The address of memory location is 0f 16-bit i.e. 2 bytes.

The various techniques to specify data for instructions are:

(1) 8-bit or 16-bit data may be directly given in the instruction itself.

(2) The address of the memory location, I/O port or I/O device, where data resides, may be given in the instruction
itself.

(3)In some instructions only one register is specified. The content of the specified register is one of the operand
and other operand is the accumulator.

(4) Some instructions specify two registers. The contents of the registers are the required data. Due to different
ways of specifying data for instruction are not of same length.
So there are three types of instructions of Intel 8085:

(1) Single byte instruction

(2)2-byte instruction

(3)3-byte instruction

Single-Byte instruction.

The content information regarding operands in the opcode itself .These are of one byte.

E.g. MOV A, B //Move the content of register B to A

78H is opcode for MOV A, B. The binary form of opcode 78H is 01111000. The first two bits i.e. 01 for MOV
operation; the next 3 bits i.e. 111 for register A and last 3 bits 000 are for register B.

Two-Byte instruction.

In case of two byte instruction the 1st byte of the instruction is opcode and 2nd byte is either data or address. Both
bytes are stored in two consecutive memory locations.

E.g. MVI B, 05 //Move 05 to register B

06, 05 is the opcode form of MVI B, 05.

Here in this case the 1st byte i.e. 06 is the opcode for MVI B and 2nd byte i.e. 05 is the data which is to be moved
to register B.

Three-Byte instruction.

In case of three bytes instruction the 1st byte of instruction is opcode and 2nd and 3rd byte of instruction are either
16-bit data or 16-bit address. They are stored in three consecutive memory locations.

E.g. LXI H, 2400H //load H-L pair with 2400H

21, 00, 24 is the opcode of LXI H, 2400H.

Here 1st byte i.e. 21 is the opcode for instruction LXI H. The 2nd byte i.e. 00 is 8 LSBs of data which is loaded
in to register L. The 3rd byte i.e. 24 is 8 MSBs of data which is loaded in to register H.

INSTRUCTIONS SET:
DATA TRANSFER GROUP

1. MOV r1, r2 (Move data; move the content of one register to another)

[r1]←[r2]. State: none. Addressing: register addressing. Machine cycle:1.

The content of resister r2 is move to register is moved to register 1.For example, the instruction

MOV A, B moves the contents of resister b to register A. The instruction MOV B, A moves the content of register
A to register B. The time for the execution of this instruction is 4 clock period. One clock period is called is state.
No lag is affected.

2. MOV r, M (move the content of memory to register)

[r] ← [[H-L]]. State: 7. flag: none. Addressing: register indirect. Machine cycle: 2.

The content of memory location, whose address is in H-L pair is moved to register r.

Example

LXI H, 2000H load H-L pair by 2000H

MOV B, M Move the content of the memory location 2000H to register B.

HLT Halt

In this example the instruction LXI H, 2000H loads H-L pair with 2000Hwhich is the address of a memory
location. Then the instruction MOV B, M will move the content of memory location 2000H to register B.

3. MOV M, r. (Move the content of register to memory)

[[H-L]] ← [r]. States: 7. Flag: none. Addressing: register indirect. Machine cycle: 2.

The content of register r is moved to the memory location address by H-L pair. For example, MOV M,C moves
the content of register c to the memory location whose address is in H-L pair.

4. MVI r, data. (Moves immediate data to register)

[r] ←data. States: 7. Flag: none. Adressing: immediate. Machine cycle : 2.

The 1st byte of the instruction is its opcode. The 2nd byte of the instruction is the data which is moved to register
r. For example, the MVI A,05 moves 05 to register A. In the code form it is written as 3E,05.The opcode for MVI
A is 3E,05.The opcode for MVI A is 3E and 05 is the data which is to be moved to register A.

5. MVI M, data (Move immediate data to memory)

[[H-L]] ←data. States: 10. Flags: none. Addressing: immediate/reg. Indirect. Machine cycle: 3.

The data is moved to the memory location whose address is in H-L pair.

Example

LXI H, 2400H Load H-L pair with 2400H.

MVI M, 08 Move 08 to the memory location 2400H.

HLT Halt.

In the above example the instruction LXI H, 2400H Loads H-L pair with 2400H which is the address of a memory
location. Then the instruction MVI M, 08 will move 08 to memory location 2400H.In the code form it is written
as 36,08.The opcode for MVI M is 36 and 08 is the data which is to be moved to the memory location 2400H.

6. LXI rp, 16-bit data (load register pair immediate)

[rp] ←data 16 bits, [rh] ←8 MSBs, [rl] ←8LSBs of data

States: 10, Flags: none, Addressing: Immediate, Machine Cycles: 3

This instruction loads 16 bit immediate data into register pair rp. This instruction is for register pair; only high
order register is mentioned after the instruction. For example; H in the LXI H stands for H-L pair. Similarly, LXI
B is for B-C pair. LXI H, 2500H loads 2500H into H-L pair. H with 2500H denotes that the data 2500 is in
hexadecimal. In the code form it is written as 21,00,25. The 1st byte of the instruction 21 is the opcode for LXI
H. The second byte 00 is of 8LSBs of the memory address and it is loaded inyo register L. The third byte 25 is 8
MSBS of the data and it is loaded into register H

7. LDA addr (Load accumulator direct)

[A] ← [addr] States: 13, flags :none, Addressing:Direct, Machine cycle:4

The content of memory location, whose address is specified by the 2nd and 3rd bytes of the instruction; is loaded
into the accumulator.The instruction LDA 2400H will load the content of the memory location 2400H into the
accumulator .Inthe code form it is written as 3A,00,24.The 1st byte 3A is the opcode of the instruction . The 2nd
byte 00 is of 8LSBs of the memory address. The 3rd byte 24 is 8Msbs of the memory address.

8. STA addr (store accumulator direct)

[addr← [A].States:13.Flags:none.Addressing:direct.Machine cycle: 4.

The content of the accumulator is stored in the memory location whose address is specified by the 2nd and 3rd
byte of the instruction. STA 2000H will store the content of the accumulator in the memory location 2000H.

9. LHLD addr (load H-L pair direct).

[L] ← [addr], [H] ← [addr+1].States:16.Flags:none.Addressing:direct.Machine cycle: 5.

The content of the memory location, whose address is specified by 2nd and 3rd bytes of the instruction, is loaded
into rsister L.The content of the next memory location is loaded into resister H. For example, LHLD 2500H will
load the content of the memory location 2500H into register L. The content of the memory location 2501H is
loaded into register H.

10. SHLD addr (store H-L pair direct)

[addr] ← [L],[addr+1] ← [H].States:16,Flags:none,Addressing:direct.Machine cycles:5

The content of the register L is stored in the memory location whose address is specified by the 2nd and 3rd bytes
of the instruction.The content of register H is stored in the next memory location .For example ,SHLD 2500H will
stored the content of register L in the memory location 2500H.The content of the register H is stored in the memory
location2501H.

11. LDAX rp (LOAD accumulator indirect)

[A] ← [[rp]].states:7, Flags:none, Addressing: register indirect, Machine cycle:2

The content of the memory location, whose address is in the register pair rp, is loaded into the accumulator.For
example ,LDAX B will load the content of the memory location,whose address is in B-C pair,into the
accumulator.Th instruction is used only for B-C and D-E register pairs.

12. STAX rp (store accumulator indirect)

[[rp]] ← [A].States:7.Flags: none. Addressing: register indirect. Machine cycles: 2.

The content of the accumulator is stored in the memory location whose address is in the register pair rp. For
example, STAX D will stored the content of the accumulator in the memory location whose address is in D-E
pair. This instruction is true only for register pair B-C and D-E.

13. XCHG (Exchange the content of the H-L with D-E pair)

[H-L]↔[D-E].States:4,Flags:none,Addressing : register, Machine cycle:1.

The content of H-L pair are exchanged with contents of D-E pair.

ARITHMETIC GROUP

The Instruction of this group performs arithmetic operation such as Addition, Subtraction,

Increment or Decrement of the content of the register or memory.

1. Add r (Add register to accumulator)

[A] ← [A] + [r]

The content of register r is added to the content of the accumulator, and the sum is placed in the accumulator.

2. ADD M (Add memory to accumulator)

[A] ← [A] + [H-L]

The content of the memory location addressed by H-L pair is added to the content to the accumulator. The sum is
placed in the accumulator.

3. ADC r (Add register with carry to accumulator)

[A] ← [A] + [r] + [CS]

The content of register r and carry status are added to the content of the accumulator. The sum is placed in the
accumulator.

4. ADC M (Add memory with carry to accumulator)

[A] ← [A] + [H-L] + [CS]

The content of the memory location addressed by H-L pair add carry status are added to the content of the
accumulator. The sum is placed in the accumulator.

5. ADI data (Add immediate data to accumulator)

[A] ← [A] + data

The immediate data is added to the content to the accumulator. The 1st byte of the instruction is its opcode. The
2nd byte of the instruction is data and it is added to the content of the accumulator. The sum is placed in the
accumulator.

FOR EXAMPLE:

The instruction ADI 08 will add 08 to the content of the accumulator and placed the result in the accumulator. In
code form the instruction is written as C6 08.

BRANCH CONTROL GROUP

The instruction of this group change the normal sequence of the program.

There are of two types of branch instruction

• Conditional branch instruction

• Unconditional branch instruction

Conditional branch instruction:

It transfer the program to the specified level when certain condition is satisfied.

Unconditional branch instruction:

It transfer the program to the specified level unconditionally.

Example: JMP addr (label).

*Conditional Jump addr (label):

1. JZ addr (label):-Jump if the result is zero, Z=1.

2. JNZ addr (label):-jump if the result is not zero, Z=0.

3. JC addr (label):-jump if there is a carry, CS=1.

4. JNC addr (label):-jump if there is no carry, CS=0.

5. JP addr(label):-jump if the result is plus,S=0.

6. JM addr(label):-jump if the result is minus,S=1.

7. JPE addr(label):-jump if even parity,P=1.

8. JPO addr(label):-jump if odd parity,P=0.

*CALL addr(label):-

• Used in unconditional branch instruction.

• Used to call a sub-routine, before control its transfer to the subroutine.

• The content of program counter is saved in the stack.

• Call is 3-byte instruction.

*Conditional CALL addr(label):

1. CC addr(label):-call subroutine if carry status CS=1.

2. CNC addr(label):-call subroutine if carry status CS=0.

3. CZ addr(label):-call subroutine if the result is zero ;the zero status Z=1.

4. CNZ addr(label):-call subroutineif the result is not zero; the zero status Z=0.

5. CP addr(label):-call subroutineif the result is plus; the sign status S=0.

6. CM addr(label):-call subroutineif the result is minus; the sign status S=1.

7. CPE addr(label):-call subroutine if even parity; the parity status P=1.

8. CPO addr(label):-call subroutine if odd parity; the parity status P=0.

*RET (Return sub routine):-

• It is used at the end of a subroutine.

• Before the execution of a subroutine the address of the next instruction of the main program is saved in the stack.

• The content of the stack pointer is incremented by 2 to indicate the new stack top.

*Conditional Return:-

1. RC:-Return from subroutine if carry status CS=1.

2. RNC:-Return from subroutine if carry status CS=0.

3. RZ:-Return from subroutine if the result is zero;the zero status Z=1.

4. RNZ:-Return from subroutineif the result is not zero;the zero status Z=0.

5. RP:-Return from subroutineif the result isplus;the sign statusS=0.

6. RM:-:-Return from subroutine if the result is minus ,the sign status S=1.

7. RPE:-:-Return from subroutine if even parity,the parity status P=1.

8. RPO:-_:-Return from subroutine if odd parity,the parity status P=0.

RST n (restart) Instruction:-

• It is a one-word call instruction the content of a program counter is saved in the stack,the program jumps to the
instruction ,starting at restart location.

• The address of the restart location is 8 times n. There are 8 RST restart instruction carrying from RST0-RST7.

• These are software interrupts used by the programmer to interrupt the microprocessor.

• The restart instruction and location are as follows:-

Instruction Opcode Restart Location

RST0 C7 0000

RST1 CF 0008
RST 2D7 0010

RST3 DF 0018

RST4 E7 0020

RST5 EF 0028

RST6 F7 0030

RST7 FF 0038

PCHL instruction:-

• Jump to address specified by H-L pair.

• The content of H-L pair are transferred to the program counter.

• The content of register L will be loaded to 8 LSBs of PC and content of register H will be loaded to 8 MSBs.

TIMING DIAGRAM FOR I/O READ AND MEMORY READ

I/O READ:

1. In I/O read cycle the microprocessor reads the data available at an input port/input device. The data is placed
in accumulator.

2. An I/O read cycle it is similar to memory read cycle except that signal I/O/M(bar) goes high in case of I/O read.

3. It indicates that the address on the address bus is for an input device.

4. It case of I/O device or I/O port the address is only 8 bit long. So the address of I/O device is duplicated on both
address and address data bus.

Ex-IN instruction is an example of I/O READ.

5. It is 2bytes long. So it requires 3 machine cycles such as opcode fetch cycle, memory read cycle to read the
input port address, I/O read cycle to read data from input port.
MEMORY READ CYCLE

1. In memory read cycle the microprocessor read the content of memory location

2. The content is the placed in either accumulator any other CPU register.

Ex-MVI A, 05H

3. In this cycle IO/M(bar) goes low indicate that the address is for memory.

4. S1 and S0 are set to be 1 and 0 respectively for read operation.

5. Address lines A8 to A15 carry 8MSBs of memory address of data.

6. Address lines AD0 to AD7 carry 8LSBs of memory address of data.

7. During T2 8LSBs of address is latched AD0

8. RD(bar) goes low in T2 enable the memory read operation.

9. Now data is placed in data bus during T3 data enters the CPU.

Ex-LXI H, 2000H

MEMORY WRITE CYCLE

1. In a memory write cycle the CPU sends data from accumulator or any other register to memory.

2. The status signal S0 and S1 are 1 and 0 respectively for write operation.

3. It goes low in T2 indicating that the write operation to be performed.

4. During T2 the address/data bus is not disable but the data to be sent out to memory placed on the address/data
bus.

5. as soon as goes high in T3, the write operation is terminated.

Example: 1. MOV M, A

2. STA 2000H
I/O WRITE CYCLE

1. In an I/O write cycle the CPU sends data to an I/O port or an I/O device from the accumulator.

2. It is similar to a memory write cycle except that IO/M goes high indicating that the address sent by CPU is for
I/O device or I/O port.

3. The address of an I/O port (8-bit) is duplicated on both address and address/data bus.

4. The OUT instruction is used for I/O write operation. It is a 2 byte instruction and required 3 machine cycle.MC1
is the opcode fetch cycle.MC2 is a memory read cycle for reading the I/O device address from memory.MC3 is
an I/O write cycle for saving accumulator data to the I/O device or I/O port.
EXAMPLES OF ASSEMBLY LANGUAGE PROGRAMS
1. ALP FOR ADDITION OF TWO 8-BIT NUMBERS; SUM 8-BIT

Mnemonics Operand Comments

LXI H, 2501 H Get Address of 1st No. in H-L pair

MOV A, M 1st no. in accumulator

INX H Increment content of H-L pair

ADD M Add 1st no. and 2nd no.

STA 2503 H Store sum in 2503 H.

HLT Stop the program.

DATA

2501- 49 H

2502- 56 H

The sum is stored in memory location 2503 H.

RESULT

2503- 9F H.

2. ALP FOR SUBTRACTION OF TWO 8-BIT NUMBERS

Mnemonics Operand Comments

LXI H, 2501 H Get address of 1st no. in H-L pair.

MOV A, M 1st no. in accumulator.

INX H Content of H-L pair in 2502 H.

SUB M 1st no. – 2nd no.

INX H Content of H-L pair becomes 2503 H.

MOV M, A Store results in 2503 H.

HLT Stop the program.

DATA

2501- 49 H

2502- 32 H

The result is stored in memory location 2503 H.

RESULT

2503- 17 H.

3. ALP FOR ADDITION OF TWO 8-BIT NUMBERS; SUM: 16-BITS

Labels Mnemonics Operand Comment

LXI H, 2501 H address of 1st no. in H-L pair.

 MVI C, 00 MSBs of sum in register C. Initial value = 00.

MOV A, M 1st no. in accumulator.

INX H Address of 2nd no. 2502 in H-L pair.

ADD M 1st no. + 2nd no.

JNC AHEAD Is carry? No, go to the label AHEAD.

INR C Yes, increment C.

AHEAD: STA 2503 H LSBs of sum in 2503 H.

MOV A, C MSBs of sum in accumulator.

STA 2504 H MSBs of sum in 2504 H.

HLT Stop the program.

DATA

2501- 98 H

2502- 9A H

RESULT

2503- 32 H, LSBs of sum.

2504- 01 H, MSBs of sum.

4. ALP FOR DECIMAL ADDITION OF TWO 8-BIT NUMBERS; SUM: 16-BITS

Labels Mnemonics Operand Comment

LXI H, 2501 H address of 1st no. in H-L pair.

MVI C, 00 MSDs of sum in register C. Initial value = 00.

MOV A, M 1st no. in accumulator.

INX H Address of 2nd no. 2502 in H-L pair.

ADD M 1st no. + 2nd no.

DAA Decimal adjust.

JNC AHEAD Is carry? No, go to the label AHEAD.

INR C Yes, increment C.

AHEAD: STA 2503 H LSBs of sum in 2503 H.

MOV A, C MSBs of sum in accumulator.

STA 2504 H MSBs of sum in 2504 H.

HLT Stop the program.

DATA

2501- 84 D

2502- 75 D

RESULT
2503- 59 D, LSDs of the sum.

2504- 01 D, MSDs of the sum.

5. ALP FOR 8-BIT DECIMAL SUBTRACTION

Mnemonics Operand Comments

LXI H, 2502 H Get address of 2nd no. in H-L pair.

MVI A, 99 Place 99 in accumulator.

SUB M 9’s compliment of 2nd no.

INR A 10’s compliment of 2nd no.

DCX H Get address of 1st no.

ADD M Add 1st no. & 10’s compliment 2nd no.

DAA Decimal Adjustment.

STA 2503 H Store result in 2503 H.

HLT Stop the program.

DATA

2501- 96 H.

2502- 38 H.

The result is stored in memory location 2503 H.

RESULT

2503- 58 H.

6. ALP FOR 8-BIT MULTIPLICATION: PRODUCT 16 BIT

Label Mnemonics Operand Comments

LHLD 2501 H Get multiplicand in H-L pair.

XCHG Multiplicand in D-E pair.

LDA 2503 H Multiplier in accumulator.

LXI H, 0000 Initial value of the product =00 in H-L pair.

MVI C, 08 Count = 8 in register C.

LOOP: DAD H shift partial product left by 1 bit.

RAL Rotate multiplier left 1 bit. Is multipliers bit=1?

JNC AHEAD No, go to AHEAD.

DAD D Product=product + multiplicand.

AHEAD: DCR C Decrement count.

JNZ LOOP

SHLD 2504 H Store result.

HLT Stop the program.

DATA

2501-84 H , LSBs of Multiplicand.

2502-00, MSBs of Multiplicand.

2503-56 H, Multiplier.

RESULT

2504-58 H, LSBs of product.

2505-2C H , MSBs of product.

7. ALP FOR 8-BIT DIVISION

Label Mnemonics Operands Comments

LHLD 2501 H Get dividend in H-L pair.

LDA 2503 H Get divisor from 2503 H.

MOV B, A Divisor in register B.

MVI C, 08 Count = 08 in register C.

LOOP: DAD H Shift dividend and quotient left by one bit.

MOV A, H Most significant bits of dividend in accumulator.

SUB B Subtract divisor from most significant bits of dividend.

JC AHEAD Is most significant part of Dividend > divisor ? No, Go to AHEAD.

MOV H, A Most significant bits of dividend in register H.

INR L Yes, add 1 to quotient.

AHEAD: DCR C Decrement count.

JNZ LOOP Is count =0? No,Jump to LOOP.

SHLD 2504 H Store quotient in 2504 and remainder in 2505 H.

HLT Store the program.

DATA

2501-9B H, LSBs of dividend.

2502-48 H, MSBs of dividend.

2503-1A H, divisor.

RESULT

2504-F2, Quotient.

2505-07, Remainder.

8. ALP TO SHIFT AN 8-BIT NUMBER LEFT BY ONE BIT

Example. Shift 65 left by one bit.

The binary representation of 65 is given below:

65=0110 0101
(6) (5)

Result of shifting

65 left by one bit =1100 1010=CA

(C) (A)

To shift a number left by one bit the number is added to itself. If 65 is added to 65, the result is

CA as shown below.

65=0110 0101

+ 65=0110 0101

1100 1010=CA

The number is placed in memory 2501 H. The result is to be stored in memory 2502 H.

PROGRAM

Memory Address Machine Codes Mnemonics Operands Comments

2000 3A,01,25 LDA 2501H Get data in accumulator

2003 87 ADD A Shift it left by one bit

2004 32,02,25 STA 2502H Store result in 2502H

2007 76 HLT Halt

DATA

2501-65 H

Result

2502-CA H

The instruction LDA 2501 H transfers the number from memory location 2501 H to the accumulator. ADD A
adds the contents of the accumulator to itself. The result is twice the number and thus the number is shifted left
by one bit. This program does not take carry into account after ADD instruction. If numbers to be handled are
likely to produce carry the program may be modified to store it.

9. ALP TO SHIFT A 16-BIT NUMBER LEFT BY ONE BIT

Shift 7596 H left by one bit. 7596=0111 0101 1001 0110

(7) (5) (9) (6)

Result of shifting left by one bit =1110 1011 0010 1100=EB2C

(E) (B) (2) (C)

The number is placed in the memory locations 2501 and 2502 H.

The result is to be stored in the memory locations 2503 and 2504 H.

PROGRAM

Memory Address Machine Codes Mnemonics Operands Comments

2000 2A,01,25 LHLD H 2501 H Get data in H-L pair

2003 29 DAD H Shift left by one bit

2004 22,03,25 SHLD 2503 H Store result in 2503 and 2504 H

2007 76 HLT Stop

Example 1 Example 2

DATA

2501-96 H, LSBs of the number. 2501-BF, LSBs of the number.

2502-75 H, MSBs of the number. 2502-00, MSBs of the number.

Result

2502-2C, LSBs of the result. 2503-7E, LSBs of the result.

2504-EB, MSBs of the result. 2504-01, MSBs of the result.

The 16-bit number has been placed in two consecutive memory location 2501 and 2502 H. The instruction LHLD
2501 H transfers the 16-bit number from 2501 and 2502 H to H-L pair. DAD H is an instruction for 16-bit addition.
It adds the contents of H-L pair to itself. Thus, the 16-bit number is shifted left by one bit. The 16-bit result is
stored in the memory locations 2503 and 2504 H by SHLD instruction. In some cases there may be carry after the
execution of instruction DAD H. In that case carry may be stored in some register. The program may be modified
accordingly. If the shifting of an 8-bit number gives a result which is more than 8-bits, the problem can be tackled
using the technique of shifting 16-bit number in Example 2.

10. ALP TO MASK OFF LEAST SIGNIFICANT 4 BITS OF AN 8-BIT NUMBER

Example.

Number=A6

=1010 0110

(A) (6)

Result=06=0000 0110

(A) (0)

We want to make off the least significant 4 bits of a given number. The LSD of the given number A6 is 6. It is to
be cleared (masked off) i.e. it is to be made equal to zero. The MSD of the number A6 is A. In the binary form it
is 1010. It is not to be affected. If this number is added with 1111 i.e. F, it will not be affected. Similarly, the LSD
of the number is 6. In the binary form it is represented by 0110. If it is added with 0000, it becomes 0000 i.e. it is
cleared. Thus, if thenumber A6 is added with F0, the LSD of the number is masked off.

PROGRAM

Address Machine Codes Mnemonics Operands Comments

2000 3A,01,25 LDA 2501 H Get data in accumulator

2003 E6,F0 ANI F0 Mask off the least significant 4 bits

2005 32,02,25 STA 2502 H Store result in 2502 H

2008 76 HLT Stop

DATA

2501-A6

Result

2502-A0
The instruction LDA 2501 H transfers the content of memory location 2501 H i.e. the given number to the
accumulator. ANI F0 logically ANDs the content of the accumulator with F0 to clear the least significant 4 bits
of the number. STA 2502 H stores the result in memory location 2502 H. HLT stops the program.

11. ALP TO MASK OFF MOST SIGNIFICANT 4 BITS OF AN 8-BIT NUMBER

Example.

Number=A6

=1010 0110

(A) (6)

Result=06=0000 0110

(0) (6)

To mask off 4 most significant bits of a number, 4 MSBs are added with 0000. The least significant bits are not
to be affected and therefore, they are added with 1111 i.e. F. Thus, if an 8-bit number is added with 0F, the 4 most
significant bits are cleared.

PROGRAM

Address Machine Codes Mnemonics Operands Comments

2000 3A,01,25 LDA 2501 H Get data in accumulator

2003 E6,0F ANI 0F Mask off the most significant 4 bits

2005 32,02,25 STA 2502 H Store result in 2502 H

2008 76 HLT Stop

DATA

2501-A6

Result

2502-06

The instruction LDA 2501 H transfers the contents of memory location 2501 H to the accumulator. ANI 0F
logically ANDs the content of the accumulator with 0F to clear the most significant 4 bits of the number. STA
2502 H stores the result in 2502 H. HLT stops the program.

12. ALP to find larger of two numbers

Example1. Find the larger of 98H and 87H.

The first number 98H is placed in the memory location 2501H.

The 2nd number 87H is placed in the memory location 2502H

The result is stored in the memory location 2503H.

The numbers are represented in the form of hexadecimal system. The first number is moved from its memory
location to the accumulator.It is compared with the 2nd number. The larger of the two numbers is then placed in
the accumulator.From the accumulator the larger number is moved to the desired memory location.

PROGRAM

Memory Machine code Labels Mnemonics Operands Comments

2000 21,01,25 LXI H,2501H Address of 1st no in HLpair

2003 7E MOV A,M 1st no in accumulator

2004 23 INX H Address of 2nd no in HLpair

2005 BE CMP M Compare 2nd no with 1st no Is the 2nd no >1st

2006 D2,0A,20 JNC AHEAD No,larger number is in Accumulator.Goto AHEAD

2009 7E MOV A,M Yes get 2nd number in the accumulator

200A 32,03,25 AHEAD:STA 2503H Store larger number in 2503H

200D 76 HLT STOP

DATA:

2501-98H

2502-87H

Result is 98H and it is stored in memory location 2503H

RESULT:

2503-98H

13. ALP to find the largest number in a data array

The no in a series are 98,75,99 as there are three nos in the series the count=03. The count is placed in the memory
location 2500H. The nos. are placed in the memory location 2501 to 2503H. The result is to be stored in the
memory location 2450H.The 1st no of the series is placed in the accumulator and it is compaied with the 2nd no
residing in the memory.The larger of two nos is placed in the accumulator .Again this no which is in the
accumulator is compared with the third no of the series and the larger no is placed in the accumulator.This process
of comparision is repeated till all the nos of the series are compared and the largest nomis stored in the desired
memory location.

PROGRAM:

Memory Machine Code Labels Mnemonics Operands Comments

2000 21,00,25 LXI H,2500H Address for count in HL pair

2003 4E MOV C,M Count in register C

2004 23 INX H Address of 1st no in HLpair

2005 7E MOV A,M 1st no in accumulator

2006 0D DCR C Decrement count

2007 23 LOOP INX H Address of next number

2008 BE CMP M Compare next number With pervious maximum.

Is next no>previous maximum?

2009 D2,0D,20 JNC AHEAD No,larger number is in Accumulator go

to the Lable AHEAD

200C 7E MOV A,M Yes, get larger in Accumulator

200D 0D AHEAD:DCR C Decrement count

200E C2,07,20 JNZ LOOP

2011 32,50,24 STA 2450H Store result in 2450H

2014 76 HLT Stop

EXAMPLE:

DATA:

2500-03

2501-98

2502-75

2503-99

RESULT:

2450-99

14. ALP to find the smaller of two numbers

Find the smaller of 84H and 99H.

The first no 84H is placed in the memory location 2501H.

The 2nd no 99H is placed in the memory location 2502H

Store the result in the memory location 2503H. The nos are represented in hexadecimal no system.The first no is
moved from its memory location to the accumulator.It is compared with the 2nd no.The smaller of the two is then
placed in the accumulator.From the accumulator the smaller no is moved to the desired memory location where it
is to be stored.

PROGRAM

Memory Machine code labels memonics operands comments

2000 21,01,25 LXI H,2501H Address of 1st no in HLpair

2003 7E MOV A,M 1st no in accumulator

2004 23 INX H Address of 2nd no in HLpair

2005 BE CMP M Compare 2nd no with 1st no Is the 2nd

no >1st

2006 D2,0A,20 JC AHEAD No,larger number is in Accumulator.

Goto AHEAD

2009 7E MOV A,M Yes get 2nd number in the accumulator

200A 32,03,25 AHEAD:STA 2503H Store larger number in 2503H

200D 76 HLT STOP

Example- 1

DATA: 2501-98H

2502-87H

Result is 87H and it is stored in memory location 2503H

15. ALP to find the smallest number in a data array

The number of a series are 8658 and 75.

As there are three numbers in the series,count=03

The count is placed in the memory location 2500H

The numbers are placed in the memory location 2501 to 2503H

The result is to be stored in the memory location 2450H

The 1st no of the series is placed in the accumulator and it is compared with the 2nd no residing in the memory.
The Smaller of two nos is placed in the accumulator .Again this no which is in the accumulator is compared with
the third no of the series and the Smaller no is placed in the accumulator.This process of comparision is repeated
till all the nos of the series are compared and the Smallest number is stored in the desired memory location.

PROGRAM:

Memory Machine Code Labels Mnemonics Operands Comments

2000 21,00,25 LXI H,2500H Address for count in HL pair

2003 4E MOV C,M Count in register C

2004 23 INX H Address of 1st no in HLpair

2005 7E MOV A,M 1ST no in accumulator

2006 0D DCR C Decrement count

2007 23 LOOP: INX H Address of next number

2008 BE CMP M Compare next number With pervious Is

next no>previous maximum?

2009 D2,0D,20 JC AHEAD No,larger number is in Accumulator go

to the Label AHEAD

200C 7E MOV A,M Yes, get larger in Accumulator

200D 0D AHEAD:DCR C Decrement count

200E C2,07,20 JNZ LOOP

2011 32,50,24 STA 2450H Store result in 2450H

2014 76 HLT Stop

EXAMPLE:

DATA:

2500-03H

2501-86H

2502-58H

2503-75H

RESULT:

2450-58H
TYPES OF MEMORY
The memory is used to store information used by the CPU. The information may be in the form of program, that
the CPU executes or data on which the CPU operates. Memory can be classified into two groups.

1. Primary Memory

2. Secondary Memory

Primary memory is constituted by memory blocks within the address space of the processor. They are
implemented by using read only memory (ROM) which are not volatile memories and read write memories or
random access memory (RAM) which are volatile memories. ROMs are used to store the permanent programs
and data while RAMs are used to store intermediate results and data. Secondary memories such as magnetic tapes,
floppy disk, hard disk etc. are used to store large amounts of data. The CPU cannot directly access secondary
units.

Primary Memory:

It is that part of the memory which can be directly access by the CPU. It can be viewed as a stack of words, each
word be associated with a unique address. These words may be instruction or data. A CPU having n address line
can access 2n memory location. The total primary memory area is partition into two separate sections called the
ROM area and the read/write area.

ROM:

On power on or a reset, the CPU always starts executing program from a fixed default address which is
usually the first address of the address space. These instructions are usually initialize the sequences which direct
the CPU to initialize all sub system in the systems. For example CPU may initialize the display driver display
outputs in a particular manner or initialize a key-board to accept the certain commands. This initialization
sequence which has to perform each time computer begins to its operation is part of the monitor software which
is stored in the permanent or non-volatile memory. The words permanent or non-volatile implies that the program
is not lost when the power is switched off and that it is available each time the power is switched on. It is
implemented by using a special kind of memory called read only memory or ROM. The data in this selection
cannot be written over and can only the read. The ROM is used to store information that should not change. ROMs
are available into 4 types. There are

i. Masked ROM
ii. PROM
iii. EPROM
iv. EEPROM

i. Masked ROM:

The instructions in such ROMs are permanently installed by the manufacturer as for the specification provided by
the system programmer and cannot be altered. This ROM contains call arrays in which 1s and 0s which are stored
by means of a metallization interconnect mostly at the time of fabrication.

ii. PROM (Programmable Read Only Memory)

The manufacturer provides a memory device which can be programmed by the user by using a PROM program.
The PROM uses a fusible links that can be burnt or melted by special PROM burning circuit. A fused link is
corresponds to zero.

iii. EPROM (Erasable PROM)

It uses most charge storage technology. It is also programmable by the user. The information stored in the EPROM
can be erased by exposing the memory to ultraviolet light which erase the data stored the data in total memory
area. Then the memory can be reprogrammable by the user by using EPROM burning circuit.
iv. EEPROM (Electrically Erasable PROM)

This is similar to EPROM except that the erasing done by electrical signal instead of ultraviolet light and that the
data in memory location can be selective erased.

RAM
It is a special kind of memory area where information can be written into or read from whenever necessary. The
CPU uses this section memory as a scratch pad memory. It is also called read/write memory or RAM. The CPU
can access any memory location by specifying its address. Unlike ROM the conventional is a volatile memory i.e.
the contents of the RAM are used when the power is switched off. RAMs are two types.

i. Static RAM

In the case of static RAM once the data is written into a memory location, the data remain unchanged unless on
same memory location is written into again. It uses flip-flops for storage elements.

ii. Dynamic RAM

In case of dynamic RAM the basic storage elements is a capacitor. This element contains a 1or a 0 depending on
the presence or absence of charge. Unlike static RAM, the contents of the dynamic RAM may change with time
due to leakage of charge. So it is necessary to periodically refresh the storage element in a dynamic RAM. Here
it has external refresh circuitry. The advantages of dynamic RAM over static RAM are it consumes less power
than static RAM and it has about 5 times more storage element per unit area. Disadvantages are that DRAMS
have slower access times and need special circuitry to periodically refresh memory.

2. Secondary Memory

The maximum capacity of primary memory 2n location. Each of 2n location where n is the number of CPU address
lines. Sometimes it is necessary to handle more data than allowed by the primary memory. In such cases secondary
memory is used. The CPU cannot directly access memory but can access through I/O ports. Examples are magnetic
tapes, hard disk, and floppy disk.

INTERRUPTS AND INTERRUPT SERVICE SUBROUTINE

HARDWARE INTERRUPTS AND SOFTWARE INTERRUPTS

Interrupts caused by I/O devices to transfer data to or from the microprocessor are called Hardware Interrupts.

Example- TRAP, RST 7.5, RST 6.5, RST 5.5

When an interrupt is recognized the next instruction is executed from a fixed location in memory as given below

Interrupt Location of ISS

TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C

The normal operation of the microprocessor can also be interrupted by abnormal internal conditions on special
instruction. Such interrupts are called Software Interrupts.

Example-RST 0 to RST 7 instructions of 8085.

They are used in debugging of a program.

INSTRUCTION OPCODE ISS ADDRESS

RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030

The internal abnormal or unusual conditions which prevent the normal processing sequence of a microprocessor
are called Exception.

Example-Divide by zero is an exception.

VECTOR INTERRUPTS AND NON VECTOR INTERRUPTS

In TRAP, RST 7.5, RST 6.5, RST 5.5 interrupts, the program is automatically transferred to the ISS address
without any external hardware .These interrupts for which hardware automatically transfers the program to a
specific memory location is known as Vector Interrupt.

When several I/O devices are connected to INTR interrupts line an external hardware is used to interface I/O
devices. This circuit generates RST-n codes to implement the multiple interrupts schemes. These are not vector
interrupts.

RST 7.5, RST 6.5, RST 5.5

RST 7.5, RST 6.5, RST 5.5 are maskable interrupts. They are enable by software using instruction EI and SIM.
SIM instruction enables or disable according to the bit of accumulator.
ADDRESS SPACE PARTITIONING
Intel 8085 uses a 16-bit wide address bus or addressing memory and I/O devices. It can access 216=64k bytes of
memory and I/O devices. There are two schemes for the allocation of address to memories or I/O devices.

1. Memory mapped I/O scheme

2. I/O mapped I/O scheme

1. Memory Mapped I/O Scheme

In this scheme there is only one address space. Address space is defined as set of all possible addresses that a
microprocessor can generate. Some address are assigned to memories and some address to I/O devices. Suppose
memory locations are assigned the address 2000-2500. One address is assigned to each memory location. These
addresses cannot be assigned to I/O devices. The addresses assigned to I/O devices are different from address
assigned to memory. For example, 2500, 2501, 2502 etc. may be assigned to I/O devices. One address is assigned
to each I/O device.

In this scheme all the data transfer instruction of the microprocessor can be used for both memory as well
as I/O devices. For example, MOV A, M will be valid for data transfer from the memory location or I/O device
whose address is in H-L pair. This scheme is suitable for small system.

2. I/O Mapped I/O Scheme

In this scheme the address are assigned to memory locations can also be assigned to I/O devices. To distinguish
whether the address on an address bus is for memory location or I/O devices. The Intel 8085 issues IO/M(bar)
signal for this purpose. When the signal is high the address of an address bus is for I/O device. When low, the
address is for a memory location. Two extra instructions IN and OUT are used to address I/O device. The IN
instruction is used to read data from an input device. And OUT instruction is used to an output device. This scheme
is suitable for large system.

Memory Interfacing

An address decoding circuit is employed to select the required I/O device or a memory chip. When IO/M(bar) is
high, decoder2 is activated and the required IO device is selected. If IO/M(bar) is low, the decoder1 is activated
the required memory chip is selected. A few msb of address line is applied to the decoder to select the memory
chip or an I/O device.
MEMORY INTERFACING & ADDRESS DECODING

This is done by using 74LS138 which is a 3:8 decoder.

The address of the memory location is sent out by the microprocessor. The corresponding memory chip is selected
by a decoding circuit. G1, G2A, G2B are enable signals of the decoder. To enable 74LS138 decoder, G1 should
be high and G2A, G2B should be low. A, B, C are the select lines of the decoder. Y output lines.

By applying proper logic to select lines, any one of the outputs can be selected. The selected output line goes low
while other output lines remain high.

The entire memory address = 64 KB for 8085 has been divided into 8 zones. The address lines A13 A14 A15 have
been applied to A, B, C select lines. The logic applied to C selects a particular memory device i.e. an EPROM or
RAM. The address lines A the address of the memory location within a selected memory chip. IO/M(bar) is
connected to G2B, G1 is connected to +5volt dc supply and G2A
Addresses of 8 zones:

Total memory = 0000 to FFFF = 64 KB

Memory of each zone = 64/8 KB = 8KB

DMA CONTROLLER (Intel 8257/ 8237):

· Intel 8257 is a four channel DMA controller used to facilitate the direct memory access or DMA mode of data
transfer.

· In this mode the devices transfers data directly to or from memory with any interference on the CPU.

· For facilitating DMA data transfer between several devices a DMA controller is used.

INTERNAL ARCHITEHCHTURE OF 8257:

· The chip supports four DMA channel i.e four peripheral devices can independently request for DMA data
transfer through these channel at a time.

· The DMA controller has 8-bit internal data buffer, a read/write a control unit ,a priority reserving unit along
with a set of register.

REGISTER ORGANISATION OF 8257:

· Each of the four channels of 8257 has a pair of two 16-bit registers. i.e DMA register and terminal count
register.

· There are two common register for all the channel.

(a) Mode set register

(b) Status register

DMA address register:

· Each DMA channel has DMA address register. Its function is to store the address of the starting memory
location which will be access by the DMA channel.

Terminal count register:

· This 16-bit register is used to make sure that the data transfer through a DMA channel stops after the required
number of DMA cycles.

· The load of 14-bit terminal count register are initialize with the binary equivalent of the number of DMA cycle
minus one.

· After each DMA cycle the terminal count register contained will be decremented by 1 and finally it becomes 0
after the required number of DMA cycle.
· The bits 14 and 15 of this register indicate the type of the DMA operations

· There are three type of DMA cycle.

(a) Read DMA cycle

(b) Write DMA cycle

(c) Verify DMA cycle

Bit no. 15 Bit no. 14 Types of DMA

operation
0 0 Verify DMA cycle

0 1 Write DMA cycle

1 0 Read DMA cycle

1 1 Illegal

MODE SET REGISTER:

The function of this register is to enable the DMA channel individually and also to set the various modes of
operation

· The bits D0 –D3 enable one of the four DMA channel of 8257. For example: If D0 is 1,channel0 is enable. If
D4 is set rotating priority is enable otherwise fixed priority is enable.

· If Bit D6 (TC) is set the selected channel is disable after terminal count register is least and it prevents any
further DMA cycle on the channel.

· The auto laod bit that is D7 if set enable channel for the repeat block chaining operations.

· After the first block is transfer using DMA the channel 2 register are reloaded with corresponding channel 3
register for the next block transfer if the update flag is set.

· Extended write bit D5 is set to 1extends the duration of memory write (MEMW) and I/O write signals IOW.

STATUS REGISTER:

· Bits D0-D3 contain the terminal count status for the four individual channels.

· If any of these is set it indicates that the specific channel is reached the terminal count register.

· Bit D4 represents the update flag if it is set the contents of channel 3 register are reloaded with corresponding
channel 2 registers without any software intervention.
SIGNAL DESCRIPTION OF 8257

DRQ0-DRQ3:

· These are the 4 individual channels DMA request inputs used by the peripheral devices for requesting DMA
services.

· The DRQ0 has the highest priority, while DRQ3 has the lowest,if fixed priority mode is selected.

DACK0bar - DACK3bar:

· These are the active low DMA acknowledgement output lines which inform the requesting peripheral that the
DMA request has been honoured.

D0-D7:

· These are bidirectional data lines used to interface the system bus with the internal data bus of 8257.

IORbar:

· In Master mode, this signal is used to read data from a peripheral during a memory write cycle.

· In slave mode, this input signal is used by the CPU to read internal registers of 8257.
IOWbar :

· In Master mode, it is a control output that is used to write data to a peripheral during DMA memory read cycle

· In slave mode, it is used to load the contents of the data bus to the 8 bit mode register.

CLK:

· This is a clock frequency input required to generate system timing for internal operations of 8257.

RESET:

· This input disables all the DMA channels by clearing the mode registers & translate all the control lines.

A0-A7:

· These are address lines.

CS:

· It is an active low chip select line that enables R/W operations from or to 8257 in slave mode.

· In master mode it is disabled.

READY:

· This input is used to stretch memory read & write cycles of 8257 by inserting wait states.

HRQ:

· Hold Request output requests access of system bus of 8085 CPU.

HLDA:

· This input if high indicates to the DMA controller that the system bus has been generated to the requested
peripheral to the CPU.

MEMRbar:

· This active low memory read output is used to read data from the addressed memory location during DMA
read cycle.

MEMWbar:

· This active low memory write output is used to write data to the addressed memory location during DMA
write operation.

ADSTB (Address strobe):

· This output from 8257 strobe the higher byte of the memory address generated by the DMA controller into the
latches.

AEN (Address Enable) :

· This output is used to disable the system address & data to stop the non DMA devices from responding during
DMA operations.

TC (Terminal Count):

· This output indicates to the currently selected peripheral that the present DMA cycle is the last for the
previously programmed data bus.

MARK:
· The modulo 128 mark output indicates the selected peripheral that the current DMA cycle is the 128th cycle
since the previous marked output.

INTERFACING DMA CONTROLLER:

The DMA controller interfacing circuit implements a switching arrangement for the address, data & control
buses of the memory & peripheral sub-system from or to the CPU to or from the DMA controller.

1. The peripheral device that wants to do a DMA data transfer sends a request to DMA controller on DRQ line.

2. The DMA controller then sends a HOLD request to CPU on HRQ line to get control of system bus.

3. The CPU completes the current machine cycle, it releases the system bus to the DMA controller and sends a
high HLDA signal.

4. The controller then sends a DMA acknowledgement DACKbar to the requesting peripheral. Now it is ready
for DMA data transfer.

5. During DMA data transfer CPU remains in HOLD state.

PPI-Programmable Peripheral Interface (8255):

A PPI is a multiport device. The port may be programmed in a verity of ways as required by the programmer.
The device is very useful for interfacing peripheral devices.

It has three, 8-bit port.

1. Port A
2. Port B
3. Port C

Port C is further subdivided into two, 4-bit ports.

Port C upper Port C lower

Each port can be programmed either as an input port or as an output port, by setting proper bits in the control
word. This control word is written into a control word register (CWR).

CONTROL GROUPS OF 8255:

The 24 lines of I/O port is divided into 2 groups namely Group A and Group B.

Each group contains one 8-bit port & a 4-bit port.

Group A Group B

Port A Port B

Port C upper Port C lower

The control word initialises the ports.

ARCHITECTURE OF INTEL 8255A:

It is a 40 pin IC package.

It operates on a single +5V dc supply.

The pins for various ports are:-

PA0 – PA7 8 pins of Port A

PB0 – PB7 8 pins of Port B

PC0 – PC3 4 pins of Port C lower

PC4 – PC7 4 pins of Port C upper

The important control signals are:

D0 – D7 These are 8-bit bidirectional data lines.

CS (Chip Select) It is a chip select signal. The low status of this signal enable communication between CPU &
8255.

RDbar (Read) It allows the CPU to read data from the input port of 8255.

WRbar (Write) when WRbar goes low, the CPU writes data or control word into 8255.

A0 and A1 the selection of ports and control word register is done using A0 and A1 in conjunction with
RD and WR. A0 and A1 are connected to the LSBs of the address bus. If two 8255 units are
used, the address of ports are as follows

1st 8255 2nd 8255

Port/control word Port/control word Port/control word Port/control word
register address register address
Port A 00 Port A 08
Port B 01 Port B 09
Port C 02 Port C 0A
Control word register 03 Control word register 0B

If the instruction is IN 00, it is the port A of 8255.1.

If the instruction is OUT 0B, the accumulator content will be transferred to control word register of 8255.2.
Mode of operation of 8255:

The Intel 8255 has three modes of operation as follows:

Mode 0 – Simple input / output

Mode 1 – Strobed input / output

Mode 2 – Bidirectional input / output

Mode 0:

It is also known as basic Input / Output mode. This mode provide simple Input / Output capability using each of
the three ports.

Features of Mode 0:--

 Two, 8-bit ports i.e. port A and port B & two, 4-bit ports i.e. port C upper and port C lower are
available. The two 4-bit ports of port C can be combined and used as a 3rd 8- bit port.
 Any port can be used as an input or output port. Output ports are latched. But, input ports are not
latched.

Mode 1:

This mode is also called strobed I/O mode. In this mode port C is used for generating handshake. Signals to
control the input or output action of port A or port B.

Features of Mode 1:

 Two groups i.e. group A and group B are avaliable for strobe data transfer. Each groups contains one 8-
bit data I/O port, one 4-bit control port.
 The 8-bit data port can be either used as input or output port.
 Both the inputs and outputs are latched. Out of 8-bit port C i.e. PC0 to PC2 are used to generate control
signals for port B and PC3 to PC5 are used to generate control signals for port A. The line PC6 and
PC7 may be used as independent data lines.

Mode 2:

It is known as strobe bidirectional I/O mode. Only port A is available. In this mode 8255 acts as a bidirectional
8-bit port with handshakes signal.

Features of mode 2:

 Only port A is available.

 The 8-bit port A is bidirectional and additionally a 5-bit control port C is available.
 Input and outputs are both latched.
 Three I/O lines are available at port C i.e. PC0 to PC2.
 The 5-bit control port C i.e. PC3 to PC7 is used for generating handshake signals for 8-bit data transfer
on port A.
Control Word format in I/O mode:

For programming the ports of 8255 a control word is formed. The CPU outputs the control word to 8255 which
is written into the control word register in 8255.No read operation of control word register is allowed.

PROGRAMABLE INTERRUPT CONTROLLER (PIC) 8259A

A PIC takes care of a number of simultaneously appearing interrupt requests along with their types and priorities
in a multiple interrupt system.

ARCHITECTURE OF 8259A

 INTERRUPT REQUEST REGISTER (IRR): IRR stores all the interrupt request in it in order to solve
them one by one on priority basis.
 IN – SERVICE REGISTER (ISR): It stores all the interrupt request that are being served.
 PRIORITY RESOLVER: This unit determines the priorities of the interrupt request appearing
simultaneously. (In fixed priority mode IR0 has the highest priority while IR7 has the lowest).
 INTERRUPT MASK REGISTER (IMR): The register stores the bits required to mask the interrupt
inputs.
 INTERRUPT CONTROL LOGIC: This block manages the interrupt and interrupt acknowledge signal
to be send to the CPU for serving one of the 8 interrupt request.
 DATA BUS BUFFER: This bidirectional buffer interface internal 8259A bus to the microprocessor
system data bus.
 R/W CONTROL LOGIC: This circuit accepts and decodes command from the CPU.
 CASCADE BUFFER /COMPARATION: This blocks stores and compare to IDs of all the 8259A use
in the system.
 PIN- DESCRIPTION :

It is a 28 pin IC package.

 CS :- It is an active low chip selected signal for enabling read and write operation of 8259A.
 WRbar :- This pin is an active low write enable input to 8259A.
 RDbar :- It is an active low read enable input to 8259A.
 D0-D7 :-They form a bidirectional data bus that carry 8-bit data and interrupt vector information.
 CAS0-CAS2 (CASCADE LINE) :- A single 8259A provides 8 vectored interrupts. If more
interrupt are required, the 8259A is used in the cascade mode in which a master 8259A along with
8 slave 8259A can provide up to 64 vectored interrupt lines. These cascade lines attached select
line for addressing the slave 8259A.
 SP/EN :- (SLAVE PROGRAM / ENABLE LIGIC) This pin is dual purpose pin. When the chip is
used in buffered mode, it can be used as a buffer enable to control buffer trans-receiver. In buffer
mode EN = 0. If not in buffer mode then the pin is used as input to designate whether the chip is
used as a master. ( SP = 1) or a slave ( EN = 0).
 INT :- This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the
CPU.
 IR0 – IR7 (INTERRUPT REQUEST): This pin act as a inputs to accept interrupt request to the
CPU.
 INTA :- (INTERRUPT ACKNOWLEDGE) The pin is an input used to strobe in 8259A interrupt
vectored data on to the data bus. The device 8259A can be interfaced with any CPU using either
device polling or interrupt schemes.

DEVICE POLLING

 Here the CPU keeps on checking each peripheral device in sequence to make sure if it requires
any service from the CPU.
 If any such service request is noticed, the CPU serves the request and then goes on to next device
in sequence.
 After all the peripheral devices are scanned, the CPU again starts from the 1st device.
 This results in reduction of processing speed because most of the CPU time is consumed in
polling the peripheral devices.

PROGRAMMABLE TIMER (8253):

It is used in real time application for timing and counting function such as BCD/binary counting, generation of
accurate time delay, generation of square wave of desired frequency etc. Intel 8253 is one of such IC, it has the
following six modes-

Mode 0: Interrupt on terminal count

Mode 1: Programmable one-shot

Mode 2: Rate generator

Mode 3: Square wave generator

Mode 4: Software triggered mode

Mode 5: Hardware triggered mode

RDbar CPU reads when it is low

WRbar CPU writes when it is low

A0, A1 These are connected to the address bus to select one of the three counters. It is also used to address
the control word registers for mode selection.

CSbar chip select

D0-D7 Bidirectional data bus

Control word register:

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

SC (select counter):

SC1 SC0

0 0 Select counter 0

0 1 Select counter 1

1 0 Select counter 2

1 1 illegal

RL (Read/Load):

RL1 RL0

0 0 Counter latching operation

0 1 Read/Load least significant byte only

1 0 Real/Load most significant byte only

1 1 Read/Load least significant byte first, then

most significant byte

BCD

0 binary counter 16-bits

1 binary coded decimal (BCD) counter

M2, M1, M0: mode select (six modes)

ARCHITECTURE OF 8086 MICROPROCESSOR

Pin diagram:
Architecture block diagram:

Registers of Intel 8086

The Intel 8086 contains the following register.

(i) General purpose Registers

(ii) Pointer and Index Registers

(iii) Segment Registers

(iv) Instruction Pointer

(v) Status Flags

General purpose Registers

There are four 16-bit general purpose register: AX, BX, CX and DX. Each of these 16-bit registers are further
subdivided in to two 8-bit register as shown below.

Register AX serves as an accumulator. Register BX, CX and DX are used as general purpose register in addition
to serving as general purpose register they also serve as special purpose register as a special purpose register BX
serves as a base register for computation of memory address .in 8086 memory addresses are to be calculated
using the contents of the segment register and effective memory address. These will be explained later on
Register CX is also used as a counter in case of multi-iteration instruction. When the content of CX becomes
zero such instruction terminate the execution. DX register is also used for memory addressing when data are
transferred between I/O port and memory using certain I/O instruction.

REGISTER ORGANIZATION

Pointer and Index Register.

The following four figures are in the group of pointer and index register.

1. Stack Pointer, SP

2. Base pointer, BP

3. Source index, SI

4. Destination Index, DI

The function of SP is same as the function of stack pointer in Intel 8085. BP, SI and DI are used in memory
address computation.

Segment Register: There four segment registers in 8086.

1. Code Segment Register, CS

2. Data Segment Register, DS

3. Stack Segment Register, SS

4. Extra Segment Register, ES

In an 8086 microprocessor-based system memory is divided in to the following four segments:

1 .Code Segment

2. Data Segment

3. Stack Segment

4. Extra Segment
The code segment of the memory holds instruction code of a program. The data variables and constant given in
the program are held in the data segment of the memory. Stack segment holds address and data of subroutines. It
also holds the contents of register and memory location given in PUSH instructions. Before attending an
interrupt the microprocessor saves the contents of program counter on the stack. Also when CALL instruction is
executed, before the execution of the subroutine the address of the next instruction of the program is saved on
the stack. The extra segment holds the destination address of some data of certain string instruction, and so on.

A segment register point to the starting address of a memory segment currently being used. For
example the code segment registers points to the starting address of the data segment, and so on. The maximum
capacity of a segment may be up to 64k byte. The starting address of a segment is divisible by 16. The segment
shown in the figure is currently used segment. There more number of such segment to make the total memory
capacity 1Mbyte. The 8086 instruction specify 16-bit memory address. The actual addresses are of 20 bits. They
are calculated using the contents of the segment register and effective memory address. The effective memory
address is computed in a variety of ways. It depends on the such as PUSH,POP,CALL or RET , The content of
the stack pointer(SP) and the content of the stack segment register(SS) are used to complete the stack of the
location to be accessed. The index register SI and DI together with segment register DS and ES are used to
perform string operations. The source addresses for string operation are computed using the content of SI and
DS. The destination addresses for string operations are computed using the contents of DI and ES.

Instruction pointer (IP):

The instruction pointer in the 8086 microprocessor act as a program counter. It point to the address of the next
instruction to be executed. Its content is automatically incremented when the execution of a program proceeds
further. The content of the instruction pointer (IP) and the content of the code segment register (CS) are used to
compute the memory address of the instruction code to be fetched. This is done during instruction fetch
operation.

Status Register:

The 8086 contains a 16-bit status register. It also called flag register or program status word (PSW). There are 9
status flags that are: over flow flag, Direction flags, Input enable flag, Trap flag, Carry flag, parity flag,
Auxiliary carry flag, zero flag, sign flag. Out of nine flag 6 are condition flag and three are control flags. These
six condition flag are carry, auxiliary carry, zero, sign and parity and overflow flag. The flag are set/reset by the
processor after the execution of an arithmetic and logic operation. The three control flag are trap (or trace)
interrupt and directional flag. These flags are set/reset by the programmer as the required by certain instruction
in the program. The overflow, trap, interrupt and directional flags are new. Other flags are same as those
available in Intel 8085. The overflow flag is set to 1 if the result of a signed operation become out of range other
it is reset it is made 0.
Status register:

When the trap flag (TF) is set to 1 a program can be run in single-step mode. The interrupt flag (IF) is set to 1 to
enable INTR of 8086. If it is 0, INTR is disabled. It is set by STI instruction and declared by CLI instruction, IF
is automatically cleared when an interrupt is recognised. It disabled ITNTR. IRET used at the end of interrupt
service sub routine (ISS) restore IF flag in the state that was before interrupt occurred.

The directional flag DF is used in string operation .It can be set by STD instruction and cleared by
CLD instruction. If it is set to 1, string bytes are accessed from higher memory address to lower memory
address. When it is set to 0 the string bytes are accessed from lower memory address to higher memory address.
For MOVES instruction, if DF is set to 1, the content of index register SI and DI are automatically decremented
by the processor to access the string from the highest memory address down to the lowest memory address. If
DF is made zero, SI and DI are automatically incremented to access the string starting with the lowest address.

Addressing Modes of Intel 8086

The way by which an operand is specify for instruction is called addressing mode. Intel

8086 has 8 addressing mode.

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing

7. Based Indexed Addressing

8. Based Indexed with Displacement Addressing

1. REGISTER ADDRESSING

· Here the operand is placed in one of the 16-bit or 8-bit general purpose registers.

· Example- MOV AX, CX (move 16-bit data in base register to accumulator)

2. IMMEDIATE ADDRESSING

· Here the operand is specified in the instruction itself.

· Example-MOV AL, 35H (move immediate data 35H to 8-bit register A)

MOV BX, 0305H (move 16-bit data 0305 to register base).

The remaining 6 addressing mode specify the location of an operand which is placed in memory.

When an operand is stored in memory location, how far the operand’s memory location is within a memory
segment from the starting address of the segment, is called offset or effective address (EA).,An offset is
determined by adding any combination of three address elements: displacement, base and index.

Displacement: It is an 8-bit or 16-bit immediate value given in the instruction.

Base: It is the content of the base register, BX or BP.

Index: It is the content of the index register, SI or DI.

The Combination of these three address elements give six memory addressing modes as described below.

3. DIRECTADDRESSING

In this mode the operand’s offset is given in the instruction as an 8-bit or 16-bit displacement element.

· Example:- 1.ADD AL,[0301]

The contents of memory 0301 is added to the content of AL, and the result is placed in AL .

· 2. ADD [0301],AX

This instruction adds the content of AX to the content of memory location 0301 and 0302.

4. REGISTER INDIRECT ADDRESSING

The operand’s offset is placed in any one of the registers BX,BP,SI or DI as specified in the instruction.

Example: MOV AX,[BX]

· This instruction moves the content of memory location addressed by the register BX to the register AX.

· For examples, BX contains 0301, and the content of 0301 is 53H and the content of next memory location is
95H.The 9553 will move to AX.

5. BASED ADDRESSING

The operand’s offset is the sum of an 8-bit or 16-bit displacement and the content of the base register BX or BP.
BX is used as a base register for data segment, and BP is used as a base register for stack segment.

Offset = [BX +8-bit or 16-bit displacement]

· Examples are:-

MOV AL, [BX+05]; an example of an 8-bit displacement.

Let us consider the register BX has 0301.The offset will be 0301+05=0306. The content of the memory location
0306 will move to AL.

MOV AL, [BX+1346H]; an example of 16-bit displacement.

If [BX] =0301.The offset =0301+1346=1647H. The content of 1647H will move to AL.
6. INDEXED ADDRESSING

The operand’s offset is the sum of the content of an index register SI or DI and an 8-bit or 16 bit displacement.
Offset= [SI or DI+8-bit or 16-bit displacement]

· Examples are:

MOV AX, [SI+05]; an example of 8-bit displacement.

MOV AX, [SI+1528H]; an example of 16-bit displacement.

7. BASED INDEXED ADDRESSING

The operand’s offset is the sum of the content of a base register BX or BP and an index register SI or DI.BX is
used as a base register for data segment, and BP is used as a base register for stack segment.

Offset= [BX or BP] + [SI or DI]

· Examples are:

ADD AX, [BX+SI]

MOV CX, [BX+SI]

8. BASED INDEXED WITH DISPLACEMENT

In this mode of addressing the operand’s offset given by

Offset= [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement

· Examples are:

MOV AX, [BX+SI+05]; an example of 8-bit displacement

MOV AX, [BX+SI+1235H]; an example of 16-bit displacement.