PIC12F529T39A: 14-Pin, 8-Bit Flash Microcontroller

PIC12F529T39A
14-Pin, 8-Bit Flash Microcontroller

High-Performance RISC CPU Low-Power Features/CMOS Technology
• Only 34 Single-Word Instructions • Standby Current:
• All Single-Cycle Instructions except for Program - 225 nA @ 2.0V, RF Sleep, typical
Branches which are Two-Cycle • Operating Current:
• Four-Level Deep Hardware Stack - 175 µA @ 4 MHz, 2.0V, RF Sleep, typical
• Direct, Indirect and Relative Addressing modes - 9.17 mA @ 4 MHz, 2.0V, RF on at +0 dBm,
for Data and Instructions typical
• Operating Speed: - 15.17 mA @ 4 MHz, 2.0V, RF on at +10 dBm,
- DC – 8 MHz internal clock typical
- DC – 500 ns instruction cycle • Watchdog Timer Current:
- 1 µA @ 2.0V, typical
Special Microcontroller Features • High Endurance Program and Flash Data
Memory cells:
• 8 MHz Precision Internal Oscillator: - 100,000 write program memory endurance
- Factory-calibrated to ±1% - 1,000,000 write Flash data memory
• In-Circuit Serial Programming™ (ICSP™) endurance
• Power-on Reset (POR) - Program and Flash data retention: >40 years
• Device Reset Timer (DRT) • Fully Static Design
• Watchdog Timer (WDT) with Dedicated On-Chip • Operating Voltage Range: 2.0V to 3.7V
RC Oscillator for Reliable Operation • Industrial temperature range: -40°C to +85°C
• Programmable Code Protection
• Multiplexed MCLR Input Pin RF Transmitter
• Internal Weak Pull-ups on I/O Pins
• Power-Saving Sleep mode • Fully-Integrated Transmitter
• Wake-up from Sleep on Pin Change • FSK Operation up to 100 kbps
• Selectable Oscillator Options: • OOK Operation up to 10 kbps
- INTRC: 4 MHz or 8 MHz precision internal • Frequency-Agile Operation in 310, 433, 868 and
RC oscillator 915 MHz bands
- EXTRC: External low-cost RC oscillator • Configurable Output Power: +10 dBm, 0 dBm
- XT: Standard crystal/resonator
- LP: Power-saving, low-frequency crystal Peripheral Features
• Six I/O Pins:
- Five I/O pins with individual direction control
- One input-only pin
- High-current sink/source for direct LED drive
• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
 2012-2015 Microchip Technology Inc. DS40001635B-page 1

PIC12F529T39A
FIGURE 1: 14-PIN TSSOP
VDD 1 14 Vss
GP5/OSC1/CLKIN 2 13 GP0/ICSPDAT
PIC12F529T39A
GP4/OSC2 3 12 GP1/ICSPCLK
GP3/MCLR/VPP 4 11 GP2/T0CKI
VDDRF 5 10 XTAL
CTRL 6 9 DATA
RFOUT 7 8 VSSRF
PIC12F529T39A Family Types

Program
Data Memory
Memory Timers 8-Bit A/D
Device I/O RF Transmitter Comparators
Flash SRAM Flash (8-bit) Channels
(words) (bytes) (bytes)
PIC12F529T39A 1536 201 64 6 1 0 1 0
PIC12LF1840T39A
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001636 PIC12LF1840T39A Data Sheet, 8-Bit Flash Microcontroller with XLP
DS40001635B-page 2  2012-2015 Microchip Technology Inc.

PIC12F529T39A
Table of Contents
1.0 General Description .................................................................................................................................................................. 7
2.0 PIC12F529T39A Device Varieties ........................................................................................................................................... 9
3.0 Architectural Overview ............................................................................................................................................................ 11
4.0 Memory Organization ............................................................................................................................................................. 15
5.0 Flash Data Memory ................................................................................................................................................................ 23
6.0 I/O Port ................................................................................................................................................................................... 25
7.0 Timer0 Module and TMR0 Register ........................................................................................................................................ 33
8.0 Special Features Of The CPU ................................................................................................................................................ 39
9.0 RF Transmitter ........................................................................................................................................................................ 51
10.0 Instruction Set Summary ........................................................................................................................................................ 63
11.0 Development Support ............................................................................................................................................................. 71
12.0 Electrical Characteristics ........................................................................................................................................................ 75
13.0 DC and AC Characteristics Graphs and Charts ..................................................................................................................... 87
14.0 Packaging Information ............................................................................................................................................................ 95
The Microchip Web Site .................................................................................................................................................................... 103
Customer Change Notification Service ............................................................................................................................................. 103
Customer Support ............................................................................................................................................................................. 103
Reader Response ............................................................................................................................................................................. 104
Product Identification System ........................................................................................................................................................... 105
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PIC12F529T39A
1.0 GENERAL DESCRIPTION The PIC12F529T39A device is available in the cost-
effective Flash programmable version, which is
The PIC12F529T39A device from Microchip suitable for production in any volume. The customer
Technology is a low-cost, high-performance, 8-bit, can take full advantage of Microchip’s price leadership
fully-static, Flash-based CMOS microcontroller. It in Flash programmable microcontrollers, while
employs a RISC architecture with only 34 single-word/ benefiting from the Flash programmable flexibility.
single-cycle instructions. All instructions are single
The PIC12F529T39A product is supported by a full-
cycle except for program branches, which take two
featured macro assembler, a software simulator, a low-
cycles. The PIC12F529T39A device delivers
cost development programmer and a full-featured
performance an order of magnitude higher than its
programmer. All the tools are supported on PC and
competitors in the same price category. The 12-bit wide
compatible machines.
instructions are highly symmetrical, resulting in a
typical 2:1 code compression over other 8-bit
microcontrollers in its class. The easy-to-use and easy 1.1 Applications
to remember instruction set reduces development time The PIC12F529T39A device fits in applications ranging
significantly. from personal care appliances and security systems to
The PIC12F529T39A product is equipped with special low-power remote transmitters/receivers. The Flash
features that reduce system cost and power technology makes customizing application programs
requirements. The Power-on Reset (POR) and Device (transmitter codes, appliance settings, receiver
Reset Timer (DRT) eliminate the need for external frequencies, etc.) extremely fast and convenient. The
Reset circuitry. There are four oscillator configurations small footprint packages, for through hole or surface
to choose from including INTRC Internal Oscillator mounting, make these microcontrollers perfect for
mode and the power-saving LP (Low-power) Oscillator applications with space limitations. Low cost, low
mode. Power-Saving Sleep mode, Watchdog Timer power, high performance, ease of use and I/O flexibility
and code protection features improve system cost, make the PIC12F529T39A device very versatile even
power and reliability. in areas where no microcontroller use has been
considered before (e.g., timer functions, logic and
PLDs in larger systems and co-processor
applications).
TABLE 1-1: FEATURES AND MEMORY OF PIC12F529T39A

PIC12F529T39A
Clock Maximum Frequency of Operation (MHz) 8
Memory Flash Program Memory 1536
SRAM Data Memory (bytes) 201
Flash Data Memory (bytes) 64
Peripherals Timer Module(s) TMR0
Wake-up from Sleep on Pin Change Yes
Features I/O Pins 5
Input Pins 1
Internal Pull-ups Yes
In-Circuit Serial Programming™ Yes
Number of Instructions 34
RF Transmitter Frequency Range 310 MHz, 433 MHz, 868 MHz and 915 MHz Bands
Packages 14-pin TSSOP

PIC12F529T39A
2.0 PIC12F529T39A DEVICE 2.2 Serialized Quick-Turn
VARIETIES ProgrammingSM (SQTPSM) Devices
When placing orders, please use the PIC12F529T39A Microchip offers a unique programming service, where a
Product Identification System at the back of this data few user-defined locations in each device are
sheet to specify the correct part number. Depending on programmed with different serial numbers. The serial
application and production requirements, the proper numbers may be random, pseudo-random or
device option can be selected using the information in sequential.
this section. Serial programming allows each device to have a
unique number, which can serve as an entry code,
2.1 Quick-Turn Programming (QTP) password or ID number.
Devices
Microchip offers a QTP programming service for factory
production orders. This service is made available for
users who choose not to program medium-to-high
quantity units and whose code patterns have stabilized.
The devices are identical to the Flash devices but with
all Flash locations and fuse options already
programmed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available. Please contact your local
Microchip Technology sales office for more details.

PIC12F529T39A
3.0 ARCHITECTURAL OVERVIEW The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
The high performance of the PIC12F529T39A device otherwise mentioned, arithmetic operations are two’s
can be attributed to a number of architectural features complement in nature. In two-operand instructions, one
commonly found in RISC microprocessors. To begin operand is typically the W (working) register. The other
with, the PIC12F529T39A device uses a Harvard operand is either a file register or an immediate
architecture in which program and data are accessed constant. In single-operand instructions, the operand is
on separate buses. This improves bandwidth over tra- either the W register or a file register.
ditional von Neumann architectures where program
The W register is an 8-bit working register used for ALU
and data are fetched on the same bus. Separating
operations. It is not an addressable register.
program and data memory further allows instructions
to be sized differently than the 8-bit wide data word. Depending on the instruction executed, the ALU may
Instruction opcodes are 12 bits wide, making it possi- affect the values of the Carry (C), Digit Carry (DC) and
ble to have all single-word instructions. A 12-bit wide Zero (Z) bits in the STATUS register. The C and DC bits
program memory access bus fetches a 12-bit instruc- operate as a borrow and digit borrow out bit,
tion in a single cycle. A two-stage pipeline overlaps respectively, in subtraction. See the SUBWF and ADDWF
fetch and execution of instructions. Consequently, all instructions for examples.
instructions (34) execute in a single cycle (500 ns @ A simplified block diagram is shown in Figure 3-1, with
8 MHz, 1 s @ 4 MHz) except for program branches. the corresponding device pins described in Table 3-2.
Table 3-1 below lists memory supported by the
PIC12F529T39A device.
TABLE 3-1: PIC12F529T39A MEMORY

Program
Data Memory
Memory
Device Flash
Flash SRAM
Data
(words) (bytes)
(bytes)
PIC12F529T39A 1536 201 64
The PIC12F529T39A device can directly or indirectly
address its register files and data memory. All Special
Function Registers (SFR), including the PC, are
mapped in the data memory. The PIC12F529T39A
device has a highly orthogonal (symmetrical) instruc-
tion set that makes it possible to carry out any opera-
tion, on any register, using any addressing mode. This
symmetrical nature and lack of “special optimal situa-
tions” make programming with the PIC12F529T39A
device simple, yet efficient. In addition, the learning
curve is reduced significantly.
The PIC12F529T39A device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.

PIC12F529T39A
FIGURE 3-1: PIC12F529T39A ARCHITECTURAL BLOCK DIAGRAM
11 8 PORTB
Data Bus
Flash Program Counter
1.5K x 12 GP0/ICSPDAT
Self-write GP1/ICSPCLK
64x8 RAM GP2/T0CKI
STACK1 201 GP3/MCLR/VPP
Program bytes
Memory STACK2 GP4/OSC2
GPR GP5/OSC1/CLKIN
STACK3
Program 12
Bus STACK4 RAM Addr 8
Addr MUX
Instruction reg
0-4 Indirect
0-7 Addr
3 Direct Addr 5-7 FSR reg
BSR
STATUS reg
8
3 MUX
Device Reset
Timer DATA PA RFOUT
Instruction
Decode & Power-on
Reset ALU
Control CP VDDRF
Watchdog 8
Timer VSSRF
OSC1/CLKIN Timing PFD
Generation Internal RC W reg
OSC2 XTAL
Clock M/N
Sigma/
Delta
Timer0
MCLR CTRL Control Logic
VDD, VSS
Note 1: 201-byte GPR in PIC12F529T39A, including linear RAM.

2: FSR and direct addressing differs from standard baseline parts.

PIC12F529T39A
TABLE 3-2: PIC12F529T39A PINOUT DESCRIPTION
Name Function Type Input Type Output Type Description
GP0/ICSPDAT GP0 I/O TTL CMOS Bidirectional I/O port with weak pull-up.
ICSPDAT I/O ST CMOS ICSP™ mode Schmitt Trigger.
GP1/ICSPCLK GP1 I/O TTL CMOS Bidirectional I/O port with weak pull-up.
ICSPCLK I ST — ICSP™ mode Schmitt Trigger.
GP2/T0CKI GP2 I/O TTL CMOS Bidirectional I/O port.
T0CKI I ST — Timer0 clock input.
GP3/MCLR/VPP GP3 I TTL — Standard TTL input with weak pull-up.
MCLR I ST — MCLR input (weak pull-up always enabled in
this mode).
VPP I High Voltage — Test mode high-voltage pin.
GP4/OSC2 GP4 I/O TTL CMOS Bidirectional I/O port.
OSC2 O — XTAL XTAL oscillator output pin for microcontroller.
GP5/OSC1/ GP5 I/O TTL CMOS Bidirectional I/O port.
CLKIN OSC1 I XTAL — XTAL oscillator input pin for microcontroller.
CLKIN I ST — EXTRC Schmitt Trigger input.
VDD VDD P Power — Positive supply for logic and I/O pins.
VSS VSS P Power — Ground reference for logic and I/O pins.
VDDRF VDDRF P Power — Positive Power Supply for RF Transmitter.
CTRL CTRL I CMOS — Configuration Selection and Configuration
Clock.
RFOUT RFOUT O — RF Transmitter RF output.
VSSRF VSSRF P Power — Ground reference for RF Transmitter.
DATA DATA I/O CMOS CMOS Configuration Data and Transmit Data.
XTAL XTAL I XTAL — Crystal oscillator input pin for RF Transmitter.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog Voltage

PIC12F529T39A
3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining
Cycle An instruction cycle consists of four Q cycles (Q1, Q2,
The clock input (OSC1/CLKIN pin) is internally divided Q3 and Q4). The instruction fetch and execute are
by four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle,
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC while decode and execute take another instruction
is incremented every Q1 and the instruction is fetched cycle. However, due to the pipelining, each instruction
from program memory and latched into the instruction effectively executes in one cycle. If an instruction
register in Q4. It is decoded and executed during the causes the PC to change (e.g., GOTO), then two cycles
following Q1 through Q4. The clocks and instruction are required to complete the instruction (Example 3-1).
execution flow is shown in Figure 3-2 and Example 3-1. A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC + 1 PC + 2
Fetch INST (PC)

Execute INST (PC - 1) Fetch INST (PC + 1)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 03H Fetch 1 Execute 1

2. MOVWF GPIO Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF GPIO, 1 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

PIC12F529T39A
4.0 MEMORY ORGANIZATION FIGURE 4-1: MEMORY MAP
The PIC12F529T39A memory is organized into PC<11:0>
program memory and data memory (SRAM). The self- CALL, RETLW 10
writable portion of the program memory called Flash
data memory, is located at addresses 600h-63Fh. As Stack Level 1
the device has more than 512 bytes of program Stack Level 2
memory, a paging scheme is used. Program memory Stack Level 3
pages are accessed using STATUS register bit, PA0. Stack Level 4
For the PIC12F529T39A, with data memory register
files of more than 32 registers, a banking scheme is
used. Data memory banks are accessed using the File Reset Vector(1) 0000h
Select Register (FSR).
On-chip Program
4.1 Program Memory Organization for Memory
the PIC12F529T39A
User Memory
Space
The PIC12F529T39A device has an 11-bit Program 512 Word 01FFh
Counter (PC) capable of addressing a 2K x 12 program 0200h
memory space.
Only the first 1.5K x 12 (0000h-05FFh) are physically On-chip Program
implemented (see Figure 4-1). Accessing a location Memory
above these boundaries will cause a wrap-around
within the 1.5K x 12 space. The effective Reset 512 Word 03FFh
vector is a 0000h (see Figure 4-1). Location 05FFh 0400h
contains the internal clock oscillator calibration
On-chip Program
value. This value should never be overwritten.
Memory
512 Word
05FFh
Flash Data Memory
0600h
Space
Flash Data Memory(2)
063Fh
0640h
07FFh
Note 1: Address 0000h becomes the effective

Reset vector. Location 05FFh contains
the MOVLW XX internal oscillator
calibration value.
2: Flash data memory is non-executable.

PIC12F529T39A
4.2 Data Memory (SRAM and FSRs)
Data memory is composed of registers or bytes of
SRAM. Therefore, data memory for a device is
specified by its register file. The register file is divided
into two functional groups: Special Function Registers
(SFR) and General Purpose Registers (GPR).
The Special Function Registers include the TMR0
register, the Program Counter Low (PCL), the STATUS
register, the I/O register (port) and the File Select
Register (FSR). In addition, the EECON, EEDATA and
EEADR registers provide for interface with the Flash
data memory.
The PIC12F529T39A register file is composed of 10
Special Function Registers and 201 General Purpose
Registers.
4.2.1 GENERAL PURPOSE REGISTER

FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.8 “Indirect Data Addressing:
INDF and FSR Registers”.
FIGURE 4-2: REGISTER FILE MAP

BSR<2:0>
000 001 010 011 100 101 110 111
File Address
20h 40h 60h 80h A0h C0h E0h
INDF(1) INDF(1) INDF(1) INDF(1)
00h
TMR0 EECON TMR0 EECON
01h
PCL PCL PCL PCL
02h
STATUS STATUS STATUS STATUS
03h
FSR FSR FSR FSR
04h
OSCCAL EEDATA OSCCAL EEDATA
05h
Linear Linear Linear Linear
PORTB EEADR PORTB EEADR General
06h General General General
07h Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
General
Addresses map back to
Purpose
addresses in Bank 0.
Registers
0Fh 2Fh 4Fh 6Fh

10h 30h 50h 70h
General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
1Fh 3Fh 5Fh 7Fh 9Fh BFh DFh FFh

Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Note 1: Not a physical register.

PIC12F529T39A
4.2.2 SPECIAL FUNCTION REGISTERS 4.2.3 LINEAR RAM
The Special Function Registers (SFRs) are registers The last four banks, addresses 0x80 to 0xFF, are
used by the CPU and peripheral functions to control the general purpose RAM registers, unbroken by SFRs.
operation of the device (Table 4-1). This region is ideal for indirect access using the FSR
The Special Function Registers can be classified into and INDF registers.
two sets. The Special Function Registers associated Note: Unlike other baseline devices, the FSR
with the “core” functions are described in this section. register does not contain bank bits and,
Those related to the operation of the peripheral therefore, does not affect direct
features are described in the section for each addressing schemes. The FSR/INDF
peripheral feature. registers have full access to RAM.
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on
Reset
N/A TRIS — — TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 --11 1111
N/A OPTION Contains Control Bits to Configure Timer0 and Timer0/WDT Prescaler 1111 1111
N/A BSR — — — — — BSR<2:0> ---- -000
00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx
01h TMR0 Timer0 Module Register xxxx xxxx
02h(1) PCL Low Order 8 bits of PC 1111 1111
03h STATUS GPWUF PA1 PA0 TO PD Z DC C 0001 1xxx
04h FSR Indirect Data Memory Address Pointer 110x xxxx
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111-
06h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx
21h EECON — — — FREE WRERR WREN WR RD ---0 x000
EEDA-
25h EEDATA EEDATA7 TA6 EEDATA5 EEDATA4 EEDATA3 EEDATA2 EEDATA1 EEDATA0 xxxx xxxx
26h EEADR — — EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 --xx xxxx
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to
access these bits.

PIC12F529T39A
4.3 STATUS Register For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
This register contains the arithmetic status of the ALU, as ‘000u u1uu’ (where u = unchanged).
the Reset status and the page preselect bit.
Therefore, it is recommended that only BCF, BSF and
The STATUS register can be the destination for any MOVWF instructions be used to alter the STATUS
instruction, as with any other register. If the STATUS register. These instructions do not affect the Z, DC or C
register is the destination for an instruction that affects bits from the STATUS register. For other instructions
the Z, DC or C bits, then the write to these three bits is which do affect Status bits, see Section 10.0
disabled. These bits are set or cleared according to the “Instruction Set Summary”.
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 4-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
GPWUF PA1 PA0 TO PD Z DC C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPWUF: Wake-up From Sleep on Pin Change bit

1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6-5 PA<1:0>: Program Page Preselect bits(1)
00 = Page 0 (000h-1FFh)
01 = Page 1 (200h-3FFh)
10 = Page 2 (400h-5FFh)
11 = Reserved. Do not use.
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF: SUBWF: RRF or RLF:
1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
Note 1: Do not set both PA0 and PA1.

PIC12F529T39A
4.4 OPTION Register By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
The OPTION register is a 8-bit wide, write-only register, register. A Reset sets the OPTION<7:0> bits.
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0. Note: If the T0SC bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-2: OPTION: OPTION REGISTER

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPWU GPPU T0CS T0SE PSA PS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 GPWU: Enable Wake-up On Pin Change bit

1 = Disabled
0 = Enabled
bit 6 GPPU: Enable Weak Pull-Ups bit
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

PIC12F529T39A
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used
to calibrate the 8 MHz internal oscillator macro. It
contains seven bits of calibration that uses a two’s
complement scheme for controlling the oscillator speed.
See Register 4-3 for details.
REGISTER 4-3: OSCCAL: OSCILLATOR CALIBRATION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0
CAL<6:0> —
bit 7 bit 0
Legend:
bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 = Minimum frequency
bit 0 Unimplemented: Read as ‘0’

PIC12F529T39A
4.6 Program Counter 4.6.1 EFFECTS OF RESET
As a program instruction is executed, the Program The PC is set upon a Reset, which means that the PC
Counter (PC) will contain the address of the next addresses the last location in the last page (i.e., the
program instruction to be executed. The PC value is oscillator calibration instruction). After executing
increased by one every instruction cycle, unless an MOVLW XX, the PC will roll over to location 00h and
instruction changes the PC. begin executing user code.
For a GOTO instruction, bits <8:0> of the PC are The STATUS register page preselect bits are cleared
provided by the GOTO instruction word. The Program upon a Reset, which means that page 0 is pre-selected.
Counter (PCL) is mapped to PC<7:0>. Bits 5 and 6 of Therefore, upon a Reset, a GOTO instruction will
the STATUS register provide page information to bits 9 automatically cause the program to jump to page 0 until
and 10 of the PC. (Figure 4-3). the value of the page bits is altered.
For a CALL instruction, or any instruction where the
PCL is the destination, bits <7:0> of the PC again are 4.7 Stack
provided by the instruction word. However, PC<8>
The PIC12F529T39A device has a four-deep, 12-bit
does not come from the instruction word, but is always
wide hardware PUSH/POP stack.
cleared (Figure 4-3).
A CALL instruction will PUSH the current value of Stack
Instructions where the PCL is the destination, or modify
1 into Stack 2 and then PUSH the current PC value,
PCL instructions, include MOVWF PCL, ADDWF PCL
incremented by one, into Stack Level 1. If more than four
and BSF PCL,5.
sequential CALLs are executed, only the most recent
Note: Because PC<8> is cleared in the CALL four return addresses are stored.
instruction or any modify PCL instruction, A RETLW instruction will POP the contents of Stack
all subroutine calls or computed jumps are Level 1 into the PC and then copy Stack Level 2
limited to the first 256 locations of any contents into Stack Level 1. If more than four sequen-
program memory page (512 words long). tial RETLWs are executed, the stack will be filled with
the address previously stored in Stack Level 2. Note
FIGURE 4-3: LOADING OF PC that the W register will be loaded with the literal value
BRANCH INSTRUCTIONS specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
GOTO Instruction program memory.
10 9 8 7 0
Note 1: There are no Status bits to indicate Stack
PC PCL
Overflow or Stack Underflow conditions.
2: There are no instruction mnemonics
Instruction Word called PUSH or POP. These are actions
PA<1:0> that occur from the execution of the CALL
7 0 and RETLW instructions.
Status
CALL or Modify PCL Instruction

10 9 8 7 0
PC PCL
Instruction Word
PA<1:0> Reset to ‘0’
7 0
Status

PIC12F529T39A
4.8 Indirect Data Addressing: INDF EXAMPLE 4-1: HOW TO CLEAR RAM
and FSR Registers USING INDIRECT
ADDRESSING
The INDF register is not a physical register.
Addressing INDF actually addresses the register MOVLW 0x10 ;initialize pointer
whose address is contained in the FSR register (FSR MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF
is a pointer). This is indirect addressing.
;register
Reading INDF itself indirectly (FSR = 0) will produce INCF FSR,F ;inc pointer
00h. Writing to the INDF register indirectly results in a BTFSC FSR,4 ;all done?
no-operation (although Status bits may be affected). GOTO NEXT ;NO, clear next
CONTINUE
The FSR is an 8-bit wide register. It is used in : ;YES, continue
conjunction with the INDF register to indirectly address :
the data memory area.
FIGURE 4-4: DIRECT/INDIRECT ADDRESSING

Direct Addressing Indirect Addressing
(BSR) (opcode) (FSR)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Bank Select Location Select Location Select

000 001 010 011 100 101 110 111
00h
Addresses map back to

addresses in Bank 0/1
Data 0Fh
Memory 10h
1Fh
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
4.9 Direct Data Addressing

Banking when using direct addressing methods is
accomplished using the MOVLB instruction to write to
the BSR. The BSR, like the OPTION register, is not
mapped to user-accessible memory. The value in BSR
has no effect on indirect addressed operations.

PIC12F529T39A
5.0 FLASH DATA MEMORY 3. Perform a row erase of the row of interest.
CONTROL 4. Write the new byte of data and any saved bytes
back to the appropriate addresses in Flash data
The Flash data memory is readable and writable during memory.
normal operation (full VDD range). This memory is not
To prevent accidental corruption of the Flash data
directly mapped in the register file space. Instead, it is
memory, an unlock sequence is required to initiate a
indirectly addressed through the Special Function
write or erase cycle. This sequence requires that the bit
Registers (SFRs).
set instructions used to configure the EECON register
happen exactly as shown in Example 5-2 and
5.1 Reading Flash Data Memory Example 5-3, depending on the operation requested.
To read a Flash data memory location the user must:
5.2.1 ERASING FLASH DATA MEMORY
• Write the EEADR register
A row must be manually erased before writing new
• Set the RD bit of the EECON register data. The following sequence must be performed for a
The value written to the EEADR register determines single row erase.
which Flash data memory location is read. Setting the 1. Load EEADR with an address in the row to be
RD bit of the EECON register initiates the read. Data erased.
from the Flash data memory read is available in the
2. Set the FREE bit to enable the erase.
EEDATA register immediately. The EEDATA register
will hold this value until another read is initiated or it is 3. Set the WREN bit to enable write access to the
modified by a write operation. Program execution is array.
suspended while the read cycle is in progress. 4. Set the WR bit to initiate the erase cycle.
Execution will continue with the instruction following the If the WREN bit is not set in the instruction cycle after
one that sets the WR bit. See Example 5-1 for sample the FREE bit is set, the FREE bit will be cleared in
code. hardware.
If the WR bit is not set in the instruction cycle after the
EXAMPLE 5-1: READING FROM FLASH
WREN bit is set, the WREN bit will be cleared in
DATA MEMORY hardware.
BANKSEL EEADR ;
Sample code that follows this procedure is included in
MOVF DATA_EE_ADDR, W ;
Example 5-2.
MOVWF EEADR ;Data Memory
;Address to read Program execution is suspended while the erase cycle
BANKSEL EECON1 ; is in progress. Execution will continue with the
instruction following the one that sets the WR bit.
BSF EECON, RD ;EE Read
MOVF EEDATA, W ;W = EEDATA EXAMPLE 5-2: ERASING A FLASH DATA
MEMORY ROW
BANKSEL EEADR
Note: Only a BSF command will work to enable MOVLW EE_ADR_ERASE ; LOAD ADDRESS OF ROW TO
the Flash data memory read documented in ; ERASE
Example 5-1. No other sequence of MOVWF EEADR ;
commands will work, no exceptions. BSF EECON,FREE ; SELECT ERASE
BSF EECON,WREN ; ENABLE WRITES
BSF EECON,WR ; INITITATE ERASE
5.2 Writing and Erasing Flash Data
Memory
Flash data memory is erased one row at a time and Note 1: The FREE bit may be set by any
written one byte at a time. The 64-byte array is made command normally used by the core.
up of eight rows. A row contains eight sequential bytes. However, the WREN and WR bits can
Row boundaries exist every eight bytes. only be set using a series of BSF
Generally, the procedure to write a byte of data to Flash commands, as documented in
data memory is: Example 5-1. No other sequence of
commands will work, no exceptions.
1. Identify the row containing the address where
the byte will be written. 2: Bits <5:3> of the EEADR register indicate
which row is to be erased.
2. If there is other information in that row that must
be saved, copy those bytes from Flash data
memory to RAM.

PIC12F529T39A
5.2.2 WRITING TO FLASH DATA EXAMPLE 5-4: WRITE VERIFY OF DATA
MEMORY EEPROM
Once a cell is erased, new data can be written. MOVF EEDATA, W ;EEDATA has not changed
Program execution is suspended during the write cycle. ;from previous write
The following sequence must be performed for a single BSF EECON, RD ;Read the value written
byte write. XORWF EEDATA, W ;
BTFSS STATUS, Z ;Is data the same
1. Load EEADR with the address.
GOTO WRITE_ERR ;No, handle error
2. Load EEDATA with the data to write. ;Yes, continue
3. Set the WREN bit to enable write access to the
array.
4. Set the WR bit to initiate the erase cycle. 5.4 Code Protection
If the WR bit is not set in the instruction cycle after the Code protection does not prevent the CPU from
WREN bit is set, the WREN bit will be cleared in performing read or write operations on the Flash data
hardware. memory. Refer to the code protection chapter for more
Sample code that follows this procedure is included in information.
Example 5-3.
EXAMPLE 5-3: WRITING A FLASH DATA

MEMORY ROW
BANKSEL EEADR
MOVLW EE_ADR_WRITE ; LOAD ADDRESS
MOVWF EEADR ;
MOVLW EE_DATA_TO_WRITE ; LOAD DATA
MOVWF EEDATA ; INTO EEDATA REGISTER
BSF EECON,WREN ; ENABLE WRITES
BSF EECON,WR ; INITITATE ERASE
Note 1: Only a series of BSF commands will work

to enable the memory write sequence
documented in Example 5-2. No other
sequence of commands will work, no
exceptions.
2: For reads, erases and writes to the Flash
data memory, there is no need to insert a
NOP into the user code as is done on
mid-range devices. The instruction
immediately following the “BSF
EECON,WR/RD” will be fetched and
executed properly.
5.3 Write Verify

Depending on the application, good programming
practice may dictate that data written to the Flash data
memory be verified. Example 5-4 is an example of a
write verify.

PIC12F529T39A
NOTES:

PIC12F529T39A
6.0 I/O PORT 6.2 TRIS Registers
As with any other register, the I/O register(s) can be The Output Driver Control registers are loaded with
written and read under program control. However, read the contents of the W register by executing the TRIS f
instructions (e.g., MOVF PORTB,W) always read the I/O instruction. A ‘1’ from a TRISGPIO register bit puts the
pins independent of the pin’s Input/Output modes. On corresponding output driver in a high-impedance
Reset, all I/O ports are defined as input (inputs are at (Input) mode. A ‘0’ puts the contents of the output data
high-impedance) since the I/O control registers are all latch on the selected pins, enabling the output buffer.
set. The TRISGPIO register is “write-only”. Bits <5:0> are
set (output drivers disabled) upon Reset.
6.1 GPIO
Note: If the T0CS bit is set to ‘1’, it will override
GPIO is an 8-bit I/O register. Only the low-order six bits the TRISGPIO function on the T0CKI pin.
are used (GP<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s. Please note that GP3 is an input-only TABLE 6-1: WEAK PULL-UP ENABLED
pin. The Configuration Word can set several I/O’s to
PINS
alternate functions. When acting as alternate functions,
the pins will read as ‘0’ during a port read. Pins GP0, Pin WPU WU
GP1, and GP3 can be configured with weak pull-ups GP0 Y Y
and also for wake-up on change. The wake-up on
GP1 Y Y
change and weak pull-up functions are not pin select-
able. If GP3/MCLR is configured as MCLR, weak pull- GP2 N N
up is always on and wake-up on change for this pin is GP3 Y(1) Y
not enabled. GP4 N N
GP5 N N
Note 1: When MCLRE = 1, the weak pull-up on
GP3/MCLR is always enabled.
2: WPU = Weak pull-up; WU = Wake-up.

PIC12F529T39A
REGISTER 6-1: GPIO: GPIO REGISTER

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — GP5 GP4 GP3 GP2 GP1 GP0
bit 7 bit 0
Legend:
bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GP<5:0>: GPIO I/O Pin bits
1 = GPIO pin is >VIH min.
0 = GPIO pin is <VIL max.
REGISTER 6-2: TRISGPIO: TRI-STATE GPIO REGISTER

U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1
— — TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0
bit 7 bit 0
Legend:
bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISGPIO<5:0>: GPIO Tri-State Control bits
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output

PIC12F529T39A
6.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 6-1. All port pins, except GP3 which is input
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRISGPIO must be cleared (= 0). For use
as an input, the corresponding TRISGPIO bit must be
set. Any I/O pin (except GP3) can be programmed
individually as input or output.
FIGURE 6-1: PIC12F529T39A EQUIVALENT CIRCUIT FOR I/O PINS – GP0/GP1

VDD VDD
GPPU
Data D Q
I/O
Data Latch
Pin
WR CK Q
WREG D Q
VSS
TRIS Latch
TRIS ‘F’ CK Q
RD Port
Q D
Wake-up
on change
Latch
CK
Pin Change
GP0/ICSPDAT GP1/ICSPCLK
• General purpose I/O • General purpose I/O
• In-Circuit Serial Programming™ data • In-circuit Serial Programming™ clock
• Wake-up on input change trigger • Wake-up on input change trigger

PIC12F529T39A
FIGURE 6-2: GP2/TOCK1
VDD
• General Purpose I/O
• A Clock Input for Timer0
Data D Q
I/O
Data Latch
Pin
WR CK Q
WREG D Q
VSS
TRIS Latch
TRIS ‘F’ CK Q
TOCS
RD Port
To Timer0

PIC12F529T39A
FIGURE 6-3: GP4/OSC2

• A crystal resonator connection
VDD
From OSC1
Oscillator Circuit
DATA D Q
BUS
I/O
Data Latch
Pin
WR
CK Q
PORT
WREG D Q
VSS
TRIS Latch
TRIS ‘F’ CK Q
INTOSC
RC
RD
PORT

PIC12F529T39A
FIGURE 6-4: GP5/OSC1/CLKIN
VDD
From OSC2 Oscillator Circuit
DATA D Q
BUS
I/O
Data Latch
Pin
WR
CK Q
PORT
WREG D Q
VSS
TRIS Latch
TRIS ‘F’ CK Q

• A crystal resonator connection
• A clock input
RD
PORT

PIC12F529T39A
FIGURE 6-5: GP3 (WITH WEAK PULL-
UP AND WAKE-UP ON
CHANGE)
GPPU
Weak
MCLRE
Reset
Input Pin(1)
VSS
Data Bus
RD Port
Q D
Wake-up
on change
latch
CK
Pin Change
Note 1: GP3/MCLR pin has a protection diode to VSS

only.
TABLE 6-2: SUMMARY OF PORT REGISTERS

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 22
TRISGPIO — — TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 22
STATUS GPWUF PA1 PA0 TO PD Z DC C 13
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 14
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, Shaded cells = unimplemented, read as ‘0’,
q = depends on the condition

PIC12F529T39A
6.4 I/O Programming Considerations EXAMPLE 6-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
6.4.1 BIDIRECTIONAL I/O PORTS I/O PORT
Some instructions operate internally as read followed ;Initial GPIO Settings
by write operations. The BCF and BSF instructions, for ;GPIO<5:3> Inputs
example, read the entire port into the CPU, execute the ;GPIO<2:0> Outputs
bit operation and re-write the result. Caution must be ;
used when these instructions are applied to a port ; GPIO latch GPIO pins
; ---------- ----------
where one or more pins are used as input/outputs. For
BCF GPIO, 5 ;--01 -ppp --11 pppp
example, a BSF operation on bit 5 of GPIO will cause
BCF GPIO, 4 ;--10 -ppp --11 pppp
all eight bits of GPIO to be read into the CPU, bit 5 to MOVLW 007h;
be set and the GPIO value to be written to the output TRIS GPIO ;--10 -ppp --11 pppp
latches. If another bit of GPIO is used as a bidirectional ;
I/O pin (say bit 0) and it is defined as an input at this Note 1: The user may have expected the pin values to
time, the input signal present on the pin itself would be be ‘--00 pppp’. The 2nd BCF caused GP5 to
read into the CPU and rewritten to the data latch of this be latched as the pin value (High).
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
6.4.2 SUCCESSIVE OPERATIONS ON
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown. I/O PORTS
Example 6-1 shows the effect of two sequential The actual write to an I/O port happens at the end of an
Read-Modify-Write instructions (e.g., BCF, BSF, etc.) instruction cycle, whereas for reading, the data must be
on an I/O port. valid at the beginning of the instruction cycle (Figure 6-6).
Therefore, care must be exercised if a write, followed by
A pin actively outputting a high or a low should not be a read operation, is carried out on the same I/O port. The
driven from external devices at the same time in order sequence of instructions should allow the pin voltage to
to change the level on this pin (“wired OR”, “wired stabilize (load dependent) before the next instruction
AND”). The resulting high output currents may damage causes that file to be read into the CPU. Otherwise, the
the chip. previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
FIGURE 6-6: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC + 1 PC + 2 PC + 3 This example shows a write to GPIO followed

Instruction by a read from GPIO.
Fetched MOVWF GPIO MOVF GPIO, W NOP NOP Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
GP<5:0>
TPD = propagation delay
Port pin Port pin Therefore, at higher clock frequencies, a
written here sampled here write followed by a read may be problematic.
Instruction
Executed MOVWF GPIO MOVF PORTB,W NOP
(Write to GPIO) (Read PORTB)

PIC12F529T39A
7.0 TIMER0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
REGISTER
either on every rising or falling edge of pin T0CKI. The
The Timer0 module has the following features: T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
• 8-bit timer/counter register, TMR0
Restrictions on the external clock input are discussed
• Readable and writable in detail in Section 7.1 “Using Timer0 with an
• 8-bit software programmable prescaler External Clock”.
• Internal or external clock select: The prescaler may be used by either the Timer0
- Edge select for external clock module or the Watchdog Timer, but not both. The
Figure 7-1 is a simplified block diagram of the Timer0 prescaler assignment is controlled in software by the
module. control bit, PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
Timer mode is selected by clearing the T0CS bit
readable or writable. When the prescaler is assigned to
(OPTION<5>). In Timer mode, the Timer0 module will
the Timer0 module, prescale values of 1:2, 1:4,...,
increment every instruction cycle (without prescaler). If
1:256 are selectable. Section 7.2 “Prescaler” details
the TMR0 register is written, the increment is inhibited
the operation of the prescaler.
for the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted A summary of registers associated with the Timer0
value to the TMR0 register. module is found in Table 7-1.
The Timer0 contained in the CPU core follows the
standard baseline definition.
FIGURE 7-1: TIMER0 BLOCK DIAGRAM

Data Bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0 Reg
T0CKI Programmable Clocks
0 PSout
pin Prescaler(2)
T0SE(1) (2 cycle delay) Sync
3
PSA(1)
(1)
PS2, PS1, PS0(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer.
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2

PIC12F529T39A
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Timer0 T0 T0 + 1 NT0 NT0 + 1
Instruction
Executed Read TMR0
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

Register
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter 29*

N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 14
N/A TRIS — — TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 —
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, Shaded cells = unimplemented, read as ‘0’.
* Page provides register information.

PIC12F529T39A
7.1 Using Timer0 with an External When a prescaler is used, the external clock input is
Clock divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
When an external clock input is used for Timer0, it must For the external clock to meet the sampling require-
meet certain requirements. The external clock ment, the ripple counter must be taken into account.
requirement is due to internal phase clock (TOSC) Therefore, it is necessary for T0CKI to have a period of
synchronization. Also, there is a delay in the actual at least four TOSC (and a small RC delay of four Tt0H)
incrementing of Timer0 after synchronization. divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
7.1.1 EXTERNAL CLOCK the minimum pulse width requirement of Tt0H. Refer to
SYNCHRONIZATION parameters 40, 41 and 42 in the electrical specification
When no prescaler is used, the external clock input is of the desired device.
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is 7.1.2 TIMER0 INCREMENT DELAY
accomplished by sampling the prescaler output on the Since the prescaler output is synchronized with the
Q2 and Q4 cycles of the internal phase clocks internal clocks, there is a small delay from the time the
(Figure 7-4). Therefore, it is necessary for T0CKI to be external clock edge occurs to the time the Timer0
high for at least two TOSC (and a small RC delay of two module is actually incremented. Figure 7-4 shows the
Tt0H) and low for at least two TOSC (and a small RC delay from the external clock edge to the timer
delay of two Tt0H). Refer to the electrical specification incrementing.
of the desired device.
FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or Small pulse
Prescaler Output (2) misses sampling
(1)
External Clock/Prescaler (3)
Output After Sampling
Increment Timer0 (Q4)
Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the times at which sampling occurs.

PIC12F529T39A
7.2 Prescaler EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0 →WDT)
An 8-bit counter is available as a prescaler for the
CLRWDT ;Clear WDT
Timer0 module or as a postscaler for the Watchdog CLRF TMR0 ;Clear TMR0 and Prescaler
Timer (WDT), respectively (see Section 8.6 MOVLW b‘00xx1111’
“Watchdog Timer (WDT)”). For simplicity, this counter OPTION
is being referred to as “prescaler” throughout this data
sheet. CLRWDT ;PS<2:0> are 000 or 001
MOVLW b‘00xx1xxx’ ;Set Postscaler to
Note: The prescaler may be used by either the OPTION ;desired WDT rate
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the Tim- To change the prescaler from the WDT to the Timer0
er0 module means that there is no pres- module, use the sequence shown in Example 7-2. This
caler for the WDT and vice versa. sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio. switching the prescaler.
When assigned to the Timer0 module, all instructions EXAMPLE 7-2: CHANGING PRESCALER
writing to the TMR0 register (e.g., CLRF TMR0,
(WDT →TIMER0)
MOVWF TMR0, etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the CLRWDT ;Clear WDT and
;prescaler
prescaler along with the WDT. The prescaler is neither
MOVLW b‘xxxx0xxx’ ;Select TMR0, new
readable nor writable. On a Reset, the prescaler
;prescale value and
contains all ‘0’s. ;clock source
OPTION
7.2.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 7-
1) must be executed when changing the prescaler
assignment from Timer0 to the WDT.

PIC12F529T39A
FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/ WDT PRESCALER(1)
TCY (= FOSC/4)
Data Bus
0 8
M 1
T0CKI U M
1 X Sync
Pin U 2 TMR0 Reg
0 X Cycles
T0SE
T0CS
PSA
0
8-bit Prescaler
M
U
1 X
Watchdog 8
Timer
8-to-1 MUX PS<2:0>
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-Out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

PIC12F529T39A
8.0 SPECIAL FEATURES OF THE The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
CPU
through a change-on-input-pins or through a Watchdog
What sets a microcontroller apart from other processors Timer time-out. Several oscillator options are also made
are special circuits that deal with the needs of real-time available to allow the part to fit the application, including
applications. The PIC12F529T39A microcontroller has an internal 4 MHz or 8 MHz oscillator. The EXTRC
a host of such features intended to maximize system oscillator option saves system cost while the LP crystal
reliability, minimize cost through elimination of external option saves power. A set of Configuration bits are used
components, provide power-saving operating modes to select various options.
and offer code protection. These features are:
• Oscillator Selection 8.1 Configuration Bits
• Reset: The PIC12F529T39A Configuration Words consist of
- Power-on Reset (POR) 12 bits. Configuration bits can be programmed to select
- Device Reset Timer (DRT) various device configurations. Two bits are for the
- Wake-up from Sleep on Pin Change selection of the oscillator type; one bit is the Watchdog
Timer enable bit, one bit is the MCLR enable bit and six
• Watchdog Timer (WDT)
bits are for code protection (Register 8-1).
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
The PIC12F529T39A device has a Watchdog Timer,
which can be shut off only through Configuration bit
WDTE. It runs off of its own RC oscillator for added
reliability. If using XT or LP selectable oscillator options,
there is always an 18 ms (nominal) delay provided by
the Device Reset Timer (DRT), intended to keep the
chip in Reset until the crystal oscillator is stable. If using
INTRC or EXTRC, the DRT provides a 1 ms (nominal)
delay.

PIC12F529T39A
REGISTER 8-1: CONFIG: CONFIGURATION WORD REGISTER(1)

U-1 P-1 P-1 P-1 P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— CP3 CP2 CP1 CP0 CPDF IOSCFS MCLRE PARITY WDTE FOSC1 FOSC0
bit 11 bit 0
Legend:
bit 11 Unimplemented: Read as ‘1’

bit 10-7 CP<3:0>: Enhanced Code Protect bits
1011 = Code protect disabled
0010 = Code protect enabled
All others = Memory access disabled(3)
bit 6 CPDF: Code Protection bit – Flash Data Memory
1 = Code protection off
0 = Code protection on
bit 5 IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 4 MCLRE: Master Clear Enable bit
1 = GP3/MCLR pin functions as MCLR
0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD
bit 3 PARITY: Configuration Word Parity bit(4)
1 = Parity bit set
0 = Parity bit clear
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC<1:0>: Oscillator Selection bits
00 = LP oscillator with 18 ms DRT(2)
01 = XT oscillator with 18 ms DRT(2)
10 = INTRC with 1 ms DRT(2)
11 = EXTRC with 1 ms DRT(2)
Note 1: Refer to the “PIC12F529T48A/T39A Memory Programming Specification” (DS41619) to determine how to
program/erase the Configuration Word.
2: DRT length (18 ms or 1 ms) is a function of clock mode selection. It is the responsibility of the application
designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in
acceptable operation. Refer to Figure 12-1 for VDD rise time and stability requirements for this mode of
operation.
3: See Section 8.9 “Program Verification/Code Protection”.
4: Set or clear to create odd parity with Configuration Word excluding CP<3:0>.

PIC12F529T39A
8.2 Oscillator Configurations FIGURE 8-2: EXTERNAL CLOCK INPUT
OPERATION (XT OR LP
8.2.1 OSCILLATOR TYPES OSC CONFIGURATION)
The PIC12F529T39A device can be operated in up to
four different oscillator modes. The user can program
Clock from OSC1
using the Configuration bits (FOSC<1:0>), to select one
ext. system PIC12F529
of these modes:
Open OSC2
• LP: Low-Power Crystal
• XT: Crystal/Resonator
• INTRC: Internal 4 MHz or 8 MHz Oscillator
• EXTRC: External Resistor/Capacitor TABLE 8-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
8.2.2 CRYSTAL OSCILLATOR/CERAMIC
Osc Resonator Cap. Range Cap. Range
RESONATORS
Type Freq. C1 C2
In XT or LP modes, a crystal or ceramic resonator is
XT 4.0 MHz 30 pF 30 pF
connected to the (GP5)/OSC1/(CLKIN) and
(GP4)/OSC2 pins to establish oscillation (Figure 8-1). Note: Component values shown are for design
The PIC12F529T39A oscillator designs require the use guidance only. Since each resonator has
of a parallel cut crystal. Use of a series cut crystal may its own characteristics, the user should
give a frequency out of the crystal manufacturers consult the resonator manufacturer for
specifications. When in XT or LP modes, the device can appropriate values of external
have an external clock source drive the components.
(GP5)/OSC1/CLKIN pin (Figure 8-2). When the part is
used in this manner, the output drive levels on the OSC2 TABLE 8-2: CAPACITOR SELECTION FOR
pin are very weak. This pin should be left open and CRYSTAL OSCILLATOR –
unloaded. Also when using this mode, the external clock PIC12F529T39A(2)
should observe the frequency limits for the clock mode
chosen (XT or LP). Osc Resonator Cap.Range Cap. Range
Type Freq. C1 C2
Note 1: The user should verify that the device
oscillator starts and performs as LP 32 kHz(1) 15 pF 15 pF
expected. Adjusting the loading XT 200 kHz 47-68 pF 47-68 pF
capacitor values and/or the Oscillator 1 MHz 15 pF 15 pF
mode may be required. 4 MHz 15 pF 15 pF
Note 1: For VDD > 4.5V, C1 = C2  30 pF is
FIGURE 8-1: CRYSTAL OPERATION recommended.
(OR CERAMIC 2: Component values shown are for design
RESONATOR) guidance only. Rs may be required to
(XT OR LP OSC avoid overdriving crystals with low-drive
CONFIGURATION) level specification. Since each crystal has
its own characteristics, the user should
C1(1) OSC1 PIC12F529 consult the crystal manufacturer for
appropriate values of external
Sleep components.
XTAL RF(3)
To Internal
Logic
OSC2
RS(2)
C2(1)
Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF approx. value = 10 M.

PIC12F529T39A
8.2.3 EXTERNAL CRYSTAL OSCILLATOR 8.2.4 EXTERNAL RC OSCILLATOR
CIRCUIT For timing insensitive applications, the RC circuit option
Either a pre-packaged oscillator or a simple oscillator offers additional cost savings. The RC oscillator
circuit with TTL gates can be used as an external frequency is a function of the supply voltage, the
crystal oscillator circuit. Pre-packaged oscillators resistor (REXT) and capacitor (CEXT) values, and the
provide a wide operating range and better stability. A operating temperature. In addition to this, the oscillator
well-designed crystal oscillator will provide good frequency will vary from unit-to-unit due to normal
performance with TTL gates. Two types of crystal process parameter variation. Furthermore, the
oscillator circuits can be used: one with parallel difference in lead frame capacitance between package
resonance, or one with series resonance. types will also affect the oscillation frequency, especially
for low CEXT values. The user also needs to take into
Figure 8-3 shows implementation of a parallel resonant
account variation due to tolerance of external R and C
oscillator circuit. The circuit is designed to use the
components used.
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a Figure 8-5 shows how the R/C combination is
parallel oscillator requires. The 4.7 k resistor provides connected to the PIC12F529T39A device. For REXT
the negative feedback for stability. The 10 k values below 3.0 k, the oscillator operation may
potentiometers bias the 74AS04 in the linear region. become unstable, or stop completely. For very high
This circuit could be used for external oscillator designs. REXT values (e.g., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. It is
FIGURE 8-3: EXTERNAL PARALLEL recommended keeping REXT between 5.0 k and
RESONANT CRYSTAL 100 k.
OSCILLATOR CIRCUIT Although the oscillator will operate with no external
+5V capacitor (CEXT = 0 pF), it is recommended using
To Other values above 20 pF for noise and stability reasons. With
Devices
10k no or small external capacitance, the oscillation
4.7k 74AS04 frequency can vary dramatically due to changes in
CLKIN
external capacitances, such as PCB trace capacitance
74AS04
or package lead frame capacitance. See Figure 12-1
PIC12F529 and Figure 12-2.
10k
XTAL FIGURE 8-5: EXTERNAL RC
OSCILLATOR MODE
10k VDD
20 pF 20 pF REXT
Internal
OSC1 Clock
Figure 8-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental N
frequency of the crystal. The inverter performs a CEXT PIC16F529
180-degree phase shift in a series resonant oscillator VSS
circuit. The 330 resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 8-4: EXTERNAL SERIES

RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To Other
330 330 Devices
74AS04 74AS04 74AS04
CLKIN
0.1 mF
PIC12F529
XTAL

PIC12F529T39A
8.2.5 INTERNAL 4/8 MHz RC For the PIC12F529T39A device, only bits <7:1> of
OSCILLATOR OSCCAL are used for calibration. See Register 4-3 for
more information.
The internal RC oscillator provides a fixed 4/8 MHz
(nominal) system clock at VDD = 3.5V and 25°C, (see Note: The bit 0 of the OSCCAL register is
Section 12.0 “Electrical Characteristics” for unimplemented and should be written as
information on variation over voltage and temperature). ‘0’ when modifying OSCCAL for
In addition, a calibration instruction is programmed into compatibility with future devices.
the last address of memory, which contains the
calibration value for the internal RC oscillator. This 8.3 Reset
location is always non-code-protected, regardless of the
code-protect settings. This value is programmed as a The device differentiates between various kinds of
MOVLW XX instruction where XX is the calibration value, Reset:
and is placed at the Reset vector. This will load the W • Power-on Reset (POR)
register with the calibration value upon Reset and the • MCLR Reset during normal operation
PC will then roll over to the users program at address • MCLR Reset during Sleep
0x000. The user then has the option of writing the value
• WDT Time-out Reset during normal operation
to the OSCCAL register (05h) or ignoring it.
• WDT Time-out Reset during Sleep
OSCCAL, when written to with the calibration value, will
• Wake-up from Sleep on pin change
“trim” the internal oscillator to remove process variation
from the oscillator frequency. Some registers are not reset in any way, and they are
unknown on Power-on Reset (POR) and unchanged in
Note: Erasing the device will also erase the any other Reset. Most other registers are reset to
pre-programmed internal calibration value “Reset state” on Power-on Reset (POR), MCLR, WDT
for the internal oscillator. The calibration or Wake-up on pin change Reset during normal
value must be read prior to erasing the operation. They are not affected by a WDT Reset
part so it can be reprogrammed correctly during Sleep or MCLR Reset during Sleep, since these
later. Resets are viewed as resumption of normal operation.
TABLE 8-3: RESET CONDITIONS FOR REGISTERS

MCLR Reset, WDT Time-out,
Register Address Power-on Reset
Wake-up On Pin Change
W — qqqq qqq0(1) qqqq qqq0(1)

INDF 00h xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu
PCL 02h 1111 1111 1111 1111
STATUS 03h 0001 1xxx q00q quuu(2), (3)
FSR 04h 110x xxxx 11uu uuuu
OSCCAL 05h 1111 111- uuuu uuu-
PORTB 06h --xx xxxx --uu uuuu
OPTION — 1111 1111 1111 1111
TRIS — --11 1111 --11 1111
BSR — ---- -000 ---- -000
EECON 21h ---0 x000 ---0 q000
EEDATA 25h xxxx xxxx uuuu uuuu
EEADR 26h --xx xxxx --uu uuuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory.
2: See Table 8-4 for Reset value for specific conditions.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

PIC12F529T39A
TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
Power-on Reset 0-01 1xxx
MCLR Reset during normal operation 0-0u uuuu
MCLR Reset during Sleep 0-01 0uuu
WDT Reset during Sleep 0-00 0uuu
WDT Reset normal operation 0-00 uuuu
Wake-up from Sleep on pin change 1-01 0uuu
Legend: u = unchanged, x = unknown
8.3.1 MCLR ENABLE The Power-on Reset circuit and the Device Reset Timer
(see Section 8.5 “Device Reset Timer (DRT)”) circuit
This Configuration bit, when unprogrammed (left in the
are closely related. On power-up, the Reset latch is set
‘1’ state), enables the external MCLR function. When
and the DRT is reset. The DRT timer begins counting
programmed, the MCLR function is tied to the internal
once it detects MCLR to be high. After the time-out
VDD and the pin is assigned to be a I/O. See Figure 8-6.
period, which is typically 18 ms or 1 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
FIGURE 8-6: MCLR SELECT
A power-up example where MCLR is held low is shown
in Figure 8-8. VDD is allowed to rise and stabilize before
GPPU
bringing MCLR high. The chip will actually come out of
Reset TDRT after MCLR goes high.
In Figure 8-9, the on-chip Power-on Reset feature is
GP3/MCLR/VPP
being used (MCLR and VDD are tied together or the pin
MCLRE Internal MCLR is programmed to be GP3). The VDD is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 8-10 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
8.4 Power-on Reset (POR) when MCLR and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
The PIC12F529T39A device incorporates an on-chip
out, VDD has not reached the VDD (min) value and the
Power-on Reset (POR) circuitry, which provides an
chip may not function correctly. For such situations, we
internal chip Reset for most power-up situations.
recommend that external RC circuits be used to
The on-chip POR circuit holds the chip in Reset until achieve longer POR delay times (Figure 8-9).
VDD has reached a high enough level for proper
operation. To take advantage of the internal POR, Note: When the devices start normal operation
program the GP3/MCLR/VPP pin as MCLR and tie (exit the Reset condition), device
through a resistor to VDD, or program the pin as GP3, in operating parameters (voltage, frequency,
which case, an internal weak pull-up resistor is temperature, etc.) must be met to ensure
implemented using a transistor (refer to Table 12-4 for operation. If these conditions are not met,
the pull-up resistor ranges). This will eliminate external the device must be held in Reset until the
RC components usually needed to create a Power-on operating conditions are met.
Reset. A maximum rise time for VDD is specified. See For additional information, refer to Application Note
Section 12.0 “Electrical Characteristics” for details. AN522, “Power-Up Considerations” (DS00522).
When the devices start normal operation (exit the Reset
condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-7.

PIC12F529T39A
FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect POR (Power-on Reset)
GP3/MCLR/VPP
MCLR Reset
S Q
MCLRE
Start-up Timer R Q
WDT Reset
WDT Time-out (10 s, 1 ms CHIP Reset
or 18 ms)
Pin Change
Sleep Wake-up on pin Change Reset
FIGURE 8-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset

PIC12F529T39A
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
Internal POR TDRT
DRT Time-out
Internal Reset
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1  VDD min.

PIC12F529T39A
8.5 Device Reset Timer (DRT) 8.6 Watchdog Timer (WDT)
On the PIC12F529T39A device, the DRT runs any time The Watchdog Timer (WDT) is a free running on-chip
the device is powered up. DRT runs from Reset and RC oscillator, which does not require any external
varies based on oscillator selection and Reset type (see components. This RC oscillator is separate from the
Table 8-5). external RC oscillator of the (GP5)/OSC1/CLKIN pin
The DRT operates on an internal RC oscillator. The and the internal 4 or 8 MHz oscillator. This means that
processor is kept in Reset as long as the DRT is active. the WDT will run even if the main processor clock has
The DRT delay allows VDD to rise above VDD min. and been stopped, for example, by execution of a SLEEP
for the oscillator to stabilize. instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to The TO bit (STATUS<4>) will be cleared upon a
establish a stable oscillation. The on-chip DRT keeps Watchdog Timer Reset.
the devices in a Reset condition after MCLR has The WDT can be permanently disabled by
reached a logic high (VIH MCLR) level. Programming programming the configuration WDTE as a ‘0’ (see
GP3/MCLR/VPP as MCLR and using an external RC Section 8.1 “Configuration Bits”). Refer to the
network connected to the MCLR input is not required in PIC12F529T39A Programming Specification
most cases. This allows savings in cost-sensitive and/or (DS41316) to determine how to access the
space restricted applications, as well as allowing the Configuration Word.
use of the GP3/MCLR/VPP pin as a general purpose
input. 8.6.1 WDT PERIOD
The Device Reset Time delays will vary from The WDT has a nominal time-out period of 18 ms, (with
chip-to-chip due to VDD, temperature and process no prescaler). If a longer time-out period is desired, a
variation. See AC parameters for details. prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writing
The DRT will also be triggered upon a Watchdog Timer
to the OPTION register. Thus, a time-out period of a
time-out from Sleep. This is particularly important for
nominal 2.3 seconds can be realized. These periods
applications using the WDT to wake from Sleep mode
vary with temperature, VDD and part-to-part process
automatically.
variations (see DC specs).
Reset sources are POR, MCLR, WDT time-out and
Under worst-case conditions (VDD = Min., Temperature
wake-up on pin change. See Section 8.8.2 “Wake-up
= Max., max. WDT prescaler), it may take several
from Sleep”, Notes 1, 2 and 3.
seconds before a WDT time-out occurs.
TABLE 8-5: DRT (DEVICE RESET TIMER 8.6.2 WDT PROGRAMMING
PERIOD) CONSIDERATIONS
Oscillator Subsequent The CLRWDT instruction clears the WDT and the
POR Reset
Configuration Resets postscaler, if assigned to the WDT, and prevents it from
INTOSC, EXTRC 1 ms (typical) 10 s (typical) timing out and generating a device Reset.
LP, XT 18 ms (typical) 18 ms (typical) The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.

PIC12F529T39A
FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source

(Figure 7-1)
0
M Postscaler
Watchdog 1 U
Time X
8-to-1 MUX PS<2:0>

PSA
WDT Enable
Configuration To Timer0 (Figure 7-3)
Bit
0 1
MUX
PSA
WDT Time-out
Note 1: PSA, PS<2:0> are bits in the OPTION register.
TABLE 8-6: SUMMARY OF REGISTER ASSOCIATED WITH THE WATCHDOG TIMER

Register on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Page
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 14

Legend: Shaded boxes = Not used by Watchdog Timer.

PIC12F529T39A
8.7 Time-out Sequence, Power-down 8.8.2 WAKE-UP FROM SLEEP
and Wake-up from Sleep Status The device can wake-up from Sleep through one of the
Bits (TO, PD, GPWUF) following events:
The TO, PD and (GPWUF) bits in the STATUS register 5. An external Reset input on GP3/MCLR/VPP pin,
can be tested to determine if a Reset condition has when configured as MCLR.
been caused by a power-up condition, a MCLR or 6. A Watchdog Timer Time-out Reset (if WDT was
Watchdog Timer (WDT) Reset. enabled).
7. A change on input pin GP0, GP1 and GP3 when
TABLE 8-7: TO/PD/(GPWUF) STATUS wake-up on change is enabled.
AFTER RESET These events cause a device Reset. The TO, PD and
GPWUF TO PD Reset Caused By GPWUF bits can be used to determine the cause of
device Reset. The TO bit is cleared if a WDT time-out
0 0 0 WDT wake-up from Sleep occurred (and caused wake-up). The PD bit, which is
0 0 u WDT time-out (not from set on power-up, is cleared when SLEEP is invoked.
Sleep) The GPWUF bit indicates a change in state while in
0 1 0 MCLR wake-up from Sleep Sleep at pins GP0, GP1 and GP3 (since the last file or
bit operation on GPIO port).
0 1 1 Power-up
0 u u MCLR not during Sleep Note: Caution: Right before entering Sleep,
read the input pins. When in Sleep,
1 1 0 Wake-up from Sleep on pin
wake-up occurs when the values at the
change
pins change from the state they were in at
Legend: u = unchanged the last reading. If a wake-up on change
Note 1: The TO, PD and GPWUF bits maintain occurs and the pins are not read before
their status (u) until a Reset occurs. A re-entering Sleep, a wake-up will occur
low-pulse on the MCLR input does not immediately even if no pins change while
change the TO, PD and GPWUF Status in Sleep mode.
bits.
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
8.8 Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
8.8.1 SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
Note: A Reset generated by a WDT time-out
does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
GP3/MCLR/VPP pin must be at a logic high level if
MCLR is enabled.

PIC12F529T39A
8.9 Program Verification/Code 8.11 In-Circuit Serial Programming™
Protection The PIC12F529T39A device can be serially
Code protection is enabled or disabled by writing the programmed while in the end application circuit. This is
correct value to the CP<3:0> bits of the Configuration simply done with two lines for clock and data, and three
register. These bits must be written every time the other lines for power, ground and the programming
device is erased. voltage. This allows users to manufacture boards with
unprogrammed PIC12F519 device and then program
If the code protection bits have not been enabled, the the PIC12F519 device just before shipping the product.
on-chip program and data memory can be read out for This also allows the most recent firmware, or a custom
verification purposes. firmware, to be programmed.
The last location (the oscillator calibration value) can The PIC12F529T39A device is placed into a
be read, regardless of the setting of the program Program/Verify mode by holding the GP1 and GP0 pins
memory's code protection bit. If the code-protect bit low while raising the MCLR (VPP) pin from VIL to VIHH
specific to the Flash data memory is programmed, (see programming specification). The GP1 pin
then none of the contents of this memory region can becomes the programming clock, and the GP0 pin
be verified externally. becomes the programming data. Both GP1 and GP0
Refer to PIC12F529T48A/T39A Memory Programming pins are Schmitt Trigger inputs in this mode.
Specification (DS41619) for more information on After Reset, a 6-bit command is then supplied to the
programming the Configuration Word. device. Depending on the command, 14 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
Note: The device code protection must be details of serial programming, please refer to the
disabled before attempting to program “PIC12F529T48A/T39A Memory Programming
Flash memory. Specification,” (DS41619).
A typical In-Circuit Serial Programming connection is
8.10 ID Locations shown in Figure 8-12.
Four memory locations are designated as ID locations
where users can store checksum or other code FIGURE 8-12: TYPICAL IN-CIRCUIT
identification numbers. These locations are not SERIAL PROGRAMMING
accessible during normal execution, but are readable CONNECTION
and writable during program/verify.
Use only the lower four bits of the ID locations. The To Normal
upper bits should be programmed as ‘0’s. External Connections
Connector PIC12F529
Signals
VDD VDD
VSS VSS
VPP MCLR/VPP
CLK GP1/ICSPCLK
Data GP0/ICSPDAT
VDD
To Normal
Connections

PIC12F529T39A
9.0 RF TRANSMITTER
The RF transmitter is an ultra low-power, integrated
multi-band Sub-GHz transmitter. It is capable of
operating in the 310, 433, 868, and 915 MHz
license-free frequency bands using Frequency Shift
Keying (FSK) or On-Off Keying (OOK) modulation of an
input data stream.
9.1 Circuit Description

The RF transmitter block diagram is shown in
Figure 9-1 and the I/O pin definitions are shown in
Table 9-1.
FIGURE 9-1: RF TRANSMITTER BLOCK DIAGRAM
DATA PA RFOUT
CP VDDRF
VSSRF
PFD
XTAL M/N
Sigma/
Delta
CTRL Control Logic

PIC12F529T39A
TABLE 9-1: RF TRANSMITTER PIN DESCRIPTION

Name Function Input Type Output Type Description
VDDRF VDDRF Power — RF Power Supply
CTRL CTRL CMOS — Configuration Selection and Configuration Clock
RFOUT RFOUT — RF Transmitter RF output
VSSRF VSSRF Power — RF Power Supply
DATA DATA CMOS CMOS Configuration Data and Transmit Data
XTAL XTAL XTAL — Crystal Oscillator
FIGURE 9-2: MODE SELECTION
TIMING DIAGRAM
Note: The RF transmitter pins are independent
from the microcontroller pins. tSTART
The RF transmitter contains of a sigma-delta

fractional-N Phase-Locked Loop (PLL) frequency VDDRF
synthesizer. Frequency Shift Keying (FSK) modulation
is made inside the PLL bandwidth. On-Off Keying
(OOK) modulation is made by turning on and off the
CTRL
Power Amplifier (PA).
The reference frequency is generated by an internal
crystal oscillator. An external quartz crystal resonator is
connected to the XTAL pin and Ground (VSSRF). The CTRL pin Sampled
choice of crystal frequency depends on the frequency
band of choice.
If the POR settings are satisfactory for the application,
The RF transmitter can deliver 0 dBm or +10 dBm into a microcontroller output pin can be freed by placing a
a 50Ω load via the RFOUT pin. An external matching weak pull-up or pull-down resistor on the CTRL pin.
network is required for each power setting and Only the DATA pin needs to be connected to an I/O pin.
frequency band for the best efficiency to the antenna.
9.2.2 RF TRANSMITTER REGISTERS
9.2 Configuring the RF Transmitter RF transmitter has three registers: Application,
The CTRL and DATA pins are used to configure the RF Frequency, and Status. These are used to write and
transmitter for transmit frequency, output power, read configuration parameters related to transmit
modulation, FSK frequency deviation, and sleep time. frequency, output power, modulation, FSK frequency
Once configured, the DATA pin is used to encode deviation, and Sleep time. A summary of register
transmit data. values are shown in Table 9-2. A detailed explanation
of Application register is shown in Table 9-3, Frequency
9.2.1 POWER-ON RESET (POR) register values in Table 9-4, and STATUS register in
Table 9-5.
At power-on, the CTRL pin is sampled as shown in
Figure 9-2 and depending on the CTRL pin logic level, To access the registers, the DATA line is sampled at
the RF transmitter will enter one of two Power-on Reset each low-to-high transition on the CTRL pin. A total of
(POR) values as shown in Table 9-3 and Table 9-4. To 24 transitions are required on the CTRL pin to
continue using the RF transmitter with these POR successfully write or read a value in the registers.
values, maintain the CTRL pin stable and at the Register write and read operations are shown in
powered-on logic level. With the DATA pin at logic ‘0’, Figure 9-3.
the RF transmitter will enter Sleep mode. Writing and reading the RF transmitter registers should
be done when the device is in Sleep mode. See
Section 9.2.4 “Sleep Mode”.
Note: It is recommended that a weak pull-up or
pull-down resistor be placed on the CTRL
pin to ensure the desired preset mode is
selected at power-on.

PIC12F529T39A
In the event that spurious activity (for example MCU DATA pins can be used to recover serial
interrupt or Reset) or less than 24 clock cycles on the communications with the RF transmitter. The recover
CTRL pin, a special sequence over the CTRL and sequence is shown in Figure 9-4.
FIGURE 9-3: REGISTER WRITE AND READ OPERATIONS
CTRL
DATA
23 22 21 20 19 18 17 16 15 ... 3 2 1 0
Write Operation
DATA pin transition DATA pin transition

from write to read from read to write
CTRL
DATA
23 22 21 20 19 18 17 16 15 ... 3 2 1 0
Write Read
Read Operation
Note 1: Refer to Section 12.1 “RF Transmitter Electrical Specifications”.

2: Exactly 24 clock cycles are required for proper configuration.
FIGURE 9-4: RECOVERY SEQUENCE TIMING

t1 t0
CTRL
DATA
23 22 21 20 19 18 17 16 15 ... 3 2 1 0

PIC12F529T39A
TABLE 9-2: RF TRANSMITTER REGISTER SUMMARY

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction
0 0 0 0 0 0 0 0 DA<15:0> Write Application
0 0 1 1 0 0 1 1 DA<15:0> Read Register
(see Table 9-3)
0 0 0 1 1 DF<18:0> Write Frequency
0 1 0 0 0 1 0 0 DF<15:0> Read Register
(see Table 9-4)
0 1 0 1 0 1 0 1 DV<7:0> DS<4:0> DF<18:16> Read STATUS
Register (see
Table 9-5)
TABLE 9-3: APPLICATION REGISTER

Power-on Reset
Bit Name Value Setting Notes
CTRL = 0 CTRL = 1
DA15 Mode 0 Automatic 0 0 Refer to Section 9.2.5 “Manual
1 Manual Transmit Mode”.
DA14 Modulation 0 FSK 0 1 Refer to Section 9.3 “Modulation
1 OOK Selection”.
DA13 Band 0 310-450 MHz 1 0 Refer to Section 9.4 “Frequency
1 860-870 MHz Selection and Configuration”.
902-928 MHz
DA<12:5> Frequency — — — 0x06(1) FSK mode only. Refer to
Deviation (fDEV) Section 9.4.3 “Frequency Calcu-
lation”.
DA4 Output Power 0 0 dBm 1 1 —
1 10 dBm
DA3 Transmitter Off 0 2 ms 1 0 —
Time (tOFFT) 1 20 ms
DA<2:0> Reserved 100(2) — 100 100 —
Note 1: Actual frequency deviation value dependant on crystal frequency.
2: When writing to the Application register, DA<2:0> must be 0b100.
TABLE 9-4: FREQUENCY REGISTER

Power-on Reset
CTRL = 0 CTRL = 1
DF<18:0> Transmit — — 0x42C1C(1) 0x42CAD(1) Refer to Section 9.4 “Frequency
Frequency Selection and Configuration”. When
(fTX) reading frequency, the Most Significant
3 bits are read from the STATUS
register (see Table 9-5)
Note 1: Actual frequency value dependant on crystal frequency.

PIC12F529T39A
9.2.3 DATA TRANSMISSION
TABLE 9-5: STATUS REGISTER
Power-on Reset
CTRL = 0 CTRL = 1
DV<7:0> Chip Version 0x11 — 0x11 0x11 0x11 = Version A1
DS<4:2> Reserved — — — — —
DS1 TX Ready 0 Sleep — —
1 Transmitting — —
DS0 Reserved — — — —
DF<18:16> Transmit Frequency (fTX) — — 0b100 0b100 Refer to Section 9.4
“Frequency Selec-
tion and Configura-
tion”. When reading
frequency, the Most
Significant 3 bits are
read from the STATUS
register (see Table 9-5)
RF data is transmitted when the DATA pin is at a logic
‘1’ for greater than tWAKE as shown in Figure 9-5. The
CTRL pin must remain stable (either logic ‘0’ or ‘1’). If
the modulation mode is OOK, the transmitted signal is
turned on and off by the DATA pin. If the modulation
mode is FSK, the transmitted signal is frequency
shifted by the DATA pin. The encoding of the
transmitted signal is determined by the length of time
the DATA pin is held logic ‘0’ or ‘1’.

PIC12F529T39A
9.2.4 SLEEP MODE
The RF transmitter will automatically enter Sleep mode
when the DATA pin is a logic ‘0’ for greater than tOFFT,
as shown in Figure 9-5. tOFFT can be configured for 2
or 20 ms in the Application register (see Table 9-3).
FIGURE 9-5: DATA PIN TRANSMIT TIMING DIAGRAM
tWAKE tOFFT
DATA
CTRL(1)
RFOUT (OOK)
RFOUT (FSK)
Sleep Wake Sleep
Note 1: The CTRL pin must remain stable (logic ‘0’ or ‘1’).

PIC12F529T39A
9.2.5 MANUAL TRANSMIT MODE
The RF transmitter can continuously transmit by setting
the mode bit (DA15) to a logic ‘1’ in the Applications
register (see Table 9-3). It will continuously transmit RF
data presented on the DATA pin without automatically
entering Sleep mode. To cease transmission the mode
bit is must be cleared (DA15 = 0). Figure 9-6 shows the
Manual Transmit mode timing.
FIGURE 9-6: MANUAL TRANSMIT MODE TIMING
DA15 = 1 DA15 = 0
CTRL
DATA
tWAKE tRAMP
RFOUT (OOK)
RFOUT (FSK)
Sleep Wake Sleep
9.3 Modulation Selection 9.3.3 DIGITAL TRANSMISSION SYSTEM

(DTS)
9.3.1 ON-OFF KEYING (OOK)
In the United States and Canada, digital modulation
OOK modulation can be configured by setting the techniques are permitted (FCC Part 15.247 and
modulation DA14 bit in the Application register RSS-210, respectively). The RF transmitter can be
(Table 9-3). Data is transmitted as stated in configured for DTS mode by selecting FSK and fDEV =
Section 9.2.3 “Data Transmission”. 200 kHz. Data encoding techniques, such as data whit-
ening, may be needed to ensure that the minimum 6 dB
9.3.2 FREQUENCY SHIFT KEYING (FSK) bandwidth is at least 500 kHz.
FSK modulation can be configured by clearing the
modulation DA14 bit in the Application register.
Frequency Deviation (fDEV) is configured by setting the
DA<12:5> bits in the Application register. Data is
transmitted as stated in Section 9.2.3 “Data
Transmission”.

PIC12F529T39A
9.4 Frequency Selection and 9.4.1 BAND SELECTION
Configuration The Band bit, DA13, in the Application register
configures the RF transmitter for a range of frequencies
The RF transmitter is capable of generating many of
for a given crystal frequency as shown in Table 9-6.
the popular RF frequencies that are permitted within
the radio regulations of the country the finished product
will be sold. The RF frequency configuration is
performed by determining which frequency band,
selecting the crystal frequency, and setting the
frequency value in the Frequency register DF<18:0>. If
FSK modulation is used, the frequency deviation is set
in the Application register DA<12:5>. See
Section 9.2.2 “RF Transmitter Registers” for
information on Configuration register settings.
TABLE 9-6: FREQUENCY BAND SELECTION
Band Setting DA<13> Frequency Band (fRF) Crystal Frequency (fXTAL)
0 310 -450 MHz 22 MHz
312 -450 MHz 24 MHz
338-450 MHz 26 MHz
1 863-870 MHz
22 MHz
902-924 MHz
863-870 MHz 24 MHz
902-928 MHz 26 MHz
9.4.2 CRYSTAL SELECTION

Once the frequency band has been selected, the
choice of crystal frequency is flexible provided the
crystal meets the specifications summarized in
Table 9-7, the boundaries of the Frequency register
DF<18:0> are followed as shown in Figure 9-7, and RF
transmit frequency error is acceptable (see
Section 9.4.3 “Frequency Calculation”).
TABLE 9-7: CRYSTAL RESONATOR SPECIFICATIONS
Symbol Description Min. Typ. Max. Unit
FXTAL Crystal Frequency 22 — 26 MHz
CL Load Capacitance — 15 — pF
ESR Equivalent Series Resistance — — 100 Ohms
The crystal frequency tolerance and frequency stability 9.4.3 FREQUENCY CALCULATION
over the operating temperature range depends on the
Once the frequency band and crystal frequency are
system frequency budget. Typically, the receiver crystal
selected, the RF transmit signal (fRF) is calculated by
frequency tolerance, stability, and receiver bandwidth
setting the Frequency register DF(18:0) bits according
will have the greatest influence. For OOK modulation,
to the formula shown in Figure 9-7. If the calculated
the transmitted RF signal (fRF) should remain inside the
value for DF(18:0) is not an integer, there will be an
receiver bandwidth, otherwise signal degradation will
associated transmit frequency error. Ensure that this
occur. For FSK modulation, fRF should remain inside
error is within the acceptable system frequency budget.
the receiver bandwidth and within 0.5 * fDEV.
Similarly, the frequency deviation is calculated as
As a general practice, do not choose a RF transmit shown in Figure 9-7.
signal (fRF) with an integer or near integer multiple of
fXTAL. This will result in higher noise and spurious
emissions.

PIC12F529T39A
FIGURE 9-7: FREQUENCY CALCULATION
Band 0 Band 1
fRF * 16384 fRF * 8192

DF(18:0) = DF(18:0) =
fXTAL fXTAL
212992 < DF(18:0) < 344064 212992 < DF(18:0) < 344064
Note: Check fRF frequency Note: Check fRF frequency

error by calculating fRF with error by calculating fRF with
integer value of DF(18:0). integer value of DF(18:0).
fDEV * 16384 fDEV * 8192

DA(12:5) = DA(12:5) =
fXTAL fXTAL
10 kHz fDEV 200 kHz 10 kHz fDEV 200 kHz
Note: Check fDEV frequency Note: Check fDEV frequency

error by calculating fDEV with error by calculating fDEV with
integer value of DA(12:5). integer value of DA(12:5).
fRF and fXTAL values in the range shown in Table 9-6

PIC12F529T39A
9.5 Applications
9.5.1 SOFTWARE INITIALIZATION
EXAMPLE 9-1: SAMPLE INITIALIZATION CODE

#define APP_REG_PREFIX 0
#define FREQ_REG_PREFIX 0x18
void sendTxCommand(unsigned char cmd)

{
// The ‘T39A samples data on the rising edge of clock. Clock is idle low.
unsigned char i;
for (i=0; i<8; i++)
{
if (cmd & 0x80)
DATA_OUT = 1;
else
DATA_OUT = 0;
CTRL_OUT = 1;
NOP();
NOP();
CTRL_OUT = 0;
cmd = cmd << 1;
}
}
void TX_Init(void)
{
unsigned char app_high = (T39A_APP_CONFIG & 0x00FF00) >> 8;
unsigned char app_low = (T39A_APP_CONFIG & 0x0000FF);
unsigned char f_upper = (T39A_FREQ_CONFIG & 0x70000) >> 16;

unsigned char f_high = (T39A_FREQ_CONFIG & 0x0FF00) >> 8;
unsigned char f_low = (T39A_FREQ_CONFIG & 0x000FF);
sendTxCommand(APP_REG_PREFIX);
sendTxCommand(app_high);
sendTxCommand(app_low);
sendTxCommand(FREQ_REG_PREFIX | f_upper);
sendTxCommand(f_high);
sendTxCommand(f_low);
return;
}
9.5.2 APPLICATION CIRCUIT

Figure 9-8 describes a sample four-button remote
transmitter application schematic. Table 9-8 contains
its bill of materials. This schematic and bill of materials
is a design suggestion only. Actual component values
will be dependent on implementation parameters.

PIC12F529T39A
APPLICATION SCHEMATIC
FIGURE 9-8:
PIC12F529T39A
TABLE 9-8: BILL OF MATERIALS

Designator Value Description
U1 PIC12F529T39A Microcontroller with integrated UHF transmitter
C6, C7 0.1 µF Decoupling
R6 470  Current limiting
Common
DS1 RED LED

R3 10 k Weak pull-down for RF configuration
R4 100 
R1, R5 47 k Voltage divider
C4 1000 pF
L5 120 nH
C5 100 pF
C3, L1, L3 0
434 MHz
L4 39 nH
Matching to 50 
C2 6.8 pF
L2 2.2 nH
X1 24 MHz
L5 12 nH
C5 1 pF
C3, L4 DNP
868 MHz
L3 27 nH Matching to 50 
C2 2.7 pF
L1, L2 0
X1 26 MHz
L5 8.2 nH
L1, L4, C2 0
C5 4.7 pF
915 MHz
C3 1.2 pF Matching to 50 
L3 2.4 nH
L2 10 nH
X1 26 MHz

PIC12F529T39A
10.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
The PIC12F529T39A instruction set is highly counter is changed as a result of an instruction. In this
orthogonal and is comprised of three basic categories. case, the execution takes two instruction cycles. One
• Byte-oriented operations instruction cycle consists of four oscillator periods.
• Bit-oriented operations Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
• Literal and control operations
true or the program counter is changed as a result of an
Each PIC12F529T39A instruction is a 12-bit word instruction, the instruction execution time is 2 s.
divided into an opcode, which specifies the instruction
Figure 10-1 shows the three general formats that the
type, and one or more operands which further specify
instructions can have. All examples in the figure use
the operation of the instruction. The formats for each of
the following format to represent a hexadecimal
the categories is presented in Figure 10-1, while the
number:
various opcode fields are summarized in Table 10-1.
0xhhh
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination where ‘h’ signifies a hexadecimal digit.
designator. The file register designator specifies which
file register is to be used by the instruction. FIGURE 10-1: GENERAL FORMAT FOR
The destination designator specifies where the result of INSTRUCTIONS
the operation is to be placed. If ‘d’ is ‘0’, the result is Byte-oriented file register operations
placed in the W register. If ‘d’ is ‘1’, the result is placed 11 6 5 4 0
in the file register specified in the instruction. OPCODE d f (FILE #)
For bit-oriented instructions, ‘b’ represents a bit field
d = 0 for destination W
designator which selects the number of the bit affected d = 1 for destination f
by the operation, while ‘f’ represents the number of the f = 5-bit file register address
file in which the bit is located. Bit-oriented file register operations
For literal and control operations, ‘k’ represents an 11 8 7 5 4 0
8 or 9-bit constant or literal value. OPCODE b (BIT #) f (FILE #)
TABLE 10-1: OPCODE FIELD b = 3-bit bit address

f = 5-bit file register address
DESCRIPTIONS
Field Description Literal and control operations (except GOTO)
f Register file address (0x00 to 0x7F) 11 8 7 0
W Working register (accumulator) OPCODE k (literal)
b Bit address within an 8-bit file register
k = 8-bit immediate value
k Literal field, constant data or label
x Don’t care location (= 0 or 1) Literal and control operations – GOTO instruction
The assembler will generate code with x = 0. It is 11 9 8 0
the recommended form of use for compatibility with
all Microchip software tools.
OPCODE k (literal)
d Destination select; k = 9-bit immediate value
d = 0 (store result in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label Label name
TOS Top-of-Stack
PC Program Counter
WDT Watchdog Timer counter
TO Time-out bit
PD Power-down bit
dest Destination, either the W register or the specified
register file location
[ ] Options
( ) Contents
 Assigned to
< > Register bit field
 In the set of
italics User defined term (font is courier)

PIC12F529T39A
TABLE 10-2: INSTRUCTION SET SUMMARY
Mnemonic, 12-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
ADDWF f, d Add W and f 1 0001 11df ffff C, DC, Z 1, 2, 4

ANDWF f, d AND W with f 1 0001 01df ffff Z 2, 4
CLRF f Clear f 1 0000 011f ffff Z 4
CLRW – Clear W 1 0000 0100 0000 Z
COMF f, d Complement f 1 0010 01df ffff Z
DECF f, d Decrement f 1 0000 11df ffff Z 2, 4
DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2, 4
INCF f, d Increment f 1 0010 10df ffff Z 2, 4
INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2, 4
IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2, 4
MOVF f, d Move f 1 0010 00df ffff Z 2, 4
MOVWF f Move W to f 1 0000 001f ffff None 1, 4
NOP – No Operation 1 0000 0000 0000 None
RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2, 4
RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2, 4
SUBWF f, d Subtract W from f 1 0000 10df ffff C, DC, Z 1, 2, 4
SWAPF f, d Swap f 1 0011 10df ffff None 2, 4
XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 0100 bbbf ffff None 2, 4
BSF f, b Bit Set f 1 0101 bbbf ffff None 2, 4
BTFSC f, b Bit Test f, Skip if Clear 1(2) 0110 bbbf ffff None
BTFSS f, b Bit Test f, Skip if Set 1(2) 0111 bbbf ffff None
LITERAL AND CONTROL OPERATIONS
ANDLW k AND literal with W 1 1110 kkkk kkkk Z
CALL k Call Subroutine 2 1001 kkkk kkkk None 1
CLRWDT – Clear Watchdog Timer 1 0000 0000 0100 TO, PD
GOTO k Unconditional branch 2 101k kkkk kkkk None
IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk Z
MOVLW k Move literal to W 1 1100 kkkk kkkk None
MOVLB k Move literal to BSR 1 0000 0001 0kkk None
OPTION – Load OPTION register 1 0000 0000 0010 None
RETLW k Return, place literal in W 2 1000 kkkk kkkk None
SLEEP – Go into Standby mode 1 0000 0000 0011 TO, PD 3
TRIS f Load TRISGPIO register 1 0000 0000 0fff None
XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Z
Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.6 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of GPIO. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).

PIC12F529T39A
ADDWF Add W and f BCF Bit Clear f

Syntax: [ label ] ADDWF f,d Syntax: [ label ] BCF f,b
Operands: 0  f  31 Operands: 0  f  31
d 01 0b7
Operation: (W) + (f)  (dest) Operation: 0  (f<b>)
Status C, DC, Z Status Affected: None
Affected: Description: Bit ‘b’ in register ‘f’ is cleared.
Description: Add the contents of the W register
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
BSF Bit Set f

ANDLW AND literal with W
Syntax: [ label ] BSF f,b
Syntax: [ label ] ANDLW k Operands: 0  f  31
Operands: 0  k  255 0b7
Operation: (W).AND. (k)  (W) Operation: 1  (f<b>)
Status Affected: Z Status Affected: None
Description: The contents of the W register are Description: Bit ‘b’ in register ‘f’ is set.
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
ANDWF AND W with f BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b

d [0,1] 0b7
Operation: (W) .AND. (f)  (dest) Operation: skip if (f<b>) = 0
Status Affected: Z Status Affected: None
Description: The contents of the W register are Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
AND’ed with register ‘f’. If ‘d’ is ‘0’, next instruction is skipped.
the result is stored in the W register. If bit ‘b’ is ‘0’, then the next instruc-
If ‘d’ is ‘1’, the result is stored back tion fetched during the current
in register ‘f’. instruction execution is discarded,
and a NOP is executed instead,
making this a 2-cycle instruction.

PIC12F529T39A
BTFSS Bit Test f, Skip if Set CLRW Clear W
Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW
Operands: 0  f  31 Operands: None

0b<7 Operation: 00h  (W);
Operation: skip if (f<b>) = 1 1Z
Status Affected: None Status Affected: Z
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the Description: The W register is cleared. Zero bit
next instruction is skipped. (Z) is set.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a 2-cycle instruction.
CALL Subroutine Call CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0  k  255 Operands: None
Operation: (PC) + 1 Top-of-Stack; Operation: 00h  WDT;
k  PC<7:0>; 0  WDT prescaler (if assigned);
(STATUS<6:5>)  PC<10:9>; 1  TO;
0  PC<8> 1  PD
Status Affected: None Status Affected: TO, PD
Description: Subroutine call. First, return Description: The CLRWDT instruction resets the
address (PC + 1) is pushed onto WDT. It also resets the prescaler, if
the stack. The 8-bit immediate the prescaler is assigned to the
address is loaded into PC WDT and not Timer0. Status bits
bits <7:0>. The upper bits TO and PD are set.
PC<10:9> are loaded from
STATUS<6:5>, PC<8> is cleared.
CALL is a 2-cycle instruction.
CLRF Clear f COMF Complement f

Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d
Operation: 00h  (f); d  [0,1]
1Z Operation: (f)  (dest)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
cleared and the Z bit is set. complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.

PIC12F529T39A
DECF Decrement f INCF Increment f

Syntax: [ label ] DECF f,d Syntax: [ label ] INCF f,d
d  [0,1] d  [0,1]
Operation: (f) – 1  (dest) Operation: (f) + 1  (dest)
Status Affected: Z Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are
the result is stored in the W incremented. If ‘d’ is ‘0’, the result
register. If ‘d’ is ‘1’, the result is is placed in the W register. If ‘d’ is
stored back in register ‘f’. ‘1’, the result is placed back in
register ‘f’.
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d  [0,1] d  [0,1]
Operation: (f) – 1  d; skip if result = 0 Operation: (f) + 1  (dest), skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.
If the result is ‘0’, the next instruc- If the result is ‘0’, then the next
tion, which is already fetched, is instruction, which is already
discarded and a NOP is executed fetched, is discarded and a NOP is
instead making it a 2-cycle instruc- executed instead making it a
tion. 2-cycle instruction.
GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  511 Operands: 0  k  255
Operation: k  PC<8:0>; Operation: (W) .OR. (k)  (W)
STATUS<6:5>  PC<10:9> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. OR’ed with the 8-bit literal ‘k’. The
The 9-bit immediate value is result is placed in the W register.
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTO is a 2-cycle
instruction.

PIC12F529T39A
IORWF Inclusive OR W with f MOVWF Move W to f

Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f
d  [0,1] Operation: (W)  (f)
Operation: (W).OR. (f)  (dest) Status Affected: None
Status Affected: Z Description: Move data from the W register to
Description: Inclusive OR the W register with register ‘f’.
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
MOVF Move f NOP No Operation

Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP
Operands: 0  f  31 Operands: None
d  [0,1] Operation: No operation
Operation: (f)  (dest) Status Affected: None
Status Affected: Z Description: No operation.
Description: The contents of register ‘f’ are
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file
register ‘f’. ‘d’ = 1 is useful as a
test of a file register, since status
flag Z is affected.
MOVLB Move literal to BSR OPTION Load OPTION Register

Syntax: [ label ] Option
Syntax: [ label ] MOVLB k
Operands: None
Operands: 0k7
Operation: (W)  Option
Operation: k  BSR
Status Affected: None
Description: The content of the W register is
Description: The 3-bit literal ‘k’ is loaded into loaded into the OPTION register.
the Bank Select Register (BSR).
The “don’t cares” will be assem-
bled at ‘0’.
MOVLW Move Literal to W

Syntax: [ label ] MOVLW k
Operands: 0  k  255
Operation: k  (W)
Description: The 8-bit literal ‘k’ is loaded into
the W register. The “don’t cares”
will assembled as ‘0’s.

PIC12F529T39A
RETLW Return with Literal in W SLEEP Enter SLEEP Mode

Syntax: [ label ] RETLW k Syntax: [label ] SLEEP
Operands: 0  k  255 Operands: None
Operation: k  (W); Operation: 00h  WDT;
TOS  PC 0  WDT prescaler;
Status Affected: None 1  TO;
0  PD
Description: The W register is loaded with the
8-bit literal ‘k’. The program Status Affected: TO, PD, GPWUF
counter is loaded from the top of Description: Time-out Status bit (TO) is set.
the stack (the return address). This The Power-down Status bit (PD) is
is a 2-cycle instruction. cleared.
GPWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See Section 8.8 “Power-down
Mode (Sleep)” on Sleep for more
details.
RLF Rotate Left f through Carry SUBWF Subtract W from f

Syntax: [ label ] RLF f,d Syntax: [label ] SUBWF f,d
Operands: 0  f  31 Operands: 0 f 31
d  [0,1] d  [0,1]
Operation: See description below Operation: (f) – (W) dest)
Status Affected: C Status Affected: C, DC, Z
Description: The contents of register ‘f’ are Description: Subtract (two’s complement
rotated one bit to the left through method) the W register from regis-
the Carry flag. If ‘d’ is ‘0’, the result ter ‘f’. If ‘d’ is ‘0’, the result is stored
is placed in the W register. If ‘d’ is in the W register. If ‘d’ is ‘1’, the
‘1’, the result is stored back in reg- result is stored back in register ‘f’.
ister ‘f’.
C register ‘f’
RRF Rotate Right f through Carry SWAPF Swap Nibbles in f

Syntax: [ label ] RRF f,d Syntax: [ label ] SWAPF f,d
d  [0,1] d  [0,1]
Operation: See description below Operation: (f<3:0>)  (dest<7:4>);
Status Affected: C (f<7:4>)  (dest<3:0>)
Description: The contents of register ‘f’ are Status Affected: None

rotated one bit to the right through Description: The upper and lower nibbles of
the Carry flag. If ‘d’ is ‘0’, the result register ‘f’ are exchanged. If ‘d’ is
is placed in the W register. If ‘d’ is ‘0’, the result is placed in W
‘1’, the result is placed back in register. If ‘d’ is ‘1’, the result is
register ‘f’. placed in register ‘f’.
C register ‘f’

PIC12F529T39A
TRIS Load TRIS Register XORWF Exclusive OR W with f

Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d
Operands: f=6 Operands: 0  f  31
Operation: (W)  TRIS register f d  [0,1]
Status Affected: None Operation: (W) .XOR. (f) dest)
Description: TRIS register ‘f’ (f = 6 or 7) is Status Affected: Z
loaded with the contents of the W
Description: Exclusive OR the contents of the
register.
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
XORLW Exclusive OR literal with W stored back in register ‘f’.
Syntax: [label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the 8-bit literal ‘k’.
The result is placed in the W
register.

PIC12F529T39A
11.0 DEVELOPMENT SUPPORT 11.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

PIC12F529T39A
11.2 MPLAB XC Compilers 11.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other related modules together
relocatable object files and archives to create an
• Flexible creation of libraries with easy module
executable file. MPLAB XC Compiler uses the
listing, replacement, deletion and extraction
assembler to produce its object file. Notable features of
the assembler include:
11.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
11.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

PIC12F529T39A
11.6 MPLAB X SIM Software Simulator 11.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by The MPLAB ICD 3 In-Circuit Debugger System is
simulating the PIC MCUs and dsPIC DSCs on an Microchip’s most cost-effective, high-speed hardware
instruction level. On any given instruction, the data debugger/programmer for Microchip Flash DSC and
areas can be examined or modified and stimuli can be MCU devices. It debugs and programs PIC Flash
applied from a comprehensive stimulus controller. microcontrollers and dsPIC DSCs with the powerful,
Registers can be logged to files for further run-time yet easy-to-use graphical user interface of the MPLAB
analysis. The trace buffer and logic analyzer display IDE.
extend the power of the simulator to record and track
The MPLAB ICD 3 In-Circuit Debugger probe is
program execution, actions on I/O, most peripherals
connected to the design engineer’s PC using a high-
and internal registers.
speed USB 2.0 interface and is connected to the target
The MPLAB X SIM Software Simulator fully supports with a connector compatible with the MPLAB ICD 2 or
symbolic debugging using the MPLAB XC Compilers, MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
and the MPASM and MPLAB Assemblers. The supports all MPLAB ICD 2 headers.
software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory 11.9 PICkit 3 In-Circuit Debugger/
environment, making it an excellent, economical
software development tool.
Programmer
The MPLAB PICkit 3 allows debugging and
11.7 MPLAB REAL ICE In-Circuit programming of PIC and dsPIC Flash microcontrollers
Emulator System at a most affordable price point using the powerful
graphical user interface of the MPLAB IDE. The
The MPLAB REAL ICE In-Circuit Emulator System is MPLAB PICkit 3 is connected to the design engineer’s
Microchip’s next generation high-speed emulator for PC using a full-speed USB interface and can be
Microchip Flash DSC and MCU devices. It debugs and connected to the target via a Microchip debug (RJ-11)
programs all 8, 16 and 32-bit MCU, and DSC devices connector (compatible with MPLAB ICD 3 and MPLAB
with the easy-to-use, powerful graphical user interface of REAL ICE). The connector uses two device I/O pins
the MPLAB X IDE. and the Reset line to implement in-circuit debugging
The emulator is connected to the design engineer’s and In-Circuit Serial Programming™ (ICSP™).
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector 11.10 MPLAB PM3 Device Programmer
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal,
Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable
(CAT5). voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
The emulator is field upgradable through future firmware (128 x 64) for menus and error messages, and a
downloads in MPLAB X IDE. MPLAB REAL ICE offers modular, detachable socket assembly to support
significant advantages over competitive emulators various package types. The ICSP cable assembly is
including full-speed emulation, run-time variable included as a standard item. In Stand-Alone mode, the
watches, trace analysis, complex breakpoints, logic MPLAB PM3 Device Programmer can read, verify and
probes, a ruggedized probe interface and long (up to program PIC devices without a PC connection. It can
three meters) interconnection cables. also set code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

PIC12F529T39A
11.11 Demonstration/Development 11.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide and Trace Systems
application firmware and source code for examination • Protocol Analyzers from companies, such as
and modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and
demonstration software for analog filter design,
KEELOQ® security ICs, CAN, IrDA®, PowerSmart
battery management, SEEVAL® evaluation system,
Sigma-Delta ADC, flow rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

PIC12F529T39A
12.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)

Ambient temperature under bias ............................................................................................................-40°C to +85°C
Storage temperature ............................................................................................................................-55°C to +150°C
Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V
Voltage on VDDRF with respect to VSSRF ........................................................................................................0 to +3.9V
Voltage on MCLR with respect to VSS ..........................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS................................................................................ -0.3V to (VDD + 0.3V)
Total power dissipation(1) ..................................................................................................................................700 mW
Max. current out of VSS pin ................................................................................................................................200 mA
Max. current into VDD pin ...................................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Max. output current sunk by any I/O pin...............................................................................................................25 mA
Max. output current sourced by any I/O pin .........................................................................................................25 mA
Max. output current sourced by I/O port ..............................................................................................................75 mA
Max. output current sunk by I/O port ...................................................................................................................75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL)
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC12F529T39A
12.1 RF Transmitter Electrical Specifications

Symbol Description Conditions Min. Typ. Max. Unit
Current Consumption
IDDSL Supply Current in Sleep mode — — 0.5 1 µA
IDDT_315 Supply Current in Transmit RFOP = +10 dBm 50% OOK — 11 — mA
mode at 315 MHz* RFOP = +10 dBm FSK — 15 — mA
RFOP = 0 dBm FSK — 9 — mA
IDDT_915 Supply Current in Transmit RFOP = +10 dBm FSK — 17.5 — mA
mode at 915 MHz* RFOP = 0 dBm FSK — 10.5 — mA
RF and Baseband Specifications
FBAND Accessible Frequency Bands Band 0, with FXOSC = 22 MHz 310 — 450 MHz
See details in Table 7 Band 0, with FXOSC = 24 MHz 312 — 450 MHz
Band 0, with FXOSC = 26 MHz 338 — 450 MHz
Band 1, with FXOSC = 26 MHz 860 — 870 MHz
902 — 928 MHz
FDA Frequency deviation, FSK — 10 — 200 kHz
BRF Bit rate, FSK Permissible Range 0.5 — 100 kbps
BRO Bit rate, OOK Permissible Range 0.5 — 10 kbps
OOK_B OOK Modulation Depth — — 45 — dB
RFOP RF output power in 50 Ohms High-Power Setting 7 10 — dBm
in either frequency bands Low-Power Setting* -3 0 — dBm
RFOPFL RF output power flatness From 315 to 390 MHz — 2 — dB
DRFOPV Variation in RF output power 2.5V to 3.3V — — 3 dB
with supply voltage 1.8V to 3.7V — — 7 dB
PHN Transmitter phase noise At offset: 100 kHz — -82 -76 dBc/Hz
350 kHz — -92 -81 dBc/Hz
550 kHz — -96 -91 dBc/Hz
1.15 MHz — -103 -101 dBc/Hz
STEP_22 RF frequency step FXOSC = 22 MHz, Band 0 — 1.34277 — kHz
FXOSC = 26 MHz, Band 1 — 3.17383 — kHz
FXOSC Crystal Oscillator Frequency — — 22 — MHz
— 24 — MHz
— 26 — MHz
Timing Specifications
tWAKE Time from Sleep to Tx mode XTAL dependant, with spec’d — 650 2000 us
XTAL
tOFFT Timer from Tx data activity to Programmable — 2 — ms
Sleep — 20 — ms
tRAMP PA Ramp up and down time — — 20 — us
tSTART Time before CTRL pin mode Time from power on to — 1 — ms
selection sampling of CTRL
fCTRL CTRL Clock Frequency — — — 10 MHz
tCH CTRL Clock High time — 45 — — ns
tCL CTRL Clock Low time — 45 — — ns
tRISE CTRL Clock Rise time — — — 5 ns
tFALL CTRL Clock Fall time — — — 5 ns

PIC12F529T39A
12.1 RF Transmitter Electrical Specifications
Symbol Description Conditions Min. Typ. Max. Unit
tSETUP DATA Setup time From DATA transition to CTRL 45 — — ns
rising edge
tHOLD DATA Hold time From CTRL rising edge to 45 — — ns
DATA transition
t0 Time at ‘1’ on DATA during See Figure 9-4 — — 5 ns
Recovery Sequence Timing
t1 Time at ‘0’ on DATA during See Figure 9-4 5 — — ns
Recovery Sequence Timing
TABLE 12-1: POWER CONSUMPTION IN TX MODE

Frequency Band Conditions Typical Current Drain
310 to 450 MHz POUT = +10 dBm, OOK modulation with 50% duty cycle 11 mA
POUT = +10 dBm, FSK modulation 15 mA
POUT = 0 dBm, FSK modulation 9 mA
860 to 870 MHz POUT = +10 dBm, FSK modulation 16.5 mA
POUT = 0 dBm, FSK modulation 10 mA
902 to 928 MHz POUT = +10 dBm, FSK modulation 17.5 mA
POUT = 0 dBm, FSK modulation 10.5 mA

PIC12F529T39A
FIGURE 12-1: PIC12F529T39A VOLTAGE-FREQUENCY GRAPH, -40C  TA  +85C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0 INTOSC ONLY
3.5
3.0
2.5
2.0
0 4 8 10 20 25
Frequency (MHz)
FIGURE 12-2: MAXIMUM OSCILLATOR FREQUENCY TABLE
LP
Oscillator Mode
XT
EXTRC
INTOSC
0 200 kHz 4 MHz 8 MHz
Frequency (MHz)

PIC12F529T39A
12.2 DC Characteristics
TABLE 12-2: DC CHARACTERISTICS: PIC12F529T39A (INDUSTRIAL)

Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Operating Temperature -40C  TA  +85C (industrial)
Param
Sym. Characteristic Min. Typ(1) Max. Units Conditions
No.
D001 VDD Supply Voltage 2.0 3.7 V See Figure 12-1
D002 VDR (2)
RAM Data Retention Voltage — 1.5* — V Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure — Vss — V See Section 8.4 “Power-on
Power-on Reset Reset (POR)” for details
D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section 8.4 “Power-on
Power-on Reset Reset (POR)” for details
D005 IDDP Supply Current During Prog/ — 250* — A
Erase.
D010 IDD Supply Current(3,4) — 175 250 A FOSC = 4 MHz, VDD = 2.0V
— 250 400 A FOSC = 8 MHz, VDD = 2.0V
— 11 20 A FOSC = 32 kHz, VDD = 2.0V
D020 IPD Power-down Current(5) — 0.1 1.2 A VDD = 2.0V
D022 IWDT WDT Current — 1.0 3.0 A VDD = 2.0V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail for external clock modes; all I/O pins tri-stated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

PIC12F529T39A
TABLE 12-3: DC CHARACTERISTICS: PIC12F529T39A (Industrial)
DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C (industrial)
Operating voltage VDD range as described in DC specification.
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O ports
D030A Vss — 0.15 VDD V Otherwise
D031 with Schmitt Trigger buffer Vss — 0.15 VDD V
D032 MCLR, T0CKI Vss — 0.15 VDD V
D033 OSC1 (EXTRC mode) Vss — 0.15 VDD V (Note 1)
D033A OSC1 (XT and LP modes) Vss — 0.3 V
VIH Input High Voltage
I/O ports —
D040A 0.25 VDD — VDD V Otherwise
+ 0.8V
D041 with Schmitt Trigger buffer 0.85 VDD — VDD V For entire VDD range
D042 MCLR, T0CKI 0.85 VDD — VDD V
D042A OSC1 (EXTRC mode) 0.85 VDD — VDD V (Note 1)
D043 OSC1 (XT and LP modes) 1.6 — VDD V
D070 IPUR I/O PORT weak pull-up current(5) 50 250 400 A VDD = 3.7V, VPIN = VSS
IIL Input Leakage Current(2), (3)
D060 I/O ports — — ±1 A Vss VPIN VDD, Pin at
high-impedance
D061 GP3/MCLR(4) — ±0.7 ±5 A Vss VPIN VDD
D063 OSC1 — — ±5 A Vss VPIN VDD, XT and LP
osc configuration
Output Low Voltage
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, –
40C to +85C
Output High Voltage
D090 I/O ports(3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, –
40C to +85C
Capacitive Loading Specs on Output Pins
D101 All I/O pins — — 50 pF
Flash Data Memory
D120 ED Byte endurance 100K 1M — E/W –40C  TA  +85C
D121 VDRW VDD for read/write VMIN — 3.7 V
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12F529T39A be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: This specification applies to GP3/MCLR configured as GP3 with internal pull-up disabled.
5: This specification applies to all weak pull-up devices, including the weak pull-up found on GP3/MCLR. The current
value listed will be the same whether or not the pin is configured as GP3 with pull-up enabled or MCLR.

PIC12F529T39A
TABLE 12-4: PULL-UP RESISTOR RANGES
Temperature
VDD (Volts) Min. Typ. Max. Units
(C)
GP0/GP1
2.0 –40 73K 105K 186K 
25 73K 113K 187K 
85 82K 123K 190K 
GP3
2.0 –40 63K 81K 96K 
25 77K 93K 116K 
85 82K 96K 116K 

PIC12F529T39A
12.3 Timing Parameter Symbology and Load Conditions – PIC12F529T39A
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
2 to mc MCLR
ck CLKOUT osc Oscillator
cy Cycle time os OSC1
drt Device Reset Timer t0 T0CKI
io I/O port wdt Watchdog Timer
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (high-impedance) V Valid
L Low Z High-impedance
FIGURE 12-3: LOAD CONDITIONS – PIC12F529T39A
Legend:
pin CL CL = 50 pF for all pins except OSC2
15 pF for OSC2 in XT or LP modes
VSS when external clock is used
to drive OSC1
FIGURE 12-4: EXTERNAL CLOCK TIMING – PIC12F529T39A
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2

PIC12F529T39A
12.4 AC Characteristics
TABLE 12-5: EXTERNAL CLOCK TIMING REQUIREMENTS

Operating Temperature -40C  TA  +85C (industrial),
AC CHARACTERISTICS
Operating Voltage VDD range is described in Section 12.0 “Electri-
cal Characteristics”.
Param
Sym. Characteristic Min. Typ Max. Units Conditions
No.
1A FOSC External CLKIN Frequency(1) DC — 4 MHz XT Oscillator mode
DC — 200 kHz LP Oscillator mode
Oscillator Frequency(1) DC — 4 MHz EXTRC Oscillator mode
0.1 — 4 MHz XT Oscillator mode
DC — 200 kHz LP Oscillator mode
1 TOSC External CLKIN Period(1) 250 — — ns XT Oscillator mode
5 — — s LP Oscillator mode
(1)
Oscillator Period 250 — — ns EXTRC Oscillator mode
250 — 10,000 ns XT Oscillator mode
5 — — s LP Oscillator mode
2 TCY Instruction Cycle Time 200 4/FOSC DC ns
3 TosL, Clock in (OSC1) Low or High 50* — — ns XT Oscillator
TosH Time 2* — — s LP Oscillator
4 TosR, Clock in (OSC1) Rise or Fall — — 25* ns XT Oscillator
TosF Time — — 50* ns LP Oscillator
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. When an external clock
input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
TABLE 12-6: CALIBRATED INTERNAL RC FREQUENCIES

Operating Temperature -40C  TA  +85C (industrial),
AC CHARACTERISTICS
Operating Voltage VDD range is described in Section 12.0 “Electrical
Characteristics”.
Param Freq.
Sym. Characteristic Min. Typ† Max. Units Conditions
No. Tolerance
F10 FOSC Internal Calibrated 1% 7.92 8.00 8.08 MHz 3.5V, 25C
INTOSC Frequency(1) 2% 7.84 8.00 8.16 MHz 2.5V VDD  3.7V
0C  TA  +85C
5% 7.60 8.00 8.40 MHz 2.0V VDD  3.7V
-40C  TA  +85C (Ind.)
† Data in the Typical (“Typ”) column is at 3.7V, 25C unless otherwise stated. These parameters are for
design guidance only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

PIC12F529T39A
FIGURE 12-5: I/O TIMING
Q4 Q1 Q2 Q3
OSC1
I/O Pin
(input)
17 19 18
I/O Pin Old Value New Value

(output)
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 12-7: TIMING REQUIREMENTS

AC CHARACTERISTICS Operating Temperature -40C  TA  +85C (industrial)
Operating Voltage VDD range is described in Section 12.0 “Electrical Characteristics”.
Param
Sym. Characteristic Min. Typ(1) Max. Units
No.
17 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid(2), (3) — — 100* ns

18 TOSH2IOI OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold 50 — — ns
time)(2)
19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 20 — — ns
20 TIOR Port Output Rise Time(3) — 10 50** ns
21 TIOF Port Output Fall Time(3) — 10 50** ns
TBD = To be determined.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 3.7V, 25°C unless otherwise stated. These parameters are for
2: Measurements are taken in EXTRC mode.
3: See Figure 12-3 for loading conditions.

PIC12F529T39A
FIGURE 12-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out(2)
Internal
Reset
Watchdog
Timer
Reset
31
34 34
I/O pin(1)
Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT Reset only in XT and LP.
TABLE 12-8: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F529T39A
Operating Voltage VDD range is described in Table 12-3.
Param
No.
30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 3.0V
31 TWDT Watchdog Timer Time-out 9* 20* 35* ms VDD = 3.0V (Industrial)
Period (no prescaler)
32 TDRT Device Reset Timer Period
Standard 9* 20* 35* ms VDD = 3.0V (Industrial)
Short 0.5* 1.125* 2* ms VDD = 3.0V (Industrial)
34 TIOZ I/O High-impedance from MCLR — — 2000* ns
low
Note 1: Data in the Typical (“Typ”) column is at 3.7V, 25C unless otherwise stated. These parameters are for
TABLE 12-9: DRT (DEVICE RESET TIMER PERIOD)

Oscillator Configuration POR Reset Subsequent Resets
IntRC and ExtRC 1 ms (typical) 10 s (typical)

XT and LP 18 ms (typical) 18 ms (typical)

PIC12F529T39A
FIGURE 12-7: TIMER0 CLOCK TIMINGS
T0CKI
40 41
42
TABLE 12-10: TIMER0 CLOCK REQUIREMENTS

Param
No.
40 Tt0H T0CKI High Pulse No Prescaler 0.5 TCY + 20* — — ns
Width With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse No Prescaler 0.5 TCY + 20* — — ns
Width With Prescaler 10* — — ns
42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
TABLE 12-11: FLASH DATA MEMORY WRITE/ERASE REQUIREMENTS

Param
No.
43 TDW Flash Data Memory 2 3.5 5 ms
Write Cycle Time
44 TDE Flash Data Memory 2 3 4 ms
Erase Cycle Time

PIC12F529T39A
13.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean + 3) or
(mean - 3) respectively, where  is a standard deviation, over each temperature range.
FIGURE 13-1: TYPICAL IDD vs. FOSC OVER VDD (XT, EXTRC mode)
800
700
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
600
500
IDD (A)
400
300
200
2V
100
0
0 1 2 3 4 5
FOSC (MHz)
FIGURE 13-2: MAXIMUM IDD vs. FOSC OVER VDD (XT, EXTRC mode)
800
700
(-40°C to 85°C)
600
500
IDD (A)
400
300
2V
200
100
0
0 1 2 3 4 5
FOSC (MHz)

PIC12F529T39A
FIGURE 13-3: IDD vs. VDD OVER FOSC (LP MODE)
120
Industrial: Mean (Worst-Case Temp) + 3σ 
(-40°C to 85°C)
100
80
32 kHz Maximum Extended

IDD (A)
60
32 kHz Maximum Industrial
40
32 kHz Typical
20
0
1 2 3 4 5 6
VDD (V)

PIC12F529T39A
FIGURE 13-4: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
0.45
0.40 Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
0.35
0.30
0.25
IPD (A)
0.20
0.15
0.10
0.05
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 13-5: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
18.0
(-40°C to 85°C)
14.0
12.0
10.0
IPD (A)
8.0
6.0
4.0
Max. 85°C
2.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F529T39A
FIGURE 13-6: TYPICAL WDT IPD vs. VDD
8 Typical: Statistical Mean @25°C

7 (-40°C to 85°C)
5
IPD (A)
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 13-7: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
25.0
(-40°C to 85°C)
20.0
15.0
IPD (A)
10.0
Max. 85°C
5.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F529T39A
FIGURE 13-8: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)
50
45 Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
40
Max. 85°C
35
30
Time (ms)
Typical. 25°C
25
20
Min. -40°C
15
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F529T39A
FIGURE 13-9: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
0.8

(-40°C to 85°C)
0.6
0.5 Max. 85°C

VOL (V)
0.4
0.3 Typical 25°C
0.2
Min. -40°C
0.1
0.0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
FIGURE 13-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

3.5
3.0
Max. -40°C
Typ. 25°C
2.5
2.0
VOH (V)
1.5

(-40°C to 85°C)
0.5
0.0
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0
IOH (mA)

PIC12F529T39A
FIGURE 13-11: TTL INPUT THRESHOLD VIN vs. VDD
1.7

(-40°C to 85°C)
1.3
Max. -40°C
VIN (V)
1.1
Typ. 25°C
0.9
0.7
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 13-12: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
4.0

(-40°C to 125°C)
3.0
2.5
VIN (V)
VIH Max. 125°C
2.0
VIH Min. -40°C
1.5
VIL Max. -40°C
1.0
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F529T39A
FIGURE 13-13: DEVICE RESET TIMER (XT AND LP) vs. VDD
45
40
35
30
DRT (ms)
25
Max. 85°C
20
15 Typical 25°C
Min. -40°C
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F529T39A
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
14-Lead TSSOP (4.4 mm) Example
XXXXXXXX 529T39A
YYWW 1010
NNN 017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC12F529T39A
14.2 Package Details
The following sections give the technical details of the packages.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

PIC12F529T39A

PIC12F529T39A

PIC12F529T39A
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (05/2012)
Initial release.
Revision B (01/2015)
Updated Register 8-1 and Table 9-3; Other minor
corrections.

PIC12F529T39A
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for
documents, latest software releases and archived support. Local sales offices are also available to help
software customers. A listing of sales offices and locations is
• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://microchip.com/support
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

PIC12F529T39A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX

Examples:
Device Tape and Reel Temperature Package Pattern a) PIC12F529T39AT - I/ST 301
Option Range Tape and Reel,
Industrial temperature,
TSSOP package
QTP pattern #301
Device: PIC12F529T39A
Tape and Reel Blank = Standard packaging (tube or tray)

Option: T = Tape and Reel(1)
Temperature I = -40C to +85C (Industrial)

Range:
Note 1: Tape and Reel identifier only appears in the

Package: ST = TSSOP catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
Pattern: QTP, SQTP, Code or Special Requirements with your Microchip Sales Office for package
(blank otherwise) availability with the Tape and Reel option.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications.
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-934-3
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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03/25/14
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PIC12F529T39A: 14-Pin, 8-Bit Flash Microcontroller

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PIC12F529T39A: 14-Pin, 8-Bit Flash Microcontroller

Uploaded by

PIC12F529T39A

14-Pin, 8-Bit Flash Microcontroller

 2012-2015 Microchip Technology Inc. DS40001635B-page 1

PIC12F529T39A Family Types

DS40001635B-page 2  2012-2015 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

 2012-2015 Microchip Technology Inc. DS40001635B-page 3

TABLE 1-1: FEATURES AND MEMORY OF PIC12F529T39A

DS40001635B-page 4  2012-2015 Microchip Technology Inc.

 2012-2015 Microchip Technology Inc. DS40001635B-page 5

TABLE 3-1: PIC12F529T39A MEMORY

DS40001635B-page 6  2012-2015 Microchip Technology Inc.

Note 1: 201-byte GPR in PIC12F529T39A, including linear RAM.

 2012-2015 Microchip Technology Inc. DS40001635B-page 7

DS40001635B-page 8  2012-2015 Microchip Technology Inc.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Fetch INST (PC)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H Fetch 1 Execute 1

 2012-2015 Microchip Technology Inc. DS40001635B-page 9

Flash Data Memory(2)

Note 1: Address 0000h becomes the effective

DS40001635B-page 10  2012-2015 Microchip Technology Inc.

4.2.1 GENERAL PURPOSE REGISTER

FIGURE 4-2: REGISTER FILE MAP

0Fh 2Fh 4Fh 6Fh

1Fh 3Fh 5Fh 7Fh 9Fh BFh DFh FFh

Note 1: Not a physical register.

 2012-2015 Microchip Technology Inc. DS40001635B-page 11

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

DS40001635B-page 12  2012-2015 Microchip Technology Inc.

REGISTER 4-1: STATUS: STATUS REGISTER

bit 7 GPWUF: Wake-up From Sleep on Pin Change bit

 2012-2015 Microchip Technology Inc. DS40001635B-page 13

REGISTER 4-2: OPTION: OPTION REGISTER

bit 7 GPWU: Enable Wake-up On Pin Change bit

000 1:2 1:1

DS40001635B-page 14  2012-2015 Microchip Technology Inc.

REGISTER 4-3: OSCCAL: OSCILLATOR CALIBRATION REGISTER

bit 7-1 CAL<6:0>: Oscillator Calibration bits

 2012-2015 Microchip Technology Inc. DS40001635B-page 15

CALL or Modify PCL Instruction

DS40001635B-page 16  2012-2015 Microchip Technology Inc.

FIGURE 4-4: DIRECT/INDIRECT ADDRESSING

Bank Select Location Select Location Select

Addresses map back to

4.9 Direct Data Addressing

 2012-2015 Microchip Technology Inc. DS40001635B-page 17

DS40001635B-page 18  2012-2015 Microchip Technology Inc.

EXAMPLE 5-3: WRITING A FLASH DATA

Note 1: Only a series of BSF commands will work

5.3 Write Verify

 2012-2015 Microchip Technology Inc. DS40001635B-page 19

DS40001635B-page 20  2012-2015 Microchip Technology Inc.

 2012-2015 Microchip Technology Inc. DS40001635B-page 21

REGISTER 6-1: GPIO: GPIO REGISTER

bit 7-6 Unimplemented: Read as ‘0’

REGISTER 6-2: TRISGPIO: TRI-STATE GPIO REGISTER

bit 7-6 Unimplemented: Read as ‘0’

DS40001635B-page 22  2012-2015 Microchip Technology Inc.

FIGURE 6-1: PIC12F529T39A EQUIVALENT CIRCUIT FOR I/O PINS – GP0/GP1

 2012-2015 Microchip Technology Inc. DS40001635B-page 23

DS40001635B-page 24  2012-2015 Microchip Technology Inc.

• General Purpose I/O

 2012-2015 Microchip Technology Inc. DS40001635B-page 25

From OSC2 Oscillator Circuit

• General Purpose I/O

DS40001635B-page 26  2012-2015 Microchip Technology Inc.

Note 1: GP3/MCLR pin has a protection diode to VSS

TABLE 6-2: SUMMARY OF PORT REGISTERS

 2012-2015 Microchip Technology Inc. DS40001635B-page 27

FIGURE 6-6: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2 PC + 3 This example shows a write to GPIO followed

DS40001635B-page 28  2012-2015 Microchip Technology Inc.