COMPUTER ENGINEERING DEPARTMENT

Computer Architecture Activity Manual

ACTIVITY 6: Verilog Programming - Conditional Statement If Statement and Case

Statement (Combinational Logic Circuit)

6.1 Program Outcomes (POs) Addressed by the Activity

a. ability to apply knowledge of mathematics and science to solve engineering problems
b. ability to design and conduct fieldworks, as well as to analyse and interpret data
c. ability to function on multidisciplinary teams

6.2 Activity’s Intended Learning Outcomes (AILOs)

At the end of this activity, the student shall be able to:
a. introduce the Integrated Development of Quartus II software
b. familiarize with the parts of Quartus II software
c. familiarize the parts of Altera Cyclone II FPGA board
d. demonstrate the uses of different forms of if-statements and case
statements in characterizing the behaviour of different combinational logic
circuits

6.3 Objectives of the Activity

The objectives of this activity are to:
a. familiarize students in using the Quartus II software and the Cyclone II FPGA board
b. familiarize the students in creating Quartus II software projects and Verilog program
c. program the behavior of different combinational logic circuits using Verilog
behavioral description
d. apply conditional structure (IF statement and case statement) in the design of Verilog
program
6.4 Principle of the Activity

Figure 1 : General Syntax of CASE Statement

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 1

6.5 Materials/Equipment

1 PC unit
1 Keyboard and Mouse
1 USB cable
1 Adaptor

6.6 Procedure/s
1. Given below is the truth table of the half-adder circuit.

a b S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

2. Given below is the first version, using nested CASE statement

3. Explanations

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 2

 This program is an implementation of a nested CASE statement in Verilog. The program
contains two processes as identified by the two outputs.

Line 1 : Definition and declaration of module; named EXPERIMENT7.

Line 2 : Definition of two inputs a and b.

Line 3 : Definition of two outputs S and C.

Line 4 : Re-declaration of output S using the reserve word reg.This is needed for the first
process for output S.

Line 5 : The reserve word always @ is used to define the process inside your Verilog
program, it is of the same concept as you are using process inside a VHDL program.
What are inside the parenthesis (a, b) are the input ports that you’ll be using inside your
process.

Line 6 : The reserve word begin is used to begin your process.

Line 7 : The expression case (a) switches the value of input a to the expression.

Line 8 : If the value of a matches with the test value 1’b0(which is actually equivalent to
a value of logic 0), the statement after the colon (:) is executed, which in this scenario
another case is to be performed.

The expression case (b) switches the value of input b to the expression.

Line 9 : If the value of b matches with the test value 1’b0(which is actually equivalent to
a value of logic 0), the statement after the colon (:) is executed, causing the value of logic
0 be stored to output S.

Line 10: If the value of b does not match with the test value 1’b0, the statement after
default is executed, an implied meaning that the value of b here is logic 1. The statement
after default is executed, causing the value of logic 1 be stored to output S.

Line 11 : The reserve word endcase is used to end the inner case statement; case(b)of
Line 8.

Line 12 : The default here is executed when the value of a does not match with the test
value 1’b0, an implied meaning that the value of a here is logic 1. The expression case
(b) switches the value of input b to the expression.

Line 13 : If the value of b matches with the test value 1’b0(which is actually equivalent
to a value of logic 0), the statement after the colon (:) is executed, causing the value of
logic 1 be stored to output S.

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 3

 Line 14 : If the value of b does not match with the test value 1’b0, the statement after
default is executed, an implied meaning that the value of b here is logic 1. The statement
after default is executed, causing the value of logic 0 be stored to output S.

Line 15 :The reserve word endcase is used to end the inner case statement; case(b) of
Line 12.

Line 16 : The reserve word endcase is used to end the outer case statement; case(a) of
Line 7.

It is necessary to always end every case you opened.

Line 17 : The reserve word end ends the first process.

Same explanation goes with Line 18 through Line 31.

Line 32 : The reserve word endmodule ends the module.

4. Save, compile and download your program in the FPGA board. Verify results.

5. Given below is the second version, using if-case statement

6. Save, compile and download your program in the FPGA board. It should give the same
output to that of the first version.

7. Given below is the third version, using case-if statement.

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 4

 8. Save, compile and download your program in the FPGA board. It should give the same
output to that of the first two versions.

9. Design a Verilog program implementing behavioral descriptions of the full-adder

circuit using nested case, if-case, case-if statements presented in the procedure. Write
your codes in Table 1 of the Data and Results section of this activity.

10. Design a Verilog program implementing behavioral descriptions of the full subtractor
circuit using nested case, if-case, case-if statements presented in the procedure. Write
your codes in Table 2 of the Data and Results section of this activity.

11. Design a Verilog program implementing behavioral descriptions of a combinational

circuit with three inputs and six outputs. The output binary number should be the square
of the input binary number. Implement the design using nested case statement. Write
your codes in Table 3 of the Data and Results section of this activity.

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 5

6.7 Activity Report

6.7.1 Data and Results

Table 1
FULL ADDER-NESTED CASE

module FA6 (A, B, Cin, S, C);

input A, B, Cin;
output S, C;
reg S;

always @ (A, B, Cin)

begin
case (A)
1'b0 :
case (B)
1'b0:
case (Cin)
1'b0 : S=1'b0;
default: S=1'b1;
endcase
default: case (Cin)
1'b0 : S=1'b1;
default: S=1'b0;
endcase
endcase
default: case (B)
1'b0:
case (Cin)
1'b0: S=1'b1;
default: S=1'b0;
endcase
default: case (Cin)
1'b0 : S=1'b0;
default: S=1'b1;
endcase
endcase
endcase
end

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 6

 reg C;
always @ (A,B,Cin)

begin
case (A)
1'b0 :
case (B)
1'b0:
case (Cin)
1'b0 : C=1'b0;
default: C=1'b0;
endcase
default: case (Cin)
1'b0 : C=1'b0;
default: C=1'b1;
endcase
endcase
default: case (B)
1'b0:
case (Cin)
1'b0: C=1'b0;
default: C=1'b1;
endcase
default: case (Cin)
1'b0 : C=1'b1;
default: C=1'b1;
endcase
endcase
endcase
end
endmodule

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 7

 FULL ADDER-IF CASE

module FA6B (A, B, Cin, S, C);

input A, B, Cin;
output S, C;
reg S;
always @ (A,B,Cin)
begin
if (A==1'b0)
case (B)
1'b0:
case (Cin)
1'b0 : S=1'b0;
default: S=1'b1;
endcase
default: case (Cin)
1'b0 : S=1'b1;
default: S=1'b0;
endcase
endcase
else
case (B)
1'b0:
case (Cin)
1'b0: S=1'b1;
default: S=1'b0;
endcase
default: case (Cin)
1'b0 : S=1'b0;
default: S=1'b1;
endcase
endcase
end
reg C;
always @ (A, B, Cin)
begin
if (A==1'b0)
case (B)
1'b0:
case (Cin)
1'b0 : C=1'b0;
default: C=1'b0;
endcase

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 8

 default: case (Cin)
1'b0 : C=1'b0;
default: C=1'b1;
endcase
endcase
else
case (B)
1'b0:
case (Cin)
1'b0: C=1'b0;
default: C=1'b1;
endcase
default: case (Cin)
1'b0 : C=1'b1;
default: C=1'b1;
endcase
endcase
end
endmodule

FULL ADDER- CASE IF

module FA6C (A, B, Cin, S, C);
input A, B, Cin;
output S, C;

reg S;

always @ (A, B, Cin)

begin

case (A)
1'b0: if (B == 1'b0 && Cin == 1'b0)
S= 1'b0;
else if (B == 1'b0 && Cin == 1'b1)

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 9

 S= 1'b1;
else if (B == 1'b1 && Cin == 1'b0)
S= 1'b1;
else
S = 1'b0;
default : if (B == 1'b0 && Cin == 1'b0)
S=1'b1;
else if (B == 1'b0 && Cin == 1'b1)
S=1'b0;
else if (B == 1'b1 && Cin == 1'b0)
S =1'b0;
else
S = 1'b1;
endcase
end

reg C;
always @ (A, B, Cin)

begin
case (A)
1'b0: if (B == 1'b0 && Cin == 1'b0)
C = 1'b0;
else if (B == 1'b0 && Cin == 1'b1)
C = 1'b0;
else if (B == 1'b1 && Cin == 1'b0)
C = 1'b0;
else
C = 1'b1;
default : if (B == 1'b0 && Cin == 1'b0)
C =1'b0 ;
else if (B == 1'b0 && Cin == 1'b1)
C =1'b1;
else if (B == 1'b1 && Cin == 1'b0)
C =1'b1;
else
C= 1'b1;
endcase
end
endmodule

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 10

 TABLE 2
FULL SUBTRACTOR-NESTED CASE
module FA6D (A, B, Bin, D, Bout);
input A, B, Bin;
output D, Bout;

reg D;

always @ (A, B, Bin)

begin
case (A)
1'b0 :
case (B)
1'b0:
case (Bin)
1'b0 : D=1'b0;
default: D=1'b1;
endcase
default: case (Bin)
1'b0 : D=1'b1;
default: D=1'b0;
endcase
endcase
default: case (B)
1'b0:
case (Bin)
1'b0: D=1'b1;
default: D=1'b0;
endcase
default: case (Bin)
1'b0 : D=1'b0;
default: D=1'b1;
endcase
endcase
endcase
end

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 11

 reg Bout;
always @ (A, B, Bin)
begin
case (A)
1'b0 :
case (B)
1'b0:
case (Bin)
1'b0 : Bout=1'b0;
default: Bout=1'b1;
endcase
default: case (Bin)
1'b0 : Bout=1'b1;
default: Bout=1'b1;
endcase
endcase
default: case (B)
1'b0:
case (Bin)
1'b0: Bout=1'b0;
default: Bout=1'b0;
endcase
default: case (Bin)
1'b0 : Bout=1'b0;
default: Bout=1'b1;
endcase
endcase
endcase
end
endmodule

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 12

 FULL SUBTRACTOR-IF CASE
module FA6E (A, B, Bin, D, Bout);
input A, B, Bin;
output D,Bout;
reg D;
always @ (A, B, Bin)
begin
if (A==1'b0)
case (B)
1'b0:
case (Bin)
1'b0 : D=1'b0;
default: D=1'b1;
endcase
default: case (Bin)
1'b0 : D=1'b1;
default: D=1'b0;
endcase
endcase
else
case (B)
1'b0:
case (Bin)
1'b0: D=1'b1;
default: D=1'b0;
endcase
default: case (Bin)
1'b0 : D=1'b0;
default: D=1'b1;
endcase
endcase
end
reg Bout;
always @ (A, B, Bin)
begin
if (A==1'b0)
case (B)
1'b0:
case (Bin)
1'b0 : Bout=1'b0;
default: Bout=1'b1;
endcase
default: case (Bin)

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 13

 1'b0 : Bout=1'b1;
default: Bout=1'b1;
endcase
endcase
else
case (B)
1'b0:
case (Bin)
1'b0: Bout=1'b0;
default: Bout=1'b0;
endcase
default: case (Bin)
1'b0 : Bout=1'b0;
default: Bout=1'b1;
endcase
endcase
end
endmodule

FULL SUBTRACTOR-CASE IF
module FA6F (A, B, Bin, D, Bout);
input A, B, Bin;
output D, Bout;

reg D;

always @ (A, B, Bin)

begin
case (A)
1'b0: if (B == 1'b0 && Bin == 1'b0)
D= 1'b0;
else if (B == 1'b0 && Bin == 1'b1)
D= 1'b1;
else if (B == 1'b1 && Bin == 1'b0)
D= 1'b1;

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 14

 else
D = 1'b0;
default : if (B == 1'b0 && Bin == 1'b0)
D=1'b1;
else if (B == 1'b0 && Bin == 1'b1)
D=1'b0;
else if (B == 1'b1 && Bin == 1'b0)
D =1'b0;
else
D = 1'b1;
endcase
end
reg Bout;
always @ (A, B, Bin)
begin
case (A)
1'b0: if (B == 1'b0 && Bin == 1'b0)
Bout = 1'b0;
else if (B == 1'b0 && Bin == 1'b1)
Bout = 1'b1;
else if (B == 1'b1 && Bin == 1'b0)
Bout = 1'b1;
else
Bout = 1'b1;
default : if (B == 1'b0 && Bin == 1'b0)
Bout =1'b0 ;
else if (B == 1'b0 && Bin == 1'b1)
Bout =1'b0;
else if (B == 1'b1 && Bin == 1'b0)
Bout =1'b0;
else
Bout= 1'b1;
endcase
end
endmodule

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 15

 TABLE 3
NESTED CASE
module FA6T3 (A1,A2,A3,B1,B2,B3,B4,B5,B6);
input A1,A2,A3;
output B1,B2,B3,B4,B5,B6;

reg B1;
always @ (A1,A2,A3)
begin

case (A1)
1'b0:
B1 = 1'b0;
default:
case (A2)
1'b0:
case (A3)
1'B0: B1 = 1'b0;
default: B1 = 1'b0;
endcase
default: case (A3)
1'B0: B1 = 1'b1;
default: B1= 1'b1;
endcase
endcase
endcase
end

reg B2;
always @ (A1,A2,A3)
begin
case (A1)
1'b0:
B2 = 1'b0;
default:
case (A2)
1'b0:
B2 = 1'b1;
default:
case (A3)
1'b0:
B2 = 1'b0;
default :

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 16

 B2 = 1'b1;
endcase
endcase
endcase
end

reg B3;
always @ (A1,A2,A3)
begin
case (A1)
1'b0:
case (A2)
1'b0:
B3 = 1'b0;
default:case (A3)
1'b0:
B3 = 1'b0;
default :B3 = 1'b1;
endcase
endcase
default:
case (A2)
1'b0:
case (A3)
1'b0: B3 = 1'b0;
default : B3 = 1'b1;
endcase
default:
B3=1'b0;
endcase
endcase
end

reg B4;
always @ (A1,A2,A3)
begin
case (A1)
1'b0 :
case (A2)
1'b0:
B4 = 1'b0;
default:

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 17

 case (A3)
1'b0:B4 = 1'b1;
default:
B4 = 1'b0;
endcase
endcase
default:
case (A2)
1'b0:
B4 = 1'b0;
default:
case (A3)
1'b0:
B4 = 1'b1;
default:
B4 = 1'b0;
endcase
endcase
endcase
end

reg B5;
always @ (A1)
begin
case (A1)
1'b0: B5 = 1'b0;
default: B5 = 1'b0;
endcase
end

reg B6;
always @ (A3)
begin
case (A3)
1'b0: B6 = 1'b0;
default: B6 = 1'b1;
endcase
end

endmodule

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 18

 6.7.2 Observations
 Case statements are simpler and straightforward than if statements.
 It is better to use case statements in more complex circuits.

6.7.3 Conclusion/s

The main objective of this activity is for the students to enhance their skills in
Verilog programming, creating case statements to be specific. During the
experiment, the students were asked to create several Verilog programs with case
statements. There are three types of case statements which are nested, if-case, and
case-if. The students succeeded in producing the output waveforms which are
correlated to the theoretical results. And thus, this activity was a success.

6.7.4 Miscellaneous (FPGA Pin Assignments)

LED PIN ASSIGNMENTS SWITCH PIN ASSIGNMENTS

LEDR0 R20 SW0 L22
LEDR1 R19 SW1 L21
LEDR2 U19 SW2 M22
LEDR3 Y19 SW3 V12
LEDR4 T18 SW4 W12
LEDR5 V19 SW5 U12
LEDR6 Y18 SW6 U11

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 19

 LEDR7 U18 SW7 M2
LEDR8 R18 SW8 M1
LEDR9 R17 SW9 L2
LEDG0 U22 KEY0 R22
LEDG1 U21 KEY1 R21
LEDG2 V22 KEY2 T22
LEDG3 V21 KEY3 T21
LEDG4 W22
LEDG5 W21
LEDG6 Y22
LEDG7 Y21

6.7.5

Section: TE31 Date Performed: July 06, 2021

Course Code: CPE0037l Date Submitted: July 06, 2021
Course Title: COMP ARCHITECTURE AND ORGANIZATION LAB
Instructor: ENGR. MISOLA
Group No.: Activity No.: FA6
Group Members: Signature:
1. JUSTINE DARYL LOPEZ

6.7.6 Rubrics/Rating

Member Member Member Member Member

Criteria
1 2 3 4 5

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 20

 Activity Conduct (1-5)
         
Equipment
Operation and (1-5)
Material Handling          

Data Collection (1-5)

 

Data Analysis and

(1-5)
Evaluation
 

Results
(1-5)
Interpretation
 

Total Score
         
Mean Score = (Total Score/5)
         
Percentage Score = (Total
Score/5)*100
         
Other Comments/Observations:

ACTIVITY 6: VERILOG PROGRAMMING - CONDITIONAL IF AND CASE STATEMENT 21