NMOS & CMOS

inverter and gates

Unit II
NMOS & CMOS Digital Logic Inverter

S. B. Sivasubramaniyan MSEC, Chennai

CMOS Inverter
 It is the basic building block of any digital system
 We had discussed the operation of the circuit
earlier

S. B. Sivasubramaniyan MSEC, Chennai

CMOS Inverter - Operation

S. B. Sivasubramaniyan MSEC, Chennai

CMOS Inverter – Operation

S. B. Sivasubramaniyan MSEC, Chennai

CMOS Inverter - inference
 The output voltage levels are 0 and VDD. This shows the signal
swing is maximum
 The static power dissipation is zero
 A low resistance path exists between output and ground and
output and VDD
 The low resistance path is independent of W/L ration of the
transistor
 The input resistance is infinite. Thus the inverter can drive large
number of similar inverters but the delay rises accordingly

S. B. Sivasubramaniyan MSEC, Chennai

The Voltage Transfer Characteristics

 Repetition of the above graphical procedure for

intermediate values gives rise to voltage transfer
characteristics
 The current equations of the two transistors in the two
regions of operation is given by
W   1 2 1 ' W  
kn    vI  Vtn  
2
iDN  k    vI  Vtn  vo  v0 
' iDN 
n
 L n  2  2  L n  

for , vo  vI  Vtn for , vo  vI  Vtn

S. B. Sivasubramaniyan MSEC, Chennai

The Voltage Transfer Characteristics

 The current equations of the two transistors in the two

regions of operation is given by

W  

iDP  k p'    VDD  vI  Vtp
 L p 
  VDD  vo  
1
2
V  v
2
 DD o  

for , vo  vI  Vtp
1 W 

 k p'    VDD  vI  Vtp  
2
iDP
2  L  p  

for , vo  vI  Vtp
S. B. Sivasubramaniyan MSEC, Chennai
The Voltage Transfer Characteristics

 The CMOS inverter is usually designed to have the equal

' W  ' W 
threshold voltage and
kn    k p  
 L n  L p
 We know, kn'  nCox & k p'   pCox
 The electron mobility is 2 to 2.5 times higher than that of holes
so to make
W  W 
kn'    k p'  
 The width of the p-channel  Ldevices
n L p
ismade 2 to 2.5 times larger
 Note: Both devices are designed to have equal Length

S. B. Sivasubramaniyan MSEC, Chennai

The Voltage Transfer Characteristics

 The width of the two devices are related by

' W  ' W 
kn    k p  
 L n  L p
W  W 
nCox     pCox  
 L n  L p

nWn   pW p Ln  L p
Wpn
 
Wn  p
S. B. Sivasubramaniyan MSEC, Chennai
The Voltage Transfer Characteristics

 When this is accomplished, we say that the CMOS

inverter is symmetric
 The Voltage transfer characteristic will be symmetric

S. B. Sivasubramaniyan MSEC, Chennai

The Voltage Transfer Characteristics

 To determine VIH, we need to equate the current of QN

and QP
 QN operates in the triode region and QP operates in the
saturation region
 Equating the currents, we get
1  1 2
 DD I tn   I tn  o v0 
2
V  v  V  v  V v 
2  2 

S. B. Sivasubramaniyan MSEC, Chennai

The Voltage Transfer Characteristics

 Differentiate both sides relative to VI, and substitute

dvo
vI  VIH &  1
dvI
 We get,
VDD
vo  VIH 
2
 Substitute,
VDD
vI  VIH & vo  VIH 
2
S. B. Sivasubramaniyan MSEC, Chennai
The Voltage Transfer Characteristics

 We get,
1
VIH   5VDD  2Vt 
8

 Similarly 1
VIL   3VDD  2Vt 
8
 From VIL and VIH, we can determine Noise Margins
NM H  VOH  VIH NM L  VIL  VOL

1 1
 NM H   3VDD  2Vt   NM L   3VDD  2Vt 
8 8
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The Voltage Transfer Characteristics

 Symmetrical transistors assumptions gave rise to

identical noise margins

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 For a CMOS inverter with matched MOSFETs having Vt =
1 V, find
 VIL , VIH and the noise margins if VDD = 5V

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 We know,
1
VIH   5VDD  2Vt 
8
 Substituting, we get
1
VIH   5  5   2  1   VIH  2.875V
8
 Similarly,
1 1
VIL 
8
 3VDD  2Vt   VIL 
8
 3  5   2  1   2.125V

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 We know,
1
NM H   3VDD  2Vt 
8
 Substituting, we get
1
NM H   3  5   2  1   NM H  2.1V
8
 Similarly,

NM L  NM H

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 Consider a CMOS inverter with Vtn  Vtp  2V , (W/L)n =
 C
20, (W/L)p = 40, n ox  2  C
p ox  20  A / V 2
, and VDD =
10 V. For vI  VDD , find the maximum current that the
inverter can sink while vo remains  0.5V

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 Sinking current is taken care by NMOS transistor
 For vo  0.5V , NMOS transistor will operate in the
triode region (?)
 The current equation is given by
W   1 2
iDN
 L n 
 
 nCox    vI  Vtn vo  v0 
2 
 The maximum current for vo  0.5V , will occur when
vo  0.5V

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 Substituting, we get

W   1 2
iDN
 L n 
 
 nCox    vI  Vtn vo  v0 
2 
 1 2
iDN  20  20   10  2  0.5  0.5 
 2 

 iDN  1.55mA

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 An inverter fabricated in a 1.2 m CMOS technology uses
the minimum possible channel length Ln  L p  1.2  m
(i.e., ). If Wn = 1.8 m, find the value of Wp
that would result in QN and QP being matched. For this
kn  80  A / V 2 , k p  27  A / V 2 ,Vtn  0.8V & VDD  5V
technology,
. Also, calculate the value of
vo  VOLof the inverter when
the output resistance

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 We know,
Wn  p

Wp n
 Substituting, we get

1.8  p 1.8 k p 1.8 27

    
Wp n Wp kn Wp 80
 W p  5.4  m

S. B. Sivasubramaniyan MSEC, Chennai

Solution

 When vo  VOL , NMOS transistor actually provides the

path of low resistance given by,
1
rDSN 
 W
kn    VDD  Vtn 
 L n
1 V
rDSN   rDSN  0.001984
 A  1.8  A
80 2    5  0.8  V
V  1.2    rDSN  1.984k 

S. B. Sivasubramaniyan MSEC, Chennai

Assignment
 Show that the threshold voltage Vth of a CMOS inverter is

 
given by
r VDD  Vtp  Vtn
Vth 
1 r
 Where,
 W 
kp  
 L p
r
 W 
kn  
 L n
S. B. Sivasubramaniyan MSEC, Chennai
Dynamic Operation
 The speed of digital system is characterized by the
propagation delay of the individual gates employed in the
chip
 The inverter propagation delay is the basic parameter
with which the propagation delay of the whole system is
specified
 Here we are going to discuss about the propagation delay
of the basic inverter

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Operation
 It is assumed that the input is driven by a pulse with zero
rise time and zero fall time
 The inverter propagation delay is the basic parameter
with which the propagation delay of the whole system is
specified

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Operation

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Operation - Assumptions
 We assume the transistors to be matched
 This makes tpHL and tpLH to be same
 Calculating any one of the parameter will help us to
obtain the other
 We will calculate tpHL
 For which, we assume that at the instant t = 0+ the
output voltage is at VDD
 Now transistor QN is ON which would sink large current

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Operation
 The characteristics is shown in the figure

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Operation
 Substituting the expression for current we get,
iDN dt  Cdvo
 W  1 2
k n    VDD  Vt  vo  v0  dt  Cdvo
 L n  2 
 W
k n  
 L n dvo
dt  
C  1 2
 VDD  Vt  vo  2 v0 
S. B. Sivasubramaniyan MSEC, Chennai
Dynamic Operation

 W
kn  
 L n 1 dvo
dt  
C  VDD  Vt   v02 
 vo  
 2  DD t  
V  V
 W
k n  
 L n 1 dvo
dt 
C  VDD  Vt   v02 
  vo 
 2  VDD  Vt  
S. B. Sivasubramaniyan MSEC, Chennai
Dynamic Operation

S. B. Sivasubramaniyan MSEC, Chennai

 Dynamic Operation
 Integrating the equation between the limits, VDD – Vt and
VDD/2, we get
 Also tpHL is denoted as tpHL2

 W
k n   VDD
 L n 1 dvo
C
t pHL 2 
 VDD  Vt   2
VDD Vt  v02 
  vo 
 2  VDD  Vt  

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Operation
 We know, dx  1 
  ax 2  x   ln 1  ax 
 
1
Here, a  & x 2  vo
2  VDD  Vt 
VDD
   2

  
C  ln  1  1 
t pHL 2 
W   1 
kn  VDD  Vt    vo 
L   2  VDD  Vt   VDD Vt
S. B. Sivasubramaniyan MSEC, Chennai
 Dynamic Operation
 Simplifying,
C   3VDD  4Vt  
t pHL 2   ln 
W VDD
kn  VDD  Vt   
L
 Total time, t pHL  t pHL1  t pHL 2

CVt C   3VDD  4Vt  

 t pHL    ln 
1 W W V
 DD t   VDD  Vt   
2
kn V  V kn DD
2 L L
S. B. Sivasubramaniyan MSEC, Chennai
Dynamic Operation
 Simplifying,
2C  Vt 1  3VDD  4Vt  
t pHL    ln 
 Vt    VDD  Vt  2
W VDD
kn  VDD 
L
 Taking the typical value for threshold voltage
Vt  0.2VDD
 And substituting here, we get 1.6C
t pHL 
 W
kn   VDD
 L n
S. B. Sivasubramaniyan MSEC, Chennai
Dynamic Operation
 For tpLH, the same expression applies except for
 W
kn  
 L n
 Which has to replaced by
 W
k p  
 L p

S. B. Sivasubramaniyan MSEC, Chennai

Propagation Delay
 For tp,
t pLH  t pHL
tp 
2

S. B. Sivasubramaniyan MSEC, Chennai

 Propagation Delay - Inference
 For tp to be lower,
 Capacitance should be small
 Kn’ should be high
 (W/L) should be high
 VDD should be high
 A trade off between above parameters is done to ensure lower propagation delay

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 A CMOS inverter in a VLSI circuit operating from a 10 V
supply has W  W 
   20,    40,
 L n  L p
nCox  2 p Cox  20 A / V 2 ,Vtn  Vtp  2V .

If the total effective load capacitance is 15 pF. Find tp

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 We Know
1.6C
tp 
 W 
kn   VDD
 L n

1.6  15 pF   t p  6ns
 tp 
20  20  10

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 Alternate
2C  Vt 1  3VDD  4Vt 
tp    ln  
W  V  V 2  VDD 
kn    VDD  Vt   DD t
 L n

2  15   1012   2 1  3  10   4  2  
tp    ln  
 20   20   8 10  2 2  10  
 t p  6ns
S. B. Sivasubramaniyan MSEC, Chennai
Assignment
 Solution
t pLH  0.8ns, t pHL  0.8ns, t p  0.8ns

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Power Dissipation – contd.

 The expression for propagation delay can also be derived

by taking the average of the currents at VDD (operating
point E) and at VDD/2 (operating point F)

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Power Dissipation – contd.

 Device current at E is the saturation current of NMOS

transistor, given by
1 W 
iDN  0  kn    VDD  Vt 
2

2  L n
 Device current at F is the triode region current of NMOS
transistor, given by
 W   V 1  VDD 
2

iDN  t   kn    VDD  Vt  DD
   
pHL
L
  n  2 2  2  

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Power Dissipation – contd.

 Average current
 1 
iDN  av     iDN  0  iDN  t  
 2   pHL 

 The propagation delay is given by (high to low)
C V
t pHL 
iDN  av 

C  VDD / 2 
t pHL 
iDN  av 

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Power Dissipation – contd.

 Propagation delay
C  VDD / 2 
t pHL 
1 1 W   
2
 W  V 1  VDD 
 kn    VDD  Vt   kn     VDD  Vt 
2 DD
    
2  2  L  n L
 n  2 2  2   
 Simplifying, we get
CVDD
t pHL 
   
2 2
 W  V  V V 1  VDD 
kn    DD t
  VDD  Vt  DD
   
L
 n  2 2 2  2  

S. B. Sivasubramaniyan MSEC, Chennai

Dynamic Power Dissipation – contd.

 Propagation delay
CVDD
t pHL 
   2 
2
 W  0.8V VDD VDD
kn    DD
  0.8VDD   
 L  n  2 2 8 

1.7C
 t pHL 
W 
kn   VDD
 L n

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 Consider a CMOS inverter fabricated in a 0.25 mm
process defined as follows,
nCox  115 A / V 2 ,  p Cox  30 A / V 2 ,Vtn  Vtp  0.4V ,
 W  0.375 m  W  1.125 m
VDD  2.5V ,    ,   , CL  6.25 fF
 L n 0.25 m  L  p 0.25 m
 Find, t pHL , t pHL & t p

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 The Propagation delay, (high to low)
C  VDD / 2 
t pHL 
 Where, iDN  av 

iDN  av 
1

 iDN  0  iDN  t 
2 pHL


S. B. Sivasubramaniyan MSEC, Chennai

Solution

1 W 
 kn    VDD  Vt 
2
iDN  0
2  L n
1  0.375 
  2.5  0.4   iDN  0  380 A
2
iDN  0  115 
2  0.25  n
 W  VDD 1  VDD  
2

iDN  t   kn    VDD  Vt     

pHL
L
  n  2 2  2  

 0.375   2.5 1  0.5  

2

iDN  t   115    2.5  0.4       iDN  t pHL   318 A

pHL
 0.25   2 2  2  
S. B. Sivasubramaniyan MSEC, Chennai
Solution

1
iDN  av    318  380  
2
 iDN  av   349  A
 Propagation delay,
C  VDD / 2   6.25  1015   1.25
t pHL   t pHL 
iDN  av   349   106 
 t pHL  23.3 ps
S. B. Sivasubramaniyan MSEC, Chennai
Solution
 From the given data,
 Wp   n 
 3 &    3.83
W  
 n  p
 We see that, the transistors are not matched,
 The low to high transition will increase by a factor
(3.83/3)
 3.83 
t pLH    t pHL  t pLH  1.3  23.3  t pLH  30 ps
 3 

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 Therefore, the actual propagation delay is given by,
1
tp 
2
 t pLH  t pHL 
1
 t p   23.3  30 
2

 t p  26.5 ps

S. B. Sivasubramaniyan MSEC, Chennai

Assignment
 Suppose that an additional load capacitance of 0.1pF is
added for the inverter mentioned in the previous
problem. Also, in an attempt to decrease the area of the
inverter in the previous problem, (W/L)p is made equal to
(W/L)n. What is the percentage reduction in area
achieved? Find the new values of tpHL, tpLH, and tp.

S. B. Sivasubramaniyan MSEC, Chennai

Current Flow and Power Dissipation

 Consider the two characteristics which were already

introduced

S. B. Sivasubramaniyan MSEC, Chennai

Current Flow and Power Dissipation

 The total energy dissipation in the CMOS inverter in the

two cases is given by
2
CVDD
 If the inverter is switched at the rated of f cycles per
second, the dynamic power dissipation is given by
PD  fCVDD
2

S. B. Sivasubramaniyan MSEC, Chennai

Current Flow and Power Dissipation

 We know, frequency of operation is inversely

proportional to the propagation delay
 The lower the propagation delay (desired) the higher is
the power dissipation (not desirable)
 A figure of merit referred to as Power Delay product is
thus introduced
 Power Delay product is given by
DP  PD t p

S. B. Sivasubramaniyan MSEC, Chennai

Power Delay product

 Power Delay product is a constant, the lower the value of

Power Delay product, higher is the effectiveness of the
technology
 The Power Delay product has the unit of joules
 It is a measure of energy dissipated per cycle of operation
 For CMOS technology, the power delay product is simply
DP  CVDD
2

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 Consider a CMOS inverter with Vtn  Vtp  2V , (W/L)n =
 C
20, (W/L)p = 40, n ox  2  C
p ox  20  A / V 2
, and VDD =
10 V. Find peak current drawn from the supply.

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 For peak current drawn from the supply, Vth = VDD/2
 QP and QN both work in the saturation region
 The current equation if given by
1 W 
 
2
iDP  k p   VDD  VI  Vtp
2  L p
 Substituting, we get
2
1  A  10  2
iDP   10 2   40  10   2  V
2 V   2 

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 Simplifying, we get
iDP  1800 A  1.8mA

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 Consider a CMOS VLSI chip having 100,000 gates
fabricated in a 1.2 m CMOS technology. Let load
capacitance per gate be 30 fF. If the chip is operated from
a 5V supply and is switched at a rate of 100 MHz, find
 The power dissipation per gate
 The total power dissipated in the chip assuming that only
30 % of the gates are switched at any one time

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 Power dissipation per gate is the dynamic power
dissipation given by
P  fCVDD
2

 Substituting,
P  100  10  30  10   5
6 15 2

 P  75W

S. B. Sivasubramaniyan MSEC, Chennai

Solution
 Total Power dissipation when 30 % of the gates are
switched at any one time
 30 
P  75W  100, 000
 100 
 P  2.25W

S. B. Sivasubramaniyan MSEC, Chennai

Problem
 Consider a CMOS inverter with Vtn  Vtp  2V , (W/L)n =

20, (W/L)p = 40, n oxC  2  C
p ox  20  A / V 2
, and VDD =
10 V. If the inverter is loaded by 15 pF capacitor, find the
dynamic power dissipation when it is switched at a
frequency of 2 MHz. What is the average current drawn
from the supply?

S. B. Sivasubramaniyan MSEC, Chennai

Assignment

 Solution
 3 mW, 0.3 mA

S. B. Sivasubramaniyan MSEC, Chennai

Combinational logic design – with CMOS

 Combinational circuits do not have memory

elements
 Combinational circuits forms part of every digital
systems

S. B. Sivasubramaniyan MSEC, Chennai

Combinational logic design – with CMOS

 CMOS logic circuit is just an extension of CMOS

inverter
 As we know, in a CMOS inverter, a pull-down
transistor is formed by a NMOS device and a pull-
up transistor is formed by a PMOS device
 Similarly, a CMOS logic circuit will have a pull-
down network formed by NMOS transistors, and
a pull-up network formed by PMOS transistors

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down and Pull-up network
 Pull-down network (PDN) will contain all input combinations
that make the output low
 Similarly, Pull-up network (PUN) will contain all input
combinations that make the output high
 We know, Pull-down network is formed by NMOS transistors
and NMOS transistors are activated when the gate is high, a
PDN network is activated when the gate(input) is high
 Similarly, a Pull-up network is activated when the
gate(input ) is low

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down and Pull-up network
 The inputs to PDN and PUN networks work in a
complementary fashion similar to CMOS inverter in
which inputs to NMOS and PMOS devices work in a
complementary fashion

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down - Basics
 The pull-down (and Pull-up) network employs devices in
parallel to realize OR function
 The pull-down (and Pull-up) network employs devices in
series to realize AND function

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down - examples
 Y will be low when A is high or B is high

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down - examples
 Y will be low when A is high and B is high

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down - examples
 Y will be low when A is high or when B and C are high

S. B. Sivasubramaniyan MSEC, Chennai

Pull-up - Basics
 The pull-up (and Pull-down) network employs devices in
parallel to realize OR function
 The pull-up (and Pull-down) network employs devices in
series to realize AND function

S. B. Sivasubramaniyan MSEC, Chennai

Pull-up - examples
 The pull-up (and Pull-down) network employs devices in
parallel to realize OR function
 The pull-up (and Pull-down) network employs devices in
series to realize AND function

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down - examples
 Y will be high when A is low or B is low

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down - examples
 Y will be high only when A and B are low

S. B. Sivasubramaniyan MSEC, Chennai

Pull-down - examples
 Y will be high only when A is low or if B and C are both
low

S. B. Sivasubramaniyan MSEC, Chennai

Assignment

 Two input NOR gate

 Two input NAND gate
 Y = [A(B + CD)]’
 Two input Ex-OR gate
 Three input Ex-OR gate

S. B. Sivasubramaniyan MSEC, Chennai