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Verilog Tutorial For Beginners

Verilog is a hardware description language (HDL) used to model and design digital circuits. It allows engineers to describe circuit behavior and functionality rather than physically designing transistor layouts. This simplifies the design process. The tutorial introduces Verilog basics like data types, modules, ports, and behavioral modeling. It provides an example of a Verilog module that models the behavior of an up/down counter to illustrate how Verilog hides physical implementation details while clearly describing a circuit's function.

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Novelyn Rabino
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95 views4 pages

Verilog Tutorial For Beginners

Verilog is a hardware description language (HDL) used to model and design digital circuits. It allows engineers to describe circuit behavior and functionality rather than physically designing transistor layouts. This simplifies the design process. The tutorial introduces Verilog basics like data types, modules, ports, and behavioral modeling. It provides an example of a Verilog module that models the behavior of an up/down counter to illustrate how Verilog hides physical implementation details while clearly describing a circuit's function.

Uploaded by

Novelyn Rabino
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
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9/3/2020 Verilog Tutorial for Beginners

Verilog Tutorial

In the early days of integrated circuits, engineers had to sit


down and physically draw transistors and their connections on
paper to design them such that it can be fabricated on silicon.
Bigger and complex circuits demanded more engineers, time
and other resources and soon enough there was a need to
have a better way of designing integrated circuits.

VHDL was soon developed to enhance the design process by


allowing engineers to describe functionality of the desired
hardware and let automation tools convert that behavior into
actual hardware elements like combinational gates and
sequential logic. Verilog was developed to simplify the
process and make the Hardware Description Language (HDL)
more robust and flexible. Today, Verilog is the most popular
HDL used and practiced throughout the semiconductor
industry.

Contents

Ch#1: Learn the essence of Verilog, how it fits into the


Introduction design flow and why it is required in design of
digital circuits

Ch#2: Data Learn all about basic data types like reg, wire and
Types nets with simple examples

Ch#3: Learn about modules, ports, initial, always and


Building assign blocks and what they actually mean in
Blocks hardware circuits

Ch#4: Learn how to model behavior of sequential and


Behavioral combinational logic using always and assign
Modeling constructs

Ch#5: Learn how to represent delays in combinational


Gate/Switch gates, and model using primitive logic gates like
Modeling AND, OR, etc

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9/3/2020 Verilog Tutorial for Beginners

Ch#6: Learn basics of simulation, concept of timescales,


Simulation scheduling regions and display statements
Basics

Ch#7: Learn real simple examples with complete


Examples testbench code and analysis

How is Verilog useful ?

Verilog creates a level of abstraction that helps hide away the


details of its implementation and technology.

For example, the design of a D flip-flop would require the


knowledge of how the transistors need to be arranged to
achieve a positive-edge triggered FF and what the rise, fall
and clk-Q times required to latch the value onto a flop among
many other technology oriented details. Power dissipation,
timing and the ability to drive nets and other flops would also
require a more thorough understanding of the physical
characteristics of a transistor.

Verilog helps us to focus on the behavior and leave the rest to


be sorted out later.

Example

The following code illustrates how a Verilog code looks like.


We will delve into more details of the code in the next article.
For the time being, let us simply understand that
the behaviorof a counter is described. The code essentially
makes the counter count up if the up_down signal is 1, and
down if its value is 0. It also resets the counter if the
signal rstn becomes 0 making this an active-low reset.

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9/3/2020 Verilog Tutorial for Beginners

module ctr (input up_down,


clk,
rstn,
output reg [2:0] out);

always @ (posedge clk)


if (!rstn)
out <= 0;
else begin
if (up_down)
out <= out + 1;
else
out <= out - 1;
end
endmodule

The simple example shown above illustrates how all the


physical implementation details have been hidden while still
providing a clear idea of how the counter functions.

ctr is a module that represents an up/down counter, and it


is possible to choose the actual physical implementation of the
design from a wide variety of different styles of flops optimized
for area, power and performance. They are usually compiled
into libraries and will be available for us to select within EDA
tools at a later stage in the design process.

Now that you know what Verilog is, let's start learning Verilog !

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9/3/2020 Verilog Tutorial for Beginners

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