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Basic Discussion On Pcie Configuration and Enumeration

This document discusses PCIe configuration and enumeration. It defines enumeration as detecting devices, assigning addresses, mapping resources, and identifying functionality. It provides a simple diagram of the enumeration process and overview of PCI/PCIe address spaces including configuration space. It describes configuration transaction types and routing. The configuration space header format and accessing the header via configuration transactions is explained. Finally, an example enumeration process is outlined.

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301 views

Basic Discussion On Pcie Configuration and Enumeration

This document discusses PCIe configuration and enumeration. It defines enumeration as detecting devices, assigning addresses, mapping resources, and identifying functionality. It provides a simple diagram of the enumeration process and overview of PCI/PCIe address spaces including configuration space. It describes configuration transaction types and routing. The configuration space header format and accessing the header via configuration transactions is explained. Finally, an example enumeration process is outlined.

Uploaded by

nazim
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Basic Discussion on

PCIe Configuration and Enumeration

Md. Nazimuddowla
Lead Design Verification Engineer
Synapse Design Inc.
mnazimuddowla@synapse-da.com
Discussion Area

https://www.synopsys.com/designware-ip/technical-
bulletin/pci-express.html https://shantanu25.wordpress.com/2016/12/11/pci-e/
Agenda of this discussion
“
1. Enumeration Definition
2. Simple task diagram for quick understanding
3. Full Circuit diagram and ports overview
4. PCI and PCIe Address Space
5. Address Configuration Spaces
6. Transaction Types
7. Transaction routing
8. Access of the configuration Space
9. Configuration Space Header
10. Steps to Configuration transaction to endpoint
11. Enumeration Process example
Enumeration by definition

❑ Its actually a process of 4 combined tasks.

❑ Firstly detecting the PCI/PCIe devices that connected to the CPU through PCI
tropology.

❑ Assigning address to the detected devices.

❑ If memory is available of the device memory then, map base address and size to the
system memory.

❑ Identify the functionalities of the devices


Task diagram for quick understanding

5
Conceptual Circuit Example
Address Spaces
PCI PCIe
◎ Configuration Space (0 to 256 ◎ Configuration Space extended to
Bytes). This is required or standard 4Kb (0 to 255 for legacy 266 to 4k for
field. native). This is required or standard
field.

◎ Memory-mapped Space (Optional)


◎ Memory-mapped Space (Optional)

◎ I/O-mapped Space (Optional)


◎ I/O-mapped Space (Optional)

◎ Message Space (Optional)


Generic PCIe Topology
◎ The Root Complex Connects the
processor to the system memory
and components.

◎ Same number of devices supported


as PCI.

◎ Up to 256 PCIe buses, 32 PCIe


devices, 8 Functions supported
under a root complex.

◎ Each Function can implement up to


4KB of configuration space.

◎ Every bridge and endpoint has this


configuration spaces. BAR is for
memory config.
8
Transaction Types
Brief Breakdown of Header Register

10
Transaction Routing

◎ Address Based Routing ◎ ID Based Routing


◎ Through the BAR register of ◎ Through the Configuration
the endpoint device. spaces of devices.
◎ Memory and IO transaction. ◎ Configuration request, ID
◎ For memory read/write, based messages, Completion
atomic operation both 32-bit transaction.
and 64-bit. ◎ Using BDF no 3DW/4DW
◎ IO read/write 32-bit address header type transaction
format. ◎ Completion and Configuration
3DW, Messages 4DW

11
Configuration Address Spaces

◎ Can Access the configuration spaces both Port IO or Memory-mapped IO (MMIO)


which is in 0-255.

◎ Extended Configuration Space have to with only MMIO (255-4KB).

◎ Compatible PCI is configured using the port I/O address/data pair


(CONFIG_ADDRESS, CONFIG_DATA)

◎ Two 32-bit I/O locations are used to generate configuration transaction.


○ 0xCF8 (CONFIG_ADDRESS)
○ 0xCFC (CONFIG_DATA)
◎ CONFIG_DATA can be accessed in DWORD, WORD, BYTE configuration.

◎ To read/write from CONFIG_DATA, the CONFIG_ADDRESS 31th bit has to be “1”.


12
13
Type-0 and Type-1 Configuration Space header

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15
Thanks for the Time
Md. Nazimuddowla
Lead Design Verification Engineer
Synapse Design Inc.
mnazimuddowla@synapse-da.com

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