ELEC 462 Computer Organization and Architecture

Course Project -Term Spring

Pipelined Processor Design

Due date: April 25, 2022 at midnight UAE time

Objective
• Design and implement a pipelined-Datapath and its control logic.
• Add pipeline registers between stages.
• Design the control logic to detect data dependencies among instructions and implement
the forwarding, hazard detection and stall unit.

- CLO1: Explain functional units, fetch-execute cycle, and internal structure of a CPU
[PLO1]
- CLO6: Employ digital-design tools to simulate hardware functions [PLO1, PLO4,
PLO5]

Pre-requisite
Before you attempt this project, you are highly advised to complete the Assignment #1 and
submit it. Not only Assignment #1 is graded, but it also forms the starting point of this project,
and will give you some experience on Logisim. You will HAVE to use the file from assignment
#1 as the starting point of your project. The components used will have to come from the
components in either the file associated with this project, or the file from your assignment #1
submission.
Logisim can be downloaded from here:
http://www.cburch.com/logisim/download.html
You can use any of the following assemblers to help in converting between machine code and
assembly:
MARS: http://courses.missouristate.edu/kenvollmar/mars/
An online MIPS assembler: https://alanhogan.com/asu/assembler.php

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Is it a Group project or an Individual Project?
This project is a group project in which you will need to find a partner or two. Each team
(consisting of a maximum of 3 students) will have to arrange between themselves to make a
group on Blackboard.

Project Timeline
• Use the Blackboard Grouping tool to form groups. Each group can have a maximum of
3 students. This needs to be done and finalized by April 5.
• Support – The course TA will be able to support you throughout the duration of the
project. You may communicate with him through email or MS Teams. His contact
details will be announced via Blackboard.
• Final Submission – April 25 at midnight UAE time
• Demo/Presentation - Short demo presentations will be held during the last week of
classes (week of April 25).

What to Implement
You will implement a five-stage MIPS pipeline, which is the most common
organization for MIPS and is similar to what is described in the book and in class:

1. Fetch
2. Decode
3. Execute
4. Memory
5. Writeback

Implement a five-stage pipelined MIPS processor in Logisim. Your design should

contain a program counter, a read-only program memory (ROM), a register
file, our ALU, and any other components needed, along with the instruction decode
and control circuits needed to connect them all together. The pipeline should: fetch
instructions to execute from the program ROM and increment the program counter
by 4; decode each instruction; select arguments from the register file; compute
results; do nothing in the memory stage; and store results back in the register file.

Your pipeline must correctly execute all of the instructions in Tables A and B
(REFER to the MIPS Reference Sheet for the meaning and Encoding of these
instructions):

Table A
Register arithmetic ADD, SUB, AND, OR, XOR, NOR,
SLT
Shifts (constant and variable) SLL, SRL, SRA

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 Immediate arithmetic - ADDI, ANDI, ORI, XORI
optional

Table B
Jumps (with one delay slot) J, JAL
Branches (with one delay slot) BEQ,
BNE
Memory Load/Store (little endian, with pipeline stall if LW, SW
needed)

Delay slot. You must properly implement the branch/jump delay slot, so that the
instruction immediately following a branch or jump is always executed, and any
relative addresses or significant bits for the PC update are based on the that address
and not the address of the jump instruction itself.

Recommended Steps:
It is required that you start by building the Datapath and control of a single-cycle processor
and ensure its correctness (Assignment #1).
Once you have succeeded in doing this, convert your design and implement a pipelined-
Datapath and its control logic. A five-stage pipeline should be constructed similar to the
pipeline presented in the class lectures.
• Add pipeline registers between stages.
• Design the control logic to detect data dependencies among instructions and
implement the forwarding logic. (please refer to the figure below for your reference)

• Implement a Hazard Detection Unit

o For branch and jump instructions, reduce the delay to one cycle only. Stall the
pipeline for one clock cycle after a jump or a taken branch instruction. If the
branch is not taken, then there is no need to stall the pipeline.
o Also, stall the pipeline after a LW instruction, if it is followed by a dependent
instruction.

WARNING

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Although Logisim is stable, it might crash from time to time. Therefore, it is best to save your
work often. Make several copies and versions of your design before making changes, in case
you need to go back to an older version.

Instruction Encoding
Use the MIPS ISA reference sheet on Blackboard as your primary reference for the
instruction Opcodes.

Program Execution
The program will be loaded and will start at address 0 in the instruction memory. The data
segment will be loaded and will start also at address 0 in the data memory.
To terminate the execution of a program, the last instruction in the program can jump or branch
to itself indefinitely.

Testing
• Carry out the simulation of the processor developed using Logisim.
• Test each of the components individually and demonstrated its correct operation
including the ALU and register file.
• To support you in the testing process, you were provided with three test programs (test-
code-1.mem, test-code2.mem and test-code-3.mem).
Test code 1
lw $t1, 0($zero)
sw $t2, 0($zero)

Test code 2
lw $t1, 0($zero)
sw $t1, 12($zero)

Test code 3
lw $t1, 0($zero)
lw $t2, 4($zero)
add $t3, $t1, $t2
add $t3, $t1, $t3
sw $t3, 12($zero)

• You are required to design additional programs to test other important instructions of
your processor, including the branch instructions.
• You can create your own test programs by using SPIM to compile the code to binary
(http://spimsimulator.sourceforge.net/ ) or using an online MIPS compiler like
http://alanhogan.com/asu/assembler.php
Note that that compiler does not currently support $rX notation.)

Project Report
The report document must contain sections highlighting the following:
1 – Design and Implementation

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 • Specify clearly the design giving detailed description of the datapath, its components,
control, and the implementation details (highlighting the design choices you made and
why, and any notable features that your processor might have.) Document clearly
design alternatives explored and why a given design is selected.
• Provide drawings of the component circuits and the overall datapath.
• Provide a complete description of the control logic and the control signals. Provide a
table giving the control signal values for each instruction. Provide the logic equations
for each control signal.
• Provide a complete description of the forwarding logic, the cases that were handled,
and the cases that stall the pipeline, and the logic that you have implemented to stall the
pipeline.
• Provide list of sources for any parts of your design that are not entirely yours (if any).
• Carry out the design and implementation with the following aspects in mind:
- Correctness of the individual components
- Correctness of the overall design when wiring the components together
- Completeness: all instructions were implemented properly, detecting dependences
and forwarding was handled properly, and stalling the pipeline was handled
properly for all cases.

2 – Simulation and Testing

• Describe the test programs that you used to test your design with enough comments
describing the program, its inputs, and its expected output. List all the instructions that
were tested and work correctly. List all the instructions that do not run properly.
• Describe all the cases that you handled involving dependencies between instructions,
forwarding cases, and cases that stall the pipeline.
• Also provide snapshots of the Simulator window with your test program loaded and
showing the simulation output results.

Teamwork
• This project is a team work project with a maximum of three students. No individual
submission allowed. Make sure to write the names of all the group members on the
project report title page.
• Project tasks should be divided among the group members so that each group member
contributes equally in the project and everyone is involved in all the following
activities:
- Design and Implementation
- Simulation and Testing
- results reporting
• Clearly show the work done by each group member using a chart and prepare an
execution plan showing the time frame for completing the subtasks of the project. You
can also mention how many meetings were conducted between the group members to
discuss the design, implementation, and testing.
• Students who help other team members should mention that to earn credit for that.

Submission Guidelines
All submissions will be done through Blackboard.

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Attach one zip file containing all the design circuits, the test programs source code and binary
instruction files that you have used to test your design, their test data, as well as the report
document.
Your report must clearly document your design solution. The documentation should include
informal descriptions of the various components in your solution. There are no limits on the
length of the report.

Grading policy:
The grade will be divided according to the following components:
■ Correctness: whether your implementation is working
■ Completeness and testing: whether all instructions and cases have been implemented,
handled, and tested properly
■ Participation and contribution to the project
■ Report organization and clarity

Late policy:
The project should be submitted on the due date. Late projects are accepted, but will be
penalized 5% for each late day and for a maximum of 4 late days (or 20%). Projects submitted
after 4 late days will not be accepted.

PLAGARISM:

Plagiarism will be taken very seriously. Plagiarized work will be given a Zero grade right
away, and the university policies on Plagiarism will be applied. It is ok to use components
from the web; however you need to site that in your report.

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