Atmega 2560 Ingles (111-140)
Atmega 2560 Ingles (111-140)
Bit 7 6 5 4 3 2 1 0
(0x6A) ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding
interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined
in Table 15-3. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is
selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed
to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt
request as long as the pin is held low.
Note: 1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the
EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Bit 7 6 5 4 3 2 1 0
0x1D (0x3D) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 EIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x1C (0x3C) INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x68) – – – – – PCIE2 PCIE1 PCIE0 PCICR
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x1B (0x3B) – – – – – PCIF2 PCIF1 PCIF0 PCIFR
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x6D) PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x6C) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
16.2 Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units,
and with PWM support. It allows accurate program execution timing (event management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-1. For the actual placement of I/O pins,
refer to “TQFP-pinout ATmega640/1280/2560” on page 2. CPU accessible I/O Registers, including I/O bits and I/O
pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on
page 126.
Edge
Tn
Detector
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
= =0
OCnA
(Int.Req.)
Waveform
= Generation
OCnA
OCRnA
Fixed
OCnB
TOP
(Int.Req.)
Value
DATA BUS
Waveform
= Generation
OCnB
OCRnB
TCCRnA TCCRnB
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not
shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable fre-
quency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 117. for
details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to gener-
ate an Output Compare interrupt request.
16.2.2 Definitions
Many register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare
Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 16-1 are also used extensively throughout the document.
Table 16-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored
in the OCR0A Register. The assignment is dependent on the mode of operation.
TOVn
DATA BUS (Int.Req.)
Clock Select
count Edge
Tn
clear clkTn Detector
TCNTn Control Logic
direction
( From Prescaler )
bottom top
OCRnx TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator OCnx
FOCn
WGMn1:0 COMnX1:0
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buff-
ering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the
output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x
directly.
16.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the
timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings
define whether the OC0x pin is set, cleared or toggled).
16.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0
without triggering an interrupt when the Timer/Counter clock is enabled.
16.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are
risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the
Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM
when the counter is down-counting.
COMnx1
COMnx0 Waveform
D Q
FOCn Generator
1
OCnx
OCnx Pin
0
D Q
DATA BUS
PORT
D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either
of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direc-
tion Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as
output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Gen-
eration mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled.
Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on
page 126.
16.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes,
setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on
the next Compare Match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 126. For
fast PWM mode, refer to Table 16-3 on page 126, and for phase correct PWM refer to Table 16-4 on page 127.
A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-
PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-
bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
16.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The
OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the
Compare Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 16-5. The counter value (TCNT0) increases until a Com-
pare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.
TCNTn
OCn
(COMnx1:0 = 1)
(Toggle)
Period 1 2 3 4
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
16.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM wave-
form generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and
OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the
Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output
is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of
the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high
frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High
frequency allows physically small sized external components (coils, capacitors), and therefore reduces total sys-
tem cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-6. The
TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent
Compare Matches between OCR0x and TCNT0.
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3 4 5 6 7
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM0A1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle
its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum fre-
quency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode,
except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
16.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform gen-
eration option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly
from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A
when WGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Com-
pare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-counting. In
inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation
frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes,
these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 16-7 on page 123. The TCNT0 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches
between OCR0x and TCNT0.
OCRnx Update
TCNTn
OCnx (COMnx1:0 = 2)
OCnx (COMnx1:0 = 3)
Period 1 2 3
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting
the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the
WGM02 bit is set. This option is not available for the OC0B pin (see Table 16-4 on page 127). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the
counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0
when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calcu-
lated by the following equation:
f clk_I/O
f OCnxPCPWM = -----------------
-
N 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 16-7 OCnx has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match.
• OCR0A changes its value from MAX, like in Figure 16-7. When the OCR0A value is MAX the OCn pin value is
the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn
value at MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.
clkI/O
clkTn
(clkI/O /1)
TOVn
Figure 16-9 shows the same timing data, but with the prescaler enabled.
clkI/O
clkTn
(clkI/O /8)
TOVn
Figure 16-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM
mode, where OCR0A is TOP.
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
OCFnx
Figure 16-11 on page 125 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM
mode where OCR0A is TOP.
clkI/O
clkTn
(clkI/O /8)
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC)
OCRnx TOP
OCFnx
Bit 7 6 5 4 3 2 1 0
0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 16-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 121 for more details.
Table 16-4 on page 127 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
Table 16-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 121 for more details.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 122 for more details.
Bit 7 6 5 4 3 2 1 0
0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/Write W W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
16.9.3 TCNT0 – Timer/Counter Register
Bit 7 6 5 4 3 2 1 0
0x26 (0x46) TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modify-
ing the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between
TCNT0 and the OCR0x Registers.
16.9.4 OCR0A – Output Compare Register A
Bit 7 6 5 4 3 2 1 0
0x27 (0x47) OCR0A[7:0] OCR0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0A pin.
16.9.5 OCR0B – Output Compare Register B
Bit 7 6 5 4 3 2 1 0
0x28 (0x48) OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0B pin.
Bit 7 6 5 4 3 2 1 0
(0x6E) – – – – – OCIE0B OCIE0A TOIE0 TIMSK0
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x15 (0x35) – – – – – OCF0B OCF0A TOV0 TIFR0
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
17.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation,
and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the
register or bit defines in a program, the precise form must be used, that is, TCNT1 for accessing Timer/Counter1
counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 17-1 on page 134. For the actual place-
ment of I/O pins, see “TQFP-pinout ATmega640/1280/2560” on page 2 and “Pinout ATmega1281/2561” on page
4. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Regis-
ter and bit locations are listed in the “Register Description” on page 154.
The Power Reduction Timer/Counter1 bit, PRTIM1, in “PRR0 – Power Reduction Register 0” on page 55 must be
written to zero to enable Timer/Counter1 module.
The Power Reduction Timer/Counter3 bit, PRTIM3, in “PRR1 – Power Reduction Register 1” on page 56 must be
written to zero to enable Timer/Counter3 module.
The Power Reduction Timer/Counter4 bit, PRTIM4, in “PRR1 – Power Reduction Register 1” on page 56 must be
written to zero to enable Timer/Counter4 module.
The Power Reduction Timer/Counter5 bit, PRTIM5, in “PRR1 – Power Reduction Register 1” on page 56 must be
written to zero to enable Timer/Counter5 module.
Timer/Counter4 and Timer/Counter5 only have full functionality in the ATmega640/1280/2560. Input capture and
output compare are not available in the ATmega1281/2561.
Edge
Tn
Detector
TOP BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
= =0
OCFnA
(Int.Req.)
Waveform
= OCnA
Generation
OCRnA
Fixed OCFnB
TOP (Int.Req.)
Values
Waveform
= OCnB
Generation
DATABUS
OCRnB
OCFnC
(Int.Req.)
Waveform
= OCnC
Generation
OCRnC
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge Noise
ICRn
Detector Canceler
ICPn
Note: 1. Refer to Figure 1-1 on page 2, Table 13-5 on page 76, and Table 13-11 on page 80 for Timer/Counter1 and 3 and
3 pin placement and description.
17.2.1 Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register (ICRn) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are
described in the section “Accessing 16-bit Registers” on page 135. The Timer/Counter Control Registers
(TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt requests (shorten as Int.Req.)
signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the
Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers are
shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte
only needs to be written once. However, note that the same rule of atomic operation described previously also
applies in this case.
TEMP (8-bit)
Clock Select
Count Edge
Tn
TCNTnH (8-bit) TCNTnL (8-bit) Clear clkTn Detector
Control Logic
Direction
TCNTn (16-bit Counter)
( From Prescaler )
TOP BOTTOM
TEMP (8-bit)
Analog
Comparator Noise Edge
ICFn (Int.Req.)
Canceler Detector
ICPn
Note: The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not Timer/Counter3, 4 or 5.
When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively on the analog
Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.
When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register
(ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn
Register. If enabled (TICIEn = 1), the input capture flag generates an input capture interrupt. The ICFn flag is auto-
matically cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a
logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and
then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Regis-
ter (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register.
The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for
defining the counter’s TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set
before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be
written to the ICRnH I/O location before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 135.