Analog Modeling Using EventODriven HDL’s

Dundar Dmnluwl, Don W&&r

Cadence Design Systems, Inc.

San Jose,California

Raj eev Madhavan

Abstract before it can be simulated However, this level of detail is

not avaihMe during top down system design.
This paper describes how eventdriven HDL’s can This peper shows how Verilog HDL can be
be used for system level (transfer function, signal flow) successrully used to develop event driven analog models for
modeling of analog mixed-signal systems. The modelling system level simulation.We also discuss how analog models
appromch is illustrated with W o g models for an ADC, in Wog can be used in the mixed-signal simulator Spec@-
DAC, and an Auto-Gain Conmi System (AGC). Simulation w o g .
results for these models obtained with the mixed-signal
simulator Spm-Verilog running under the Cadence
Analog Amst system R e f [811 will be pmented. System 2.0 Analog Behavioral Modeling With Event-
tasks and featms in Varilog that support this kind of Driven HDL’s
modeling and their advantages and limitations will be
discussed. We will briefly describe the requirements for a Eventdriven simulators can be used to model
full-fledged analog HDL as being developed by the VHDL sampled data analog and digital systems. These systems can
1076.1 effort. be modekd’using behaviopal repmentations of the
expnssions and the sampling method.
1.0 Introduction
2.1 D i d z e d analog modeling
Analog designers use circuit simulators such as
SPICE and Spectre [Ref [7]]for analog and digital circuits at For system level and architectural design, it is very
the transistor level. The methodology involves specifing the useful to have a high level *tion of analog functions in
circuit as a netlist of simulator primitives which are tenns of rransfer functions or signal flow block diagrams.At
parametesized models. this level each functional block is represented as a unilateral
The circuit simulator translates the netlist of transfer function of inputs to outputs. For example, an analog
primitives into a set of simultaneous non-linear ordinary multiplier takes two analog signals a, b as input and
differential equations which are solved with iterative produces a+b as output
numerical techniques to compute the response of the circuit Sampled data analog (SDA) and sampled data
to external stimuli. digital (SDD) systems can be modeled in an eventdriven
While circuit simularors can predict very accurately HDL like V d o g or VHDL. In SDA, time is discretized
the detailed behavior of an analog circuit, they are very while signal values are continuous. In SDD. both time and
computation intensive and can not be applied for system- values are discretized.
level verification. Continuous time analog systems can be modeled in
Another shortcoming of circuit simulators is the sampled data form by using a sufficiently high sampling rate
lack of abstraction of detail. The circuit has to be (the Nyquist criterion).
implemented in terms of transistors.resistors. and capacitors

7th lntemailonal Conference on VLSI Design - January 1994

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 By using standard transformation techniques such Anabg values can be represenred as 64-bit rtals in
as the bilinear transformation, differential equafim can be Verilog. Verilog tasLs $bitsmeal and Srealtotrits [Ref [211
transformed into difference equations which can be modeled allow the uansf-011 between the bit and real
in an event-driven HDL. Delay elements can be used to reprcscncations. Rcal values can be passed through the
describe Z-domain discrete systems. An example is the terminals of a Verilog module in @-bit f m . Verilog
transfer characteristic of a DSP filter (shown in Figure 1) supports a basic set of arithmetic operators: *, /, +, -.
which can be represented in an event-driven simulator. 'Ikigonomeak and transce&mi functions (such as an
exponential function which is used in the AGC) can be
linked in through PLI Wef [l]]. We will explore some
lgure 1.DSP Filter models which use these system tasks.

OUT 1 2 4 Analog to Digital Converter Model

The block diagram of an ideal analog to digital

converter of the successive appximation type is shown m
Figure 2. The Verilog model is listed in Figure 4.

temp1 <= #5 in; Figure 2. ADC Model Block Dlagram

temp2 <= in;
....... 1
assinn out = temol+tem02

2.2 Multi-Rate Problem -4

vin-bits

In multi-rate circuits, widely varying clock rates are

used in different sections of the circuit The clock rates can
vary by as much as lO..lW,O. To simulate such circuits
with the sampling rate of the fastest clock is not efficient
For efficient simulation of multi-rate circuits, we
use a piecewise-linear signal repnxntation Ref [a].
Each
analog signal is represented as a piecewise linear function
between sampling points. Higher order approximations are
possible, but are more difficult to implement. At each
sampling point, a signal has a value and a slope, i.e. the rate
of change of the signal value. Hence, at any time point when -
Parameters: N Number of bits
a function outputs a new signal value based on the value of Anaiog Inputs in binary form:
the inputs and the internal state of the function, it must also vin-bits - input voltage vin
calculate the slope of the signal. If the slopes of the inputs vin-d-bits -slope of vin
are known,it is possible to predict the slope of the output. vin-t-bits - sampling time of vin
Linear interpolation is used to obtain signal values between wef-bits - Reference voltage
sample points. Interpolation is required when a function has ~ l -kclock
an input signal with a lower sampling rate than the function Startconv - Start conversion
itself. outputs:
Dout[N-l:Ol - digital output
2.3 Useful Verilog System Tasks eoc (digital)- End of conversion

Event-driven analog modeling in Vexilog can be

seen very much like KIL simulation.At each sampling point The system task $bits& converts the bit
(clock tick), an analog model produces new values based on representation of analog inputs (Vim and Vreo into real
its inputs and intemal state. No zero delay loops are allowed: values. The %dog model for the ADC uses the falling edge
i.e. an output change cannot produce an input change in the (negedge in Verilog) of StanConv (digital input) to trigger a
same clock cycle. The difference with RTL is that signals V d o g rask "ADConversion" and uses the positive edge of
have analog values. SrartConv to disable the conversion task and to set the eoc

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 Fig 4. ADC Verilog Behavioral model
'timescale Ins / Ins
'define N 16 /* Number of bits of the ADC */
'define N1 15
module adc( startconv, clk, eoc, Vin-bits, Vin-d-bits,
Vin-t-bits,Vref-bits, Dout ) ;
input startconv, clk, Vin-bits, Vin-d-bits, Vin-t-bits,
Vref-bits; output Dout, eoc;
wire [63:01 Vin-bits, Vin-d-bits, Vin-t-bits;
wire [63:01 Vref-bits; reg ['Nl:O] Dout; reg eoc;
real Vin, Vin-d, vin-t, Vsample, Vref, Vdac, Vbit;
integer i;
reg ['N1:0] bit; reg ['N1:0] fullscale;
initial begin
eoc = 1; Dout= 'N'bO;
end
always @ (negedge startConv) ADconversion;
always @ (posedge startconv) begin
disable ADconversion; eoc = 1;
end
task ADconversion; begin
eoc = 1; Dout= 'N'bO; fullscale= 'bo;
fullscale= -fullscale ;
Vin = $bitstoreal( Vin-bits ) ;
Vin-d = $bitstoreal( Vin-d-bits ) ;
Vin-t = $bitstoreal( Vin-t-bits ) ;
// find the value of Vin corresponding to current time.
Vsample = Vin + Vin-d * ($time - Vin-t);
Vref = $bitstoreal( Vref-bits ) ;
Vdac = 0.0; bit = 'N'bl << ("1); i = 'NI;
repeat (IN) begin
@ (negedge clk) W i t = (bit*Vref)/fullScale;
Vdac= Vdac + Vbit;
if (Vdac >= Vsample) begin DoutCi] = l'bO;
Vdac = Vdac - Vbit;
end else Dout[i] = 1,bl;
bit = bit >> 1; i = i - 1;
end
@ (negedge clk) eoc = 0;
end
endtask
endmodule

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 llag to 1 Bt the end of convasion.The input vdrage to the 2.7.1 Simulation results
ADC is qrcscnted as a piecewise Linear wavefam as
disc& earlier. Thatfore, besides the value of the input The comet functioning of h e circuit has been
voltage (vin-bits). its slope (vin-d-bits) and the spmple time successfully vaified with specs-verilog. The circuit was
point (vin-t-bits) are input to the block. If a piecewise simulated with a 300 Hz sinewave input over 3OOmS with a
coastantrpproximariwr is used as forvref-b& the s b p e a d clock rate of 1 Mhz.The total simulation time was about IS
thesnmpbpointaremnquired. mins on a Sparc IPX with 32Meg memory. A Specm
simulation of the circuit at the transistor level would have
2.6 Mixed-signalsimuLtion taka days and Couldonly have been dm afterall the blocLs
inthecircUithadbeeni"ented
In the Specmz-Wog mixed-signal solution.
analog signals can cross simulator boundaim such that
analogbehpviaal models inverilogcanbe used in amixed-
~collext
In a c b s s i d mixai-signal simu&or, aaabg
fmmhu~~mnlrlal macimitsimulamrandtb di&d
f"B in a digital simahax. At the intafaar barrrm
malogrd d i g w a2d (aaslog to dilptal) o r a (digital m
mrbe) e"BIC used a2d canvatj an anrbg
into a single-bit logic MLue: 0, 1, or X based on a
thshoMhg limcaon. d2a convem a single bit bgtc vaiue
into an anaiog signal (voltage or current) using a ramp
function
1 - 1 - l I I

In Sp#pe-Wog, in addition to a2d and d2a

mrafaces a2a (aaaiog to anaio@ inrcrfacesare suppom~.
An a2ahtuface passes an analog signal value from one
~ulapuiatotbeothawidKnuconvcrsion
In the Anabg Artist mixed-signal simuhion
syslem,mixai-~desi~arealtcredassc~.Tbe
USQ can select which blocks w
ill be srmulated with Specne
rd wbicb widr \krilog by cbooaing the p a p a s i " We bave shown how went driven analog
Viewofeachbbckar theschaarpc '.Theviewofabladr behfiriaal modeling in Vailog can be successfully used for
caa be selectedon an instamebasefrom theavailable views syaem level top down design and bottom up wxificatim in
forthe bbck. The usacan gamatc new simulntion views. the mixed-signal Specm-Wog simulation solution. High
Thc SySDun will geneme nalistsfor SpectnandVailog ad kvel modeling allows dramatic speed up of simutation o m
iasut interha c0IIvatLn.s (a. ma a2a) whaeva the CiICuit k n L Anotha impatant advantage is thar the
~ Pbe verified early on in the design
m. A mixcd-signai wavcfonn display allows the ~m syaem level C O ~ C C ~cm
to simuItpnaotlsiy view analog and digiral signals on the roce ear before any &tailed implementation is available. We
m e timeaxis. The signals am selected on thehiemchid have outlined rcquircments for a full-fledgedAHDL and
iisped limitations of event-driven analog modeling.

2.7 Auto-Gain Control Circuit (AGC) References

An example of a system level application is the [1J Open V a h g IntaraatiOaai, Veribg-HDLPLI Refenncc
-gain cmurol Cirarit (AGC) in Figure 6. This Circpit M& Umion 1.0, Open W o g Inttmationai, Oaober
cwmI.8 the @n of the amplifies in the AGC black far 1991.
~tmplitudesoftheiapu~Tbecbta iPI
s ~openvailog- . ,VnilogHta"Descw
h"itcd. and fed into a whdow &mLM8yo8cR-nce M a n d ( U M )&mion 1.0,
compa".The ourput of the window Comprrrrua is fed inI0 open V a O g InmMtional,oaoba 1991.
M updowncountQ whose 6 -bit output is used to amad the [3] IEEE 1076.1 Design ObjectivesDocwnent, k o n 0.3,
gain of an "matic gain amp- (AGA). All Mocks IEEE(rP, from ftp.uanet pub/standards/IEEE)
except the AGAand the sine wave source arc modeled in 141 MHDLPnlimiMly Rrfcnncc M d ,Intenneaics, Jan
Vailog. The AGA has been modeled at two levels: a) a 1993.
mixed-signal model with sections in Spectre and Verilog. b) [5] Developmentof an Analog HDL. Chrish Kirfra et al.
fully in Vailog. This allows the usa to switch betweem IEEE. Custom integrated Conference.Rocham. 1989.
different levels of abstraction and to simulate the AGC [q Event-Driven Behavioral Simulation of Anabguc Trans-
system befaretbe circuit has ban designed. fcrFunctions.RobatA.Corall.EDAC1990.
The input signal hxn the Spam-sarrce is a [71 Spectre Manual, Cadure Design Sysmns, Inc.
sinewave. with a stepchange in thearnpiitude. [81 Arrist Refaence Manual. Cadence Design Syswns, Inc.

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