4 Addressing modes

• a constant;
• a register;
• a memory location.

Before considering in some detail the basic addressing modes, let us recall
that we have already discussed about this topic (even though not in terms
of addressing modes) when we approached the n-address machine subject.

Using examples, we saw that the operand can be in a register (we call this
to be the register addressing mode) or fully included in the instruction
(we call this direct addressing mode), and we tried to figure out the
impact over the code length and execution speed. We also discussed about
the PC-relative addressing and the use of displacements.

The most used addressing modes are presented below; a left arrow means
assignment, and M stands for memory. We use an array notation for
memory because we can view the memory as an array of bytes (or half-
words or words whichever you prefer, but the significance of the notation
must be very clear).

Register

ex: ADD r1, r2, r3

means: r1 r2 + r3
comment:used when a value is in a register.

Immediate (or literal)

ex: ADD r1, r2, 1

means: r1 r2 + 1
comment:used when a constant is needed.

Direct
ex: ADD r1, r2, (100)
means: r1 r2 + M[100]
comment: used to access static data; the address of the operand is include
in the instruction; space must be provided to accommodate a
whole address.

Register indirect (or register deferred)

ex: ADD r1, r2, (r3)

means: r1 r2 + M[r3]
comment: the register (r3 in this example) contains the address of a memory
location.

Virgil Bistriceanu Illinois Institute of Technology

64
 4.2 A classification of addressing modes

Displacement

ex: ADD r1, r2, 100(r3)

means: r1 r2 + M[r3 + 100]
comment: the address is the sum of the content of the register (the base)
and a constant from the instruction (the displacement); used to
access local variables on a stack or data structures. If the
displacement is zero, then it is the same as register indirect.

Memory indirect (or memory deferred)

ex: ADD r1, r2, @r3

means: r1 r2 + M[M[r3]]
comment: used in pointer addressing; if r3 contains the address of a
pointer p, then M[M[r3]] yields *p.

Indexed

ex: ADD r1, r2, (r3)[r4]

means: r1 r2 + M[r3 + size*r4]
comment: two registers are added to get a memory address, used in array
addressing with one register the base address of the array and the
other one the offset from the base to the desired element in the
array.

Autoincrement

ex: ADD r1, r2,(r3)+

means: r1 r2 + M[r3]
r3 r3 + s
comment: used to step through arrays, the first time it is used r3 points to
the beginning of the array; each access increments r2 with the
size s of an array’s element (s = 1 for byte, s = 2 for half-word,
etc.)

Autodecrement

ex: ADD r1, r2, -(r3)

means: r3 r3 - s
r1 r2 + M[r3]
comment: can be used like autoincrement, but to step through arrays in
reverse order. Together with the autoincrement mode it can be
used to implement a stack.

This list is far from being complete and you may wonder:

• why so many addressing modes?

• which are the minimum necessary addressing modes?

Virgil Bistriceanu Illinois Institute of Technology

65
4 Addressing modes

The answer to the first question is that addressing modes significantly

reduce instruction count of programs (keep in mind that this comes with
the increased hardware complexity). As for the second question the answer
depends upon the architecture; for a load-store architecture register,
immediate, and register deferred are sufficient. From this three we can
create the equivalent of other addressing modes although somehow
clumsily.

Example 4.5 ADDRESSING MODES:

Rewrite the following sequence of code using the register and register
deferred addressing modes:
/* a sequence that does nothing */
LOAD r1, (200)
ADD r3, r2, 10(r1)
AND r3, r2, @r2
...
...
...

Answer:
LOAD r1, 200# immediate;
LOAD r1, (r1)# register deferred
ADD r4, r2, 10# these two instructions replace the
ADD r3, r2, r4# ADD in the above sequence
LOAD r4, (r2)# and the two simulate the memory
AND r3, r2,(r4)# deferred addressing;

Observe that the IC is greater, and we need more registers; r4 is used to

calculate the displacement from r1 because r1 has not been destroyed; the
same remark holds for r2.

4.3 Immediate addressing:

Immediate values are used in:

• arithmetic operations:

ADD r1, 1 # increment register r

• comparisons, mostly in branches (although it depends upon the

branching method the architecture is using):

BEQ addr, r1, 2 #branch to addr if contents of r1 is 2;

• moves (immediate loads) to bring a constant into a register:

LOAD r1, 3

• In this case the immediate can be:

Virgil Bistriceanu Illinois Institute of Technology

66
 4.4 Displacement Addressing

• a constant written in the code (as in A + B + 4). The

values are usually small
• an address constant which can be large.

Again there is a tradeoff in deciding the maximum size immediate

operands should have in the instruction set:

• if the instruction size is fixed, a word (32 bit) for instance, then we
must compromise between the space we allocate for immediate
operands and the space we have to use for other fields (opcode,
registers, etc.)

• if the instruction size is variable, then an immediate could easily

accommodate an address.

4.4 Displacement Addressing:

Displacements are used in two ways:

• to access data in memory. The most common examples are

accessing the local variables in an activation record (AR), and
accessing the fields of a structure or record;

• to compute the target address for branches, jumps, calls in PC-

relative addressing.

Measurements show a wide distribution of displacements for the first

category, while for the second one most displacements are short (4 - 8 bits),
mainly due to the fact that usually the target of a branch (jump) is close to
the actual instruction. The tradeoffs in deciding the length of the
displacement are similar to those in deciding the length of immediate
operands.

Example 4.6 ADDRESSING MODES:

An array of two integers (an integer is 32 bits wide) is placed in memory

starting with address 100. Show how to increment the elements of the array
using displacement addressing. The memory is byte addressable.

Answer:
LOAD r1, 100# in r1 base
LOAD r2, 0(r1)# load the first element of array
ADD r2, r2, 1
STORE 0(r1), r2
LOADr2, 4(r1)# second word starts at 104
ADDr2, r2, 1
STORE 4(r1),r2

Virgil Bistriceanu Illinois Institute of Technology

67
4 Addressing modes

4.5 Indirect addressing (memory indirect)

In indirect addressing an address is considered to be the address of an

address, rather than the address of a value. Suppose we have the following
declarations in C:

int num, *ptr;

which declares num to be of type integer and ptr to be of type pointer to

integer. The following statement:

ptr = #

assigns the address of num to ptr. The logical structure created by the
above assignment is:

ptr num

Example 4.7 ADDRESSING MODES:

An integer is stored somewhere in the memory; a pointer to this integer is

at address 200. Use memory indirect addressing to increment the number.

Answer:
The relation between the pointer and the number is shown below:

the integer

200

If the machine supports the base address (200) to be in memory we have:

LOAD r2, 1
ADD r2, r2, @(200)
STORE@(200), r2

Virgil Bistriceanu Illinois Institute of Technology

68
 4.5 Indirect addressing (memory indirect)

If the base address is in a register, as most of the machines require

(machines that support this addressing mode):

LOAD r1, 200

LOAD r2, 1
ADD r2, r2, @(r1)
STORE@(r1), r2

This addressing mode is at the base of all virtual memory systems. It

allows to relocate programs without changing addresses in programs that
use them. The problem is that if we want to accept instructions that take
much more time to execute than their counterparts using simpler
addressing modes.

Example 4.8 MEMORY ACCESS:

How many memory accesses require the following instructions?

ADD r1, r2, r3

ADD r1, r2, (r3)
ADD r1, r2, @r3

Suppose every instruction is one word long, as well as every address.

Answer:
ADD r1, r2, r3
require only one memory access, reading the instruction;
ADD r1, r2, (r3)
require two memory accesses, the first to read the instruction and the other
one to read the value from memory location(s), whose address is in r3;
ADD r1, r2, @(r3)
three memory accesses are made in this case, the first to read the
instruction, the second to get M[r3], and the third one to get M[M[r3]].

While the implementation of this addressing mode has nothing difficult per
se, it raises some problems when we try to realize an efficient
implementation of the CPU: efficient pipelining require all instructions to
complete in the same number of clock cycles, which is difficult if we allow
instructions with different running times. Sure we could make all
instructions execute in the same number of clock cycles as the longest
running instruction, by simply inserting idle clock cycles. What an idea!
It’s wrong because it happens that the longest running instructions are not
the common cases. And it is precisely the common case that we want to
optimize.

Virgil Bistriceanu Illinois Institute of Technology

69
4 Addressing modes

4.6 Indexed addressing

Indexed addressing is provided in many machines for the convenience of

accessing arrays.

Example 4.9 ADDRESSING MODES

An array of two integers (each integer = 32 bits) is placed in memory

starting with address 100. Show how to increment the elements of the array
using indexed addressing.

Answer:
LOAD r1, 100 # in r1 base;
LOAD r2, 0 # the first index in array;
LOAD r3, 1
ADD r4, r3, (r1)[r2]
STORE (r1)[r2]
ADD r2, r2, 1 #index = index + 1
ADD r4, r3, (r1)[r2]
STORE (r1)[r2]

What is the price we have to pay to include this addressing mode in the
instruction set? Again we take into account how the addressing mode
effects the instruction length and the execution time as compared with
other addressing modes. We shall consider the instruction encoding and the
execution time as the parameters for this discussion.

Instruction encoding

For a three address machine (our examples so far are for such a machine)
we need four fields to encode the registers to be used:

• destination
• first source operand
• base
• index

For a 32 bit machine with fixed instruction size (one word), and a set of 32
registers, the necessary fields to encode the four registers require 4*5 = 20
bits. If we allow 6 bits for the opcode, then we still have 32 - (20+6) = 6
bits in the instruction. Do we need them? Of course we need them because
we have to encode two more things in the instruction:
• what kind of addressing mode are we using;
• what is the dimension size with which the index has to be
multiplied.

As long as we are concerned with the first problem we face yet another

Virgil Bistriceanu Illinois Institute of Technology

70
 4.6 Indexed addressing

problem, we didn’t discuss so far:

• do we allow all possible addressing modes we choose for our

instruction set apply for any operand?

If the answer is yes, then we have to specify, besides the

addressing mode, to which operand does this addressing mode
apply (we discuss about a register-memory machine, not about a
memory-memory machine, which allows all operands to have
their own addressing mode, an even more complicated problem).
For a three address machine, this requires two more bits in the
instruction.

In the case of a no answer, we have to decide to which operand the

addressing mode applies (in our examples, it was second source
operand); in this case we do not need extra encoding space,
because the operand to which the addressing mode applies is
implicitly specified, and thus can be hardwired.

To conclude this, we have to encode the addressing mode(s), and possibly

to which operand(s) it applies.

When we finally come to the second problem, specifying the size, we

realize that we need two bits because arrays can be formed with the
following data sizes:

• byte;
• half-word;
• word;
• double-word.

Certainly these two bits are needed, it would be much too restrictive not to
allow certain arrays of the basic data types. By now the following bits are
available:

32 - (20 + 6) - 2 = 4 bits

four bits with which we can try to encode the addressing mode and,
possibly, the operand to which it applies. A possible solution could be to
use two bits for encoding the addressing mode, thus allowing four
addressing modes, and the other two to specify to which of the three
operands applies. Should we allow more addressing modes, so we restrict
the number of operands to which that mode applies.

A final note: if we decide on fixed size instructions, then we have to drop

some addressing modes; for instance, the direct mode which requires a
whole absolute address to be provided in the instruction (unless the
instruction is wider than an address).
Virgil Bistriceanu Illinois Institute of Technology
71
4 Addressing modes

Execution time

Executing an instruction which allows one operand to be accessed using

indexing means that we have to compute the address as follows:

address = base_address + size * index

One integer multiplication and one integer addition have to be performed;

while the addition is not a problem, we have the ALU, the multiplication
requires special hardware, which can be included in the CPU, and this
hardware must be very fast. When we say hardware support we do not
necessarily mean a multiplier; the reason for this is that multiplication by
one (byte), two (half-word), four (word), eight (double-word) can be easily
done using left shifting by zero, one, two, and three positions respectively.

Example 4.10 SHIFT OPERATIONS:

A 16 bit register contains the binary configuration:

0000 0000 0001 0010

that is the register contains 1810 in an unsigned representation. Show the

register’s content after left shifting by one, two, and three positions
respectively, and the decimal representation of the number.

Answer:

one bit left shift:0000 0000 0010 0100

is the binary representation of 36:
36 = 18 * 2

two bits left shift:0000 0000 0100 1000

is the binary representation of 72:
72 = 18 * 4

three bits left shift:0000 0000 1001 0000

is the binary representation of 144:
144 = 18 * 8

While the shift hardware is simpler than that required for a full integer
multiplier, it still is an expensive resource (in terms of silicon area), and
will probably be introduced in the CPU only if the shift operation is a must.
Note that though most CPUs introduced in the recent years have shifters as
a part of the CPU, shift instructions are common in the instruction sets.

Computing an address of an operand using the addressing mode requires at

least two clock-cycles: one for multiplication (or shift) and another one for
addition. We should consider the adoption of this addressing mode
carefully, especially if we consider having instructions that execute in the

Virgil Bistriceanu Illinois Institute of Technology

72
 4.6 Indexed addressing

same number of clock-cycles.

Obviously this addressing mode is more expensive in clock-cycles than a

simpler addressing mode, like register deferred; indexed addressing can be
simulated using simpler addressing modes as the example 4.11 shows:

Example 4.11 ADDRESSING MODES

An array of two integers (each integer = 32 bits) is placed in memory

starting with address 100. Show how to increment each element of the
array using register deferred addressing mode.

Answer:
LOAD r1, 100# the base
LOAD r2, 1 # 1 will be used for increment
ADD r3, r2, (r1)
STORE (r1), r3
ADD r1, r1, 4# the next array element is at 104
ADD r3, r2, (r1)
STORE (r1), r3

Compare this example with example 4.9.

We conclude this session by underlining again the basic design principle:

make the common case fast. If this addressing mode is not very often
used (and indeed it is not, at least in common programs), it is probably wise
to dispose it, and try to optimize the common case(s) (which seems to be
immediate, displacement, register deferred).

Virgil Bistriceanu Illinois Institute of Technology

73