Lab1: Verilog Abstraction Levels

1.Write a Verilog code for a half adder using data flow abstraction and verify using
testbench

Design code:
module half_adder(input a,b,output sum,carry);
assign sum=a^b;
assign carry=a&b;
endmodule

Simulation code:
module half_adder_tb;
reg a,b;
wire sum,carry;
integer i;
half_adder DUT(.a(a),.b(b),.sum(sum),.carry(carry));
initial
begin
for(i=0;i<4;i=i+1)
begin
{a,b}=i;
#10;
end
end
initial $monitor("input a=%b,b=%b,output sum=%b,carry=%b",a,b,sum,carry);
initial #100 $finish;
endmodule
Synthesis Circuit:

Simulation waveform:

Transcript:
2. Write a Verilog code for full adder using two half adders and verify using testbench
Design code:
module half_adder(input a,b, output s,c);
assign s= a^b;
assign c= a&b;
endmodule
/////////////////
module full(input a_in,b_in,c_in, output sum_out,carry_out);
wire w1,w2,w3;
half_adder HA1(.a(a_in),.b(b_in),.s(w1),.c(w2));
half_adder HA2(.a(w1),.b(c_in),.s(sum_out),.c(w3));
or OR1(carry_out,w2,w3);
endmodule
Simulation code:
module full_tb;
reg a,b,c;
wire sum,carry;
integer i;
full DUT(.a_in(a),.b_in(b),.c_in(c),.sum_out(sum),.carry_out(carry));
initial
begin
for(i=0;i<8;i=i+1)
begin
{a,b,c} = i;
#10;
end
end
initial
$monitor(" a= %b, b= %b, c= %b, sum= %b, carry= %b ", a,b,c,sum,carry);
initial #100 $finish;
endmodule
Synthesis circuit:

Simulation waveform:

Transcript:
3 Write a Verilog code for full adder using data flow abstraction and verify using testbench
Design code:
module fulladder_addr(input a,b,cin, output sum,carry);
assign sum = a^b^cin;
assign carry = (a&b)|(b&cin)|(cin&a);
endmodule
Simulation code:
module fulladder_addr_tb;
reg a,b,cin;
wire sum,carry;
integer i;
fulladder_addr DUT(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
begin
for(i=0;i<8;i=i+1)
begin
{a,b,cin}=i;
#10;
end
end
initial
$monitor("a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry);
initial #100 $finish;
endmodule
Synthesis circuit:

Simulation waveform:

Transcript:
4 Write a Verilog code for 2:4 decoder using data flow abstraction and verify using
testbench
Design code:
module dec2_4(input a_in,b_in, output c_out,d_out,e_out,f_out);
assign c_out = (~a_in) & (~b_in);
assign d_out = (~a_in) & b_in;
assign e_out = (a_in) & (~b_in);
assign f_out = (a_in) & (b_in);
endmodule
Simulation code:
module dec2_4tb();
reg a, b;
wire c, d, e, f;
integer i;
dec2_4 DUT(.a_in(a), .b_in(b), .c_out(c), .d_out(d), .e_out(e), .f_out(f));
initial
begin
for(i=0;i<4;i=i+1)
begin
{a,b} = i;
#10;
end
end
initial
$monitor("a = %b,b= %b, c = %b, d = %b, e = %b, f = %b", a, b, c, d, e, f);
initial
#100 $finish;
Endmodule
Synthesis circuit:

Simulation waveform:

Transcript:
5 Write a Verilog code for 4:1 mux using 2:1 mux using data flow abstraction and verify
using testbench
Design code:
module mux2(a,b,s,y);
input a,b,s;
output y;
assign y= s ? b : a;
endmodule
//////////////////////
module mux4(input p,q,r,t,s0,s1, output y);
wire w1,w2;
mux2 M1(.a(p),.b(q),.s(s0),.y(w1));
mux2 M2(.a(r),.b(t),.s(s0),.y(w2));
mux2 M3(.a(w1),.b(w2),.s(s1),.y(y));
endmodule
Simulation code:
module mux4_tb;
reg i0,i1,i2,i3,s0,s1;
wire y;
integer i;
mux4 DUT(.p(i0),.q(i1),.r(i2),.t(i3),.s0(s0),.s1(s1),.y(y));
initial
begin
for(i=0;i<64;i=i+1)
begin
{i0,i1,i2,i3,s0,s1}= i;
#1;
end
end
initial
$monitor("i0=%b,i1=%b,i2=%b,i3=%b,s0=%b,s1=%b,y=%b",i0,i1,i2,i3,s0,s1,y);
initial #100 $finish;
endmodule
Synthesis circuit:

Simulation waveform:
Transcript:
6 Write a Verilog code for bidirectional buffer using dataflow abstraction and verify using
testbench
Design code:
module t_buf(input a,ctrl, output y);
assign y=ctrl?a:1'bz;
endmodule
/////////////
module t_buf2(input b,ctrl,output y);
assign y=~ctrl?b:1'bz;
endmodule
////////////
module bi_buffer(input ctrl,inout a,b);
t_buf BUF1(.a(a),.ctrl(ctrl),.y(b));
t_buf2 BUF2(.b(b),.ctrl(ctrl),.y(a));
endmodule
Simulation code:
module bi_buffer_tb;
reg ctrl;
reg tempa,tempb;
wire a,b;
integer i;
bi_buffer DUT(.ctrl(ctrl),.a(a),.b(b));
assign a=ctrl?tempa:1'bz;
assign b=~ctrl?tempb:1'bz;
initial
begin
for(i=0;i<8;i=i+1)
begin
{tempa,tempb,ctrl}= i;
#10;
end
end
initial
$monitor("ctrl=%b,a=%b,b=%b",ctrl,a,b);
initial #80 $finish;
endmodule
Synthesis circuit:

Simulation waveform:

Transcript:
7 Write a Verilog code and testbench for ripple carry adder using one bit full adder
Design code:
module fulladder(a,b,ci,s,c);
input a,b,ci;
output s,c;
assign s=a^b^ci;
assign c=a&b|b&ci|ci&a;
endmodule

module ripple(a,b,c,s,co);
input [3:0] a;
input [3:0] b;
input c;
output [3:0] s;
output co;
wire w1,w2,w3;

fulladder A1(.a(a[0]),.b(b[0]),.ci(c),.s(s[0]),.c(w1));
fulladder A2(.a(a[1]),.b(b[1]),.ci(w1),.s(s[1]),.c(w2));
fulladder A3(.a(a[2]),.b(b[2]),.ci(w2),.s(s[2]),.c(w3));
fulladder A4(.a(a[3]),.b(b[3]),.ci(w3),.s(s[3]),.c(co));
endmodule
Simulation code:
module ripple_tb;
reg [3:0]a,b;
reg ci;
wire [3:0]s;
wire co;
integer i;
ripple DUT(.a(a),.b(b),.c(ci),.s(s),.co(co));
initial
begin
a=4'b0000;
b=4'b0000;
ci=0;
end
initial
begin
for(i=0;i<256;i=i+1)
begin
{a,b}=i;
#10;
end
end
initial
$monitor("a=%b,b=%b,ci=%b,s=%b,co=%b", a,b,ci,s,co);
initial #2560 $finish;
endmodule
Synthesis circuit:

Simulation waveform:
Transcript:
8 Write a Verilog code for 4:1 mux using 2:4 decoder and tri state buffer and verify using
testbench
Design code:
module decoder(a,b,d0,d1,d2,d3);
input a,b;
output d0,d1,d2,d3;
assign d0=(~a&~b);
assign d1=(~a&b);
assign d2=(a&~b);
assign d3=(a&b);
endmodule
/////////
module t_buff(input x,en,output w);
assign w=en?x:1'bz;
endmodule
//////////
module dec_mux(input i0,i1,i2,i3,s0,s1,output y);
wire w1,w2,w3,w4;
decoder DEC1(.a(s0),.b(s1),.d0(w1),.d1(w2),.d2(w3),.d3(w4));
t_buff BUFF1(.x(i0),.en(w1),.w(y));
t_buff BUFF2(.x(i1),.en(w2),.w(y));
t_buff BUFF3(.x(i2),.en(w3),.w(y));
t_buff BUFF4(.x(i3),.en(w4),.w(y));
endmodule
Simulation code:
module dec_mux_tb;
reg p,q,r,t,s0,s1;
wire y;
integer i;
dec_mux DUT(.i0(p),.i1(q),.i2(r),.i3(t),.s0(s0),.s1(s1),.y(y));
initial
begin
for(i=0;i<64;i=i+1)
begin
{p,q,r,t,s0,s1}= i;
#1;
end
end
initial
$monitor("p=%b,q=%b,r=%b,t=%b,s0=%b,s1=%b,y=%b",p,q,r,t,s0,s1,y);
initial #100 $finish;
endmodule
Synthesis circuit:

Simulation waveform:
Transcript:
9 Write a Verilog code for 8:3 priority encoder using structural modelling and verify using
testbench
Design code:
module priority_ckt(i,h,idel);
input [7:0]i;
output [7:0]h;
output idel;
assign h[7]=i[7];
assign h[6]=i[6]&~i[7];
assign h[5]=i[5]&~i[6]&~i[7];
assign h[4]=i[4]&~i[5]&~i[6]&~i[7];
assign h[3]=i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign h[2]=i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign h[1]=i[1]&~i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign h[0]=i[0]&~i[1]&~i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
assign idel=~i[0]&~i[1]&~i[2]&~i[3]&~i[4]&~i[5]&~i[6]&~i[7];
endmodule
/////////
module encoder(b,y);
input [7:0]b;
output[2:0]y;
or OR1(y[0],b[1],b[3],b[5],b[7]);
or OR2(y[1],b[2],b[3],b[6],b[7]);
or OR3(y[2],b[4],b[5],b[6],b[7]);
endmodule
////////
module priority_en(p,i,b,x,z);
input [7:0]x,i,b;
output [2:0]p;
output z;
wire [7:0]w;
priority_ckt PC(.i(x),.h(w),.idel(z));
encoder EC(.b(w),.y(p));
endmodule
Simulation code:
module priority_en_tb;
reg [7:0]s,r,t;
wire [2:0]f;
wire idel;
integer i;
priority_en DUT(.x(s),.p(f),.i(r),.b(t),.z(idel));
initial
begin
for(i=0;i<256;i=i+1)
begin
{s}=i;
#10;
end
end
initial
$monitor("s=%b,f=%b,idel=%b",s,f,idel);
initial #2560 $finish;
endmodule
Synthesis circuit:
Simulation waveform:

Transcript: