Phase-Locked Loop Design and Applications

PLL Linear Model

Summarized by Awen Sung

Nov. 20, 2022
 Phase-Locked Loops

 Classification of Phase-Locked Loop

 Linear PLL: input is analog, circuit is analog.
 Digital PLL: input is digital, circuit is partial digital, partial analog.
 All Digital PLL: input can be digital or analog, circuit is all digital.

 Linear Phase-Locked Loop

Assume
𝑢1 𝑡 = 𝐴1 𝑠𝑖𝑛(𝜔1 𝑡 + 𝜃1 𝑡 )
𝑢2 𝑡 = 𝐴2 𝑐𝑜𝑠(𝜔2 𝑡 + 𝜃2 𝑡 )

Let’s use 𝜔2 𝑡 as reference.

𝜔1 𝑡 + 𝜃1 𝑡 = 𝝎𝟐 𝒕 + 𝜔1 − 𝜔2 𝑡 + 𝜃1 𝑡 = 𝝎𝟐 𝒕 + ∆𝝎𝒕 + 𝜽𝟏 𝒕 = 𝝎𝟐 𝒕 + 𝜽′𝟏 𝒕
The phase difference (Excess phase) between 𝑢1 (𝑡) and 𝑢2 (𝑡) is given by
𝜽𝒆 𝒕 = 𝜽′𝟏 𝒕 − 𝜽𝟐 (𝒕)
 Phase-Locked Loops (Phase Detector)
 Multiplier Phase Detector
𝑢𝑑 𝑡
= 𝐾𝑚 ∙ 𝑢1 𝑡 ∙ 𝑢2 𝑡
= 𝐾𝑚 𝐴1 𝐴2 ∙ 𝑠𝑖𝑛 𝜔2 𝑡 + 𝜃1′ 𝑡 ∙ 𝑐𝑜𝑠 𝜔2 𝑡 + 𝜃2 𝑡
= 𝐾𝑑 ∙ {𝑠𝑖𝑛 𝜽′𝟏 𝒕 − 𝜽𝟐 𝒕 + 𝑠𝑖𝑛[𝟐𝝎𝟐 𝒕 + 𝜃1′ 𝑡 + 𝜃2 (𝑡)]}

Assume the high frequency term (𝟐𝝎𝟐 𝒕) is filtered out by LF

𝑢𝑓 𝑡 = 𝐾𝑑 𝑠𝑖𝑛(𝜽𝒆 (𝒕))
1
where 𝐾𝑚 : multiplier gain, 𝐾𝑑 = 2 𝐾𝑚 𝐴1 𝐴2 : phase detector gain

• PD is used to extract the phase difference between VCO and reference

clock.
• If the VCO output 𝑢2 𝑡 is a square wave, we can expand it with Fourier
series, and analyze the loop behavior in the same way.
• 𝑢𝑑 𝑡 is linear proportional to 𝜃𝑒 (𝑡) and multiplier gain 𝐾𝑚 when the phase
difference is small.
 Phase-Locked Loops (LF & VCO)
 Loop Filter
Loop filter is usually a low-pass filter, typically a 1st order filter.
The loop filter output, 𝑢𝑓 𝑡 is the convolution of 𝑢𝑑 (𝑡) and 𝑓 𝑡 ,
𝑡
𝑢𝑓 𝑡 = න 𝑓 𝑡 − 𝜏 𝑢𝑑 𝜏 𝑑𝜏
0
Using the Laplace transform,
𝑈𝑓 𝑠 = 𝐹 𝑠 𝑈𝑑 𝑠
 Voltage Controlled Oscillator
The output frequency of VCO can be varied by the input control voltage.
The angular frequency of the VCO is given by
𝜔0 𝑡 = 𝜔2 + 𝐾0 𝑢𝑓 𝑡
where 𝜔2 is the free running frequency of the VCO, 𝐾0 is the VCO gain (rad/V).
The phase of 𝜔0 (𝑡) is 𝑡 𝑡
න 𝜔0 𝜏 𝑑𝜏 = 𝜔2 𝑡 + 𝐾0 න 𝑢𝑓 𝜏 𝑑𝜏
0 0
𝑡
𝐾0
𝜃2 𝑡 = 𝐾0 න 𝑢𝑓 𝜏 𝑑𝜏 ; 𝜃2 𝑠 = 𝑈 (𝑠)
0 𝑠 𝑓
 Linear Model of a Type-I PLL (1/2)

• The open-loop transfer function is given by

∅𝑜𝑢𝑡 1 𝐾𝑉𝐶𝑂
𝐻 𝑠 ȁ𝑜𝑝𝑒𝑛 = 𝑠 ȁ𝑜𝑝𝑒𝑛 = 𝐾𝑃𝐷 ∙ 𝑠 ∙
∅𝑖𝑛 1+𝜔 𝑠
𝐿𝑃𝐹

revealing the poles at 𝑠 = −𝜔𝐿𝑃𝐹 and 𝒔 = 𝟎.

Since the loop gain contains a pole at the origin, the system is called “type-I”.

• Owing to the pole at the origin, the loop gain goes to infinity as 𝑠 approaches
to zero. Thus, the PLL ensures that the change in ∅𝑜𝑢𝑡 is exactly equal to the
change in ∅𝑖𝑛 as 𝑠 goes to zero.
 Linear Model of a Type-I PLL (2/2)

• The closed-loop transfer function can be written as

∅𝑜𝑢𝑡 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝜔𝑜𝑢𝑡
𝐻 𝑠 ȁ𝑐𝑙𝑜𝑠𝑒 = 𝑠 ȁ𝑐𝑙𝑜𝑠𝑒 = 𝑠2
= 𝑠
∅𝑖𝑛 +𝑠+𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝜔𝑖𝑛
𝜔𝐿𝑃𝐹

If 𝑠 → 0, 𝐻 𝑠 → 1 because of the infinite loop gain.

• Since a change in 𝜔𝑜𝑢𝑡 must be accompanied by a change in 𝑉𝑐𝑜𝑛𝑡 ,

𝑉
we have 𝐻 𝑠 = 𝐾𝑉𝐶𝑂 ∙ 𝜔𝑐𝑜𝑛𝑡 (𝑠).
𝑖𝑛
The response of 𝑉𝑐𝑜𝑛𝑡 to variations in 𝜔𝑖𝑛 indeed yields the response of the
close-loop system.
 PLL Basic Model

If the PLL is locked,

𝑉𝑑 𝑠 = 𝐾𝑑 𝜃𝑖 𝑠 − 𝜃𝑜 𝑠 = 𝐾𝑑 𝜃𝑒 𝑠
𝑉𝑐 𝑠 = 𝐹 𝑠 𝑉𝑑 𝑠
𝐾𝑜 𝑉𝑐 𝑠
𝜃𝑜 𝑠 = 𝑠
Thus,
𝜃𝑜 𝐾 𝐾𝑑 𝐹 𝑠
𝑜
𝑠 = 𝑠+𝐾 =𝐻 𝑠
𝜃𝑖 𝑜 𝐾𝑑 𝐹 𝑠
𝜃𝑒 𝑠
𝑠 = 𝑠+𝐾 =1−𝐻 𝑠
𝜃𝑖 𝑜 𝐾𝑑 𝐹 𝑠
𝑉𝑐 𝑠𝐾 𝐹 𝑠 𝑠
𝑠 = 𝑠+𝐾 𝑑𝐾 =𝐾 𝐻 𝑠
𝜃𝑖 𝑜 𝑑𝐹 𝑠 𝑜

• 𝜃𝑒 is the phase error, 𝐾𝑑 is the phase detector gain, 𝐾𝑜 is the VCO gain, and
𝐻 𝑠 is the closed-loop transfer function.
 PLL Waveforms in Locked Conditions

𝜔1 −𝜔0
V1 = 𝐾𝑉𝐶𝑂
𝑉 𝜔1 −𝜔0
∅0 = 𝐾 1 = 𝐾
𝑃𝐷 𝑃𝐷 𝐾𝑉𝐶𝑂

• As the input frequency of the PLL varies, so does the phase error.
• To minimize phase error, 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 must be maximized.

• The exact equality of the input and output frequencies of a PLL in the locked
condition is a critical attribute.
• The equality would not exist if the PLL compared the input and output
frequencies rather than phases.
 Response of a PLL to a Phase Step

Let
𝑉𝑖𝑛 𝑡 = 𝑉𝐴 cos 𝜔1 𝑡
𝑉𝑜𝑢𝑡 𝑡 = 𝑉𝐵 cos 𝜔1 𝑡 + ∅0

At 𝑡1 (a phase step enters)

∅𝑖𝑛 = 𝜔1 𝑡 + ∅𝟏 𝒖(𝒕 − 𝒕𝟏 )

• The growing phase difference between the input and output then creates
wide pulses at the output of the PD ⇒ 𝜔𝑜𝑢𝑡 changes.
• If the loop is locked, 𝜔𝑜𝑢𝑡 = 𝜔1, all of the parameters assume their original
value.
∞
‫∅ = 𝑡𝑑 𝑡𝑢𝑜𝜔 𝑡׬‬1 𝑉𝑜𝑢𝑡 𝑡 = 𝑉𝐵 cos(𝜔1 𝑡 + ∅0 + ∅𝟏 𝒖(𝒕 − 𝒕𝟏 ))
1
 Response of a PLL to a Frequency Step

• The PD generates increasingly wider pulses, and 𝑉𝐿𝑃𝐹 rises with time.
• As 𝜔𝑜𝑢𝑡 approaches 𝜔1 + ∆𝜔, the width of the pulses generated by the PD
decreases.
𝜔1 + ∆𝝎 − 𝜔0
𝑉𝑐𝑜𝑛𝑡 =
𝐾𝑉𝐶𝑂
Response of a PLL to an External Step on Control Line

Initial condition
𝜔𝑜𝑢𝑡 = 𝜔𝑖𝑛
𝜔𝑖𝑛 −𝜔0
𝑉𝑐𝑜𝑛𝑡 =
𝐾𝑉𝐶𝑂
𝜔𝑖𝑛 −𝜔0
𝑉𝐿𝑃𝐹 = − 𝑉1
𝐾𝑉𝐶𝑂
𝑉𝐿𝑃𝐹 𝜔𝑖𝑛 −𝜔0 𝑉
∆∅1 = =𝐾 −𝐾1
𝐾𝑃𝐷 𝑃𝐷 𝐾𝑉𝐶𝑂 𝑃𝐷

′ 𝜔𝑖𝑛 −𝜔0
If 𝑉𝑒𝑥 steps from 𝑉1 to 𝑉2 at 𝑡 = 𝑡1 : 𝑉𝑐𝑜𝑛𝑡 = 𝑉𝐿𝑃𝐹 + 𝑉2 = + (𝑉2 − 𝑉1 )
𝐾𝑉𝐶𝑂
′
𝜔𝑜𝑢𝑡 = 𝜔0 + 𝐾𝑉𝐶𝑂 𝑉𝑐𝑜𝑛𝑡 = 𝜔𝑖𝑛 + 𝐾𝑉𝐶𝑂 (𝑉2 − 𝑉1 )
When returning to lock: 𝜔𝑜𝑢𝑡 = 𝜔𝑖𝑛
𝜔𝑖𝑛 −𝜔0 𝜔𝑖𝑛 −𝜔0 𝑉
𝑉𝐿𝑃𝐹 = 𝐾𝑉𝐶𝑂
− 𝑉2 ∆∅2 = 𝐾 −𝐾2
𝑃𝐷 𝐾𝑉𝐶𝑂 𝑃𝐷

The are under 𝜔𝑜𝑢𝑡 during the transient is equal to the change in the output phase
and hence the change in the phase error.
∞ 𝑽𝟏 −𝑽𝟐
∆∅ = ‫׬‬0 𝜔𝑜𝑢𝑡 𝑑𝑡 = ∆∅2 − ∆∅1 = 𝑲𝑷𝑫
 Dynamics of Simple PLL
As 2
𝜃𝑜 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝜔𝑛 𝑠𝜃𝑜 𝑠 𝜔𝑜𝑢𝑡 𝑠
𝐻 𝑠 ȁ𝑐𝑙𝑜𝑠𝑒𝑑 = = 𝑠2
= 2 = =
𝜃𝑖 +𝑠+𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝑠 2 +2𝜁𝜔𝑛 𝑠+𝜔𝑛 𝑠𝜃𝑖 𝑠 𝜔𝑖𝑛 𝑠
𝜔𝐿𝑃𝐹

𝑉𝑐𝑜𝑛𝑡 1 𝜔𝐿𝑃𝐹
𝐻 𝑠 = 𝐾𝑉𝐶𝑂 𝑠 𝜔𝑛 = 𝜔𝐿𝑃𝐹 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝜁=2
𝜔𝑖𝑛 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂

⇒ Monitoring the response of 𝑉𝑐𝑜𝑛𝑡 to variations in 𝜔𝑖𝑛 yields the response of

the closed-loop system

The two poles of the closed-loop system

𝑠1,2 = −𝜁𝜔𝑛 ± 𝜁 2 − 1 𝜔𝑛2 = −𝜁 ± 𝜁 2 − 1 𝜔𝑛
• If 𝜁 > 1, both poles are real, the transient response contains two exponential with
time constants 1/𝑠1 and 1/𝑠2 .
• If 𝜁 < 1, the poles are complex and the response to an input frequency step
𝜔𝑖𝑛 = ∆𝜔𝑢 𝑡 is

𝜁
𝜔𝑜𝑢𝑡 𝑡 = 1 − 𝑒 −𝜁𝜔𝑛 𝑡 cos 𝜔𝑛 1 − 𝜁 2 𝑡 + sin 𝜔𝑛 1 − 𝜁 2 𝑡 ∆𝜔𝑢 𝑡
1−𝜁 2
1
= 1− 𝑒 −𝜁𝜔𝑛 𝑡 sin 𝜔𝑛 1 − 𝜁 2 𝑡 + 𝜃 Δ𝜔𝑢 𝑡
1−𝜁 2

𝜃 = sin−1 1 − 𝜁 2
 Settling Speed of PLL
The step response of PLL contains a sinusoidal component with a frequency
𝜔𝑛 1 − 𝜁 2 that decays with a time constant 𝜁𝜔𝑛 −1 . To accelerate the settling
speed, 𝜁𝜔𝑛 must be maximized.
1 𝜔𝐿𝑃𝐹 𝟏
𝜻𝝎𝒏 = 𝜔𝐿𝑃𝐹 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 ∙ = 𝝎
2 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝟐 𝑳𝑷𝑭

• The lower 𝜔𝐿𝑃𝐹 , the greater the suppression of the high frequency components produced
by the PD but the longer the settling time constant.
• Trade-off between the settling speed and the ripple on the VCO control line.

Example.
Suppose a cellular telephone incorporates a 900-MHz phase-locked loop to generate the
carrier frequencies. If 𝜔𝐿𝑃𝐹 = 2𝜋 ∙ 20𝑘𝐻𝑧 and the output frequency is to be changed from
901 MHz to 901.2 MHz. The settling time within 100 Hz accuracy is

1 − 𝑒 −𝜁𝜔𝑛 𝑡𝑠 sin 𝜔𝑛 1 − 𝜁 2 𝑡𝑠 + 𝜃 ∙ 200𝑘𝐻𝑧 = 200𝑘𝐻𝑧 − 100𝐻𝑧

100𝐻𝑧
𝑒 −𝜁𝜔𝑛 𝑡𝑠 sin 𝜔𝑛 1 − 𝜁 2 𝑡𝑠 + 𝜃 = 𝑒 −𝜁𝜔𝑛 𝑡𝑠 = 0.0005
200𝑘𝐻𝑧

7.6 15.2
𝑡𝑠 = = = 0.12 𝑚𝑠
𝜁𝜔𝑛 𝜔𝐿𝑃𝐹
Stability Behavior of Type I PLLs
Underdamped Response of a 2nd-Order System
2nd-Order PLL
2nd-Order PLL Response
Charge Pump PLL Linear Model
One Pole One Zero Low Pass Filter
Charge-Pump Phase-Locked Loops
Charge-Pump Phase-Locked Loops
Major Issues of Type II Charge-Pump PLL
3rd-Order Charge-Pump PLLs
3rd-Order Charge-Pump PLLs
Multi-Path Charge-Pump Filter
PLL Based Frequency Synthesizer
Generic PLL Linear Model
2nd-Order PLL with 1st-Order Loop Filter
Stability Analysis
3rd-Order PLL Stability Analysis
3rd-Order PLL Parameter Design
2nd-Order Loop Filter Design
Open Loop Bandwidth and Phase Margin
 Loop Filter Parameter Design
 Given loop bandwidth ωc and phase margin ψm,, let
 Comparisons of Type I and Type II PLL
• Root locus of Type I and Type II PLL

• Bode Plot of Type I and Type II PLL

Reference Spur
4th-Order PLL with 3rd-Order Loop Filter
Phase Noise Performance
Jitter in PLLs
Phase Noise Performance
PLL Tracking Performance
PLL Tracking Performance
Delay Locked Loops