1) Please describe ASIC Design flow, each and every step in Frontend and Backend flows.

How would the flow vary as we move from one node to another node, means from one
gatelength technology to another, say from 14nm to 7nm technology ?

DESIGN SPECIFICATION
This is the stage at which we define what are the important parameters of
the system/design that you are planning to design. A simple example would
be: I want to design a counter; it should be 4 bit wide, should have
synchronous reset, with active high enable; when reset is active, counter
output should go to "0".

VALIDATING SPECS
In this stage the design specification is minimized if required using Boolean
Algebra, K Map and Quine Mccluskey Method.

ARCHITECTURE DESIGN / HIGH LEVEL DESIGN

This is the stage at which you define various blocks in the design and how
they communicate. Let's assume that we need to design a microprocessor:
high level design means splitting the design into blocks based on their
function; in our case the blocks are registers, ALU, Instruction Decode,
Memory Interface, etc.

MICROARCHITECTURE / LOW LEVEL DESIGN

Low level design or Micro design is the phase in which the designer
describes how each block is implemented. It contains details of State
machines, counters, Mux, decoders, internal registers. It is always a good
idea to draw waveforms at various interfaces. This is the phase where one
spends lot of time.

RTL CODING
RTL is an acronym for register transfer level. This implies that your VHDL/
Verilog code describes how data is transformed as it is passed from
register to register. The transforming of the data is performed by the
combinational logic that exists between the registers. In RTL coding, Micro
design is converted into Verilog/VHDL code, using synthesizable constructs
of the language.
LOGIC SYNTHESIS
Logic synthesis is the process of converting a high-level description of
design into an optimized gate-level representation. Logic synthesis uses a
standard cell library which have simple cells, such as basic logic gates like
and, or, and nor, or macro cells, such as adder, muxes, memory, and flip-
flops.

FUNCTIONAL VERIFICATION
Functional Verification is defined as the process of verifying that an RTL
(Synthesizable Verilog, VHDL, SystemVerilog) design meets its specification
from a functional perspective. Functional verification establishes that the
design under test (DUT) implements the functionality of the specification
correctly. This is done by generating testbench.
SCAN INSERTION (DFT)
Scan chain is a technique used in design for testing. The objective is to make
testing easier by providing a simple way to set and observe every flip-flop in
an IC. ... When this signal is asserted, every flip-flop in the design is
connected into a long shift register.
STA/ FORMAL VERIFICATION
The purpose of formal verification is to determine whether or not a particular
design satisfies a set of predetermined requirements, properties, or
conditions. It is a sum of a number of different techniques that employ the
use of static analysis and mathematical or algorithmic calculations in order
to determine just how correct or incorrect a piece of ASIC block or SoC is.

PHYSICAL DESIGN
In integrated circuit design, physical design is a step in the
standard design cycle which follows after the circuit design.
These design flows lay down the process and guide-lines/framework for that
phase. The physical design flow uses the technology libraries that are
provided by the fabrication houses.

FABRICATION
The fabrication cycle of VLSI chips consists of a sequential set of basic steps
which are crystal growth and wafer preparation, epitaxy, dielectric and
polysilicon film deposition, oxidation, lithography, and dry etching. During
the fabrication process, the devices are created on the chip.

ATPG TESTING
ATPG (acronym for both Automatic Test Pattern Generation
and Automatic Test Pattern Generator) is an electronic design
automation method/technology used to find an input (or test) sequence that,
when applied to a digital circuit, enables automatic test equipment to
distinguish between the correct circuit behavior and the faulty circuit behavior
caused by defects. The generated patterns are used to test semiconductor
devices after manufacture, or to assist with determining the cause of failure
failure analysis.
PACKAGING
Packaging format influences, size, cost, electrical performance, mechanical
performance, and assembly requirements. System To ASIC uses world-
class packaging facilities all over the world to assure high quality redundant
assembly capability. These facilities provide rigorous package reliability
qualification such as AEC-Q100, and maintain stringent quality standards
such as IATF 16949, allowing delivery into very demanding markets. From
state of the art chip scale package profiles, to plastic leadless (QFN, SLP,
MLF), to die in waffle pack, STA provides packaging solutions that meet your
budget, performance, and size objectives.

PROTOTYPE TESTING
FPGA prototyping (also called ASIC prototyping or ASIC emulation)
consists of implementing a portion or the totality of an ASIC design into
an FPGA in order to validate its functionality.With the high non-recurring cost
of manufacturing an ASIC, revising an ASIC to fix broken functionality is a
very costly process.

PRODUCTION
Different techniques are used to produce ASICs. These include a
combination of acid baths, photolithography, furnace annealing, ion
implantation, and metallic sputter deposition. Once manufactured, the wafer
is then tested for fabrication errors. Scan testing is used to check failures for
each individual gate.

BY DECREASING THE GATELENGTH SAY FROM 14nm and 7nm

Technology Power consumption and area consumption decreases and
speed increases. The impact on the Back End (BE) is that we are using
more sets of tools/features to get the job done, and it takes longer to signoff
a design (both tool runtime and engineers’ work time).
Impact and challenges are

• DOUBLE PATTERNING
• EXTRACTION
• ROUTING
• TIMING

2) Please describe FPGA Design flow in detail. How is it different from ASIC Design flow ?

Design Entry
There are different techniques for design entry. Schematic based, Hardware
Description Language and combination of both etc. . Selection of a method
depends on the design and designer. If the designer wants to deal more with
Hardware, then Schematic entry is the better choice. When the design is
complex or the designer thinks the design in an algorithmic way then HDL is
the better choice. Language based entry is faster but lag in performance and
density. HDLs represent a level of abstraction that can isolate the designers
from the details of the hardware implementation. Schematic based entry
gives designers much more visibility into the hardware. It is the better choice
for those who are hardware oriented. Another method but rarely used is
state- 4 machines. It is the better choice for the designers who think the
design as a series of states. But the tools for state machine entry are limited.
In this documentation we are going to deal with the HDL based design entry.

Synthesis
The process which translates VHDL or Verilog code into a device netlist
formate. i.e a complete circuit with logical elements( gates, flip flops, etc…)
for the design.If the design contains more than one sub designs, ex. to
implement a processor, we need a CPU as one design element and RAM as
another and so on, then the synthesis process generates netlist for each
design element Synthesis process will check code syntax and analyze the
hierarchy of the design which ensures that the design is optimized for the
design architecture, the designer has selected. The resulting netlist(s) is
saved to an NGC (Native Generic Circuit) file (for Xilinx® Synthesis
Technology (XST)).

Implementation
This process consists a sequence of three steps
1. Translate
2. Map
3. Place and Route

Translate process combines all the input netlists and constraints to a logic
design file. This information is saved as a NGD (Native Generic Database)
file. This can be done using NGD Build program. Here, defining constraints
is nothing but, assigning the ports in the design to the physical elements (ex.
pins, switches, buttons etc) of the targeted device and specifying time
requirements of the design. This information is stored in a file named UCF
(User Constraints File). Tools used to create or modify the UCF are PACE,
Constraint Editor etc.

Map process divides the whole circuit with logical elements into sub blocks
such that they can be fit into the FPGA logic blocks. That means map
process fits the logic defined by the NGD file into the targeted FPGA
elements (Combinational Logic Blocks (CLB), Input Output Blocks (IOB))
and generates an NCD (Native Circuit Description) file which physically
represents the design mapped to the components of FPGA. MAP program
is used for this purpose.

Place and Route

PAR program is used for this process. The place and route process places
the sub blocks from the map process into logic blocks according to the
constraints and connects the logic blocks. Ex. if a sub block is placed in a
logic block which is very near to IO pin, then it may save the time but it may
effect some other constraint. So trade off between all the constraints is taken
account by the place and route process The PAR tool takes the mapped
NCD file as input and produces a completely routed NCD file as output.
Output NCD file consists the routing information.

Device Programming
Now the design must be loaded on the FPGA. But the design must be
converted to a format so that the FPGA can accept it. BITGEN program deals
with the conversion. The routed NCD file is then given to the BITGEN
program to generate a bit stream (a .BIT file) which can be used to configure
the target FPGA device. This can be done using a cable. Selection of cable
depends on the design.
Design Verification
Verification can be done at different stages of the process steps.

Behavioral Simulation (RTL Simulation)

This is first of all simulation steps; those are encountered throughout the
hierarchy of the design flow. This simulation is performed before synthesis
process to verify RTL (behavioral) code and to confirm that the design is
functioning as intended. Behavioral simulation can be performed on either
VHDL or Verilog designs. In this process, signals and variables are
observed, procedures and functions are traced and breakpoints are set. This
is a very fast simulation and so allows the designer to change the HDL code
if the required functionality is not met with in a short time period. Since the
design is not yet synthesized to gate level, timing and resource usage
properties are still unknown.

Functional simulation (Post Translate Simulation)

Functional simulation gives information about the logic operation of the
circuit. Designer can verify the functionality of the design using this process
after the Translate process. If the functionality is not as expected, then the
designer has to made changes in the code and again follow the design flow
steps. Static Timing Analysis This can be done after MAP or PAR processes
Post MAP timing report lists signal path delays of the design derived from
the design logic. Post Place and Route timing report incorporates timing
delay information to provide a comprehensive timing summary of the design.