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Procedia Technology 12 (2014) 112 – 118

The 7th International Conference Interdisciplinarity in Engineering (INTER-ENG 2013)

Signal processing using FPGA structures

Zoltan German-Salloa,*
a
“Petru Maior” University of Tirgu-Mures, str. Nicolae Iorga nr 1 540088, Romania

Abstract

This work describes a Virtex-II implementation of a digital signal processing module for filtering data signals. The aim of any
filtering process is to have a clean signal for analysis and interpretation.A synthesized noisy signal (with known noise) will be
used as input to test the modules implemented on FPGA. The Xilinx System Generator Environment will be used in simulation
and discrete wavelet transform based filter synthesis, respectively for hardware co-simulation. In order to evaluate the filtering
procedure signal to noise ratio and RMS error are measured and compared at different noise levels and different analyzing
functions (wavelets).

© 2013 The Authors.Published by Elsevier B.V.

© 2013 The
Selection andAuthors. Published
peer-review under by Elsevier Ltd.
responsibility of Department of Electrical and Computer Engineering, Faculty of Engineering,
Selection and peer-review under responsibility
“Petru Maior” University of Tîrgu Mureș. of the Petru Maior University of Tirgu Mures.

Keywords: Type your keywords here, separated by semicolons ;

1. Introduction

A field programmable gate array (FPGA) is a general-purpose integrated circuit that is programmedor
reprogrammedby the designer, even after it has been deployed into a system. FPGA is a good testing platform for
evaluating and implementing signal processing algorithms due to its programmability, configurability, low cost, high
logic density and high reliability [1] [7].FPGAs have beenused widely, for implementation of various algorithms of
diverse complexity. With uncountable built-in functions as well as toolboxextensions, MATLAB is an excellent tool
for algorithmdevelopment and data analysis. A great majority of thealgorithms used today in DSP originate as

* Corresponding author. Tel.: +0-040-740-251344.

E-mail address:[email protected]

2212-0173 © 2013 The Authors. Published by Elsevier Ltd.

Selection and peer-review under responsibility of the Petru Maior University of Tirgu Mures.
doi:10.1016/j.protcy.2013.12.463
 Zoltan German-Sallo / Procedia Technology 12 (2014) 112 – 118 113

MATLAB models.Simulink is a graphical tool, which lets a user graphically designthe architecture and simulate the
timing and behavior of the wholesystem. The connection between FPGAs and MATLABmodels can be made by
Xilinx SystemGenerator (XSG). XSG is a widely used great tool which offers block libraries that plugs into
Simulink tool (containing bit-trueand cycle-accurate models of their FPGAs), thatenables the use of the model-based
designenvironment Simulink for FPGA design. It is a system-levelmodeling tool in which designs are captured in the
DSP friendlySimulink modeling environment using a Xilinx specific Blockset [8].All of the downstream FPGA
implementation steps includingsynthesis and place and route are automatically performed togenerate an FPGA
programming file. An FPGA is programmed by downloading a configuration program called a bitstream into static
on-chip random-access memory [9].
Much like the object code for a microprocessor, this bitstream is the product of compilation tools that translate the
high-level abstractions produced by a designer into something low-level and executable. Many useful DSP
buildingblocks are provided in the Xilinx DSP blockset for Simulink. Also XSG provides many features such as
SystemResource Estimation (SRE) to take full advantage of the FPGA resources,Hardware Co-Simulation (HWC)
and accelerated simulation throughhardware in the loop co-simulation; which give many orders of simulation
performance increase.XSG allows the design of hardware system starting from a graphical high level Simulink
environment extends the traditional Hardware Description Language (HDL) design providing graphical modules,
and thus does not require a detailed knowledge of this complex language. A discrete wavelet transform based
filtering procedure implemented on FPGAs can be a very useful tool in digital signal processing. To implement a
such kind of application XSGprovides blocks for building the model and Simulink provides a test environment for
the design.

2. The discrete wavelet transform (DWT)

The 1D Discrete Wavelet Transform (1DDWT) is defined as representation of a signal through a discrete
dilations and translations of the analysingfunction, called wavelet [2]. In its most common form, the DWT employs
a dyadic grid and orthonormal wavelet basis functions.The following equation shows how wavelets are generated

\ j ,k t  2 j 2\ 2 j 2 t  k 
from the mother wavelet:

(1)

 
Wavelet decomposition is a linear expansion and it is expressed as

xt  ¦ ckM t  k   ¦ d k\ 2 j 2 t  k
f f

k f k f
(2)
where φ(t) is called the scaling function and ckand djk are the coarse and detail level expansion coefficients.The
implementation of wavelet theory is performed using filter banks. In applications one never has to deal directly with
the scaling or waveletfunctions, only with the coefficients of the associated filters in the filter banks Two main
methods exist for the implementation of 1DDWT, the traditional convolution-based implementation [3] and the
lifting-based implementation [4]. In the traditional implementation of DWT, a pair of finite impulse response filters
(FIR) is applied in parallel, high-pass and low-pass filter.The filters are finite impulse response (FIR) structures and
meet some certain mathematical requirements in order to have a perfect reconstruction after decomposition. Fig. 1
presents a second order DWT decomposition with the correspondent time-frequency frames
114 Zoltan German-Sallo / Procedia Technology 12 (2014) 112 – 118

HL
X

HLL
L

LL

LLLHLL HL H f
LLL

Fig.1. DWT structure for dyadic scale decomposition and the obtained time-frequency frames

After filtering, the coefficients are ordered using two dominant patterns, one that works as a smoothing filter
(like a moving average), and one pattern that works to bring out the data's so-called detail information. The pyramid
algorithm (Mallat) [2] computes the one dimensional convolution based DWT at different levels of resolution. The
1D-DWT is a two channel sub-band decomposition of an input signal X(n) that produces two sub-band coefficients
L(n) and H(n) for one-stage of decomposition.

3. The proposed procedure

The main idea in a wavelet based signal denoising is a procedure called wavelet shrinkage and thresholdingas
developed originally by Donoho et al.[5]. Wavelet shrinkage denoising means non-linear thresholding of (mostly
detail) coefficients in wavelet transform domain. The denoising using the wavelet transform is done by representing
the signal by a small number of coefficients [6] which are passed througha thresholding procedure[9]. The signal is
composed into L levels before thresholding is applied. If the details are small, they might be set to zero without
substantially affecting the main features of the data set.
The idea of thresholding, then, is to omit all coefficients that are less than a particular threshold. These
coefficients are used in an inverse wavelet transformation to reconstruct the data set. In this procedure the signal is
transformed, thresholded and inverse-transformed from the resulting coefficients. An appropriate threshold can

zero mean gaussian white noise with a variance of V 2 . The power spectral density of a white noise is theoretically
suppress noise present in a signal. The underlying model for the noisy signal is the superposition of the signal and a

constant with amplitude of V 2 along the whole frequency domain. To eliminate the noise, an algorithm will
determine which wavelet coefficients should be thresholded. Most simple nonlinear thresholding rules for wavelet-
based denoising assume that the wavelet coefficients areindependent. For denoising applications, generally soft
thresholding is used. It is assumed that the noise power is smaller than the signal power.Most simple nonlinear
thresholding rules for wavelet-based denoising assume that the wavelet coefficients areindependent.
 Zoltan German-Sallo / Procedia Technology 12 (2014) 112 – 118 115

X D1 T D1

A1 A1 T D2 ∑
Analysis Synthesis
A1 D2

Fig.2. The proposed DWT decomposition based filtering procedure

The proposed model realized in Simulink for a second level DWT decomposition based filtering is presented on
Fig. 2. The Xilinx System Generator, a high-performanc edesign tool, runs as part of Simulink. The System
Generator elements bundled as theXilinx Blockset, appear in the Simulink library browser.

Fig.3. The proposed Simulink model with the generated hardware co-simulation block

The chosen test signal has a rectangular shape as most of transmitted data signals and it is well suited for testing
the proposed filtering algorithms. Also, the input signal is a synthetic test signal with added noise. The power of
signal and noise are known, that allows computing filtering parameters. The thresholding procedure is applied only
to detail coefficients because we assume that the major part of noise is contained in these components. Our approach
applies the soft thresholding method and uses the so called universal threshold given by [8]

Thr V 2 logN 
1 2
(3)
116 Zoltan German-Sallo / Procedia Technology 12 (2014) 112 – 118

4. Results

The test signal, the Gaussian noise and the obtained noisy data signal are presented on Fig. 4. The filtered signal
was obtained after implementation in XSG and hardware co-simulation (filtering algorithm ran on FPGA structure).

Fig.4 The test signal, the noise, the noisy data and the filtered signals.

The noisy data signal filtering was carried out with different analysing functions (wavelets) and with different
levels of added noise in order to have a good evaluation of the filtering performances. The root mean square (RMS)

x 
error is defined as

 x 2filt
2 1 2
RMSerror orig (4)
 Zoltan German-Sallo / Procedia Technology 12 (2014) 112 – 118 117

Root mean squared error using different wavelet types

0.5
0.45
0.4
0.35
0.3
coif1
RMS

0.25
0.2 db3
0.15 db2
0.1 sym2
0.05
0
0.01 0.001 0.0001 0.00001
Noise power (%)

Fig.5. Root mean squared error using different wavelet types.

The signal to noise ratio (SNR) measured after filtering is defined, the estimated noise being the difference

SNR 10 logPfilt _ sig Pest _ noise

between the original and filtered signal.

(5)

The obtained SNR with different levels of added noise applying ‘db3’ type wavelet are presented on Fig. 6.

1.6

1.4

1.2

0.8 snr

0.6 error

0.4

0.2

0
0.01 0.001 0.0001 0.00001

Fig.6. The obtained signal to noise ratio.

The convolution-based 1-D DWT requires both a large number of arithmetic computations and a large memory
for storage.
118 Zoltan German-Sallo / Procedia Technology 12 (2014) 112 – 118

5. Conclusions and further work

The FPGA structure can be used as digital signal processing tool, for filtering, denoising and many other
applications. Simulink offers a great variety of designing, testing tools in a simply understandable manner. The
obtained results, the filtering procedure can be improved using other types of analyzing functions, thresholding
methods and threshold values. It is well known, that the analyzing functions shape must be appropriate to the
analyzed signal in order to have a good and efficient decomposition (few coefficients). For this, it is important to
choose analyzing function and the degree of decomposition according to the analyzed signal shape.
As all other systems, XSG has its own limitationswhich need to be addressed, before it can be used widely and
efficiently. Not all blocks from Simulink are available inXilinxBlockset. And there exists no way togenerate
hardware from models which use thebasic Simulink Blockset (apart from thoseprovided by the Xilinx). So though,
forsimulation purpose, Simulink blocks providegraphical block based design, the actualimplementation possible on
hardware is quitedifferent from it. This creates a big gap betweenmodeling and hardware design and as
such,sometimes greatly restricts the usefulness of the tool.System Generator requires a lot from thecomputer and the
generation step can be aproblem for larger models.
Working in System Generator, it is important to keep in mind that an FPGA has many degrees of freedom in
implementing signal processing functions, for example, the freedom to define data path widths throughout your
system and to employ many individual data processors (e.g., multiply-accumulate engines), depending on system
requirements. System Generator provides abstractions that allow you to design for an FPGA largely by thinking
about the algorithm you want to implement. However, the more you know about the underlying FPGA, the more
likely you are to exploit the unique capabilities an FPGA provides in achieving high performance
The blocks provided in Xilinx do not provide as muchflexibility as their counterparts in Simulink Blockset.Apart
from a need of different treatment for these blocks,this also puts a burden on the designer for having tocalculate
many design parameters and specifications suchas binary points etc for every block output, and also for constants
used in blocks. The number of blocks and functions of the blocks are alsolimited today. The time to simulate models
with components fromXilinxBlockset is longer than the time it takes tosimulate in Simulink. The simulation using
Simulink blocks is frame-based, which enables them to processhundred of pieces of data on one simulation step.
Blocksin Xilinx Blockset can only process one piece of data inone simulation step.
Still,using XSG inside Simulink forbit and cycle true simulations is an order of magnitudefaster than running the
same simulation through an HDLsimulator.

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